About the Execution of LoLa+red for UtilityControlRoom-PT-Z2T3N08
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 6712.724 | 325988.00 | 423188.00 | 1073.30 | TFFT???T??FTTTFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r487-tall-167912704001106.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is UtilityControlRoom-PT-Z2T3N08, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912704001106
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.3M
-rw-r--r-- 1 mcc users 19K Feb 26 14:42 CTLCardinality.txt
-rw-r--r-- 1 mcc users 104K Feb 26 14:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 26K Feb 26 14:40 CTLFireability.txt
-rw-r--r-- 1 mcc users 113K Feb 26 14:40 CTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 17:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 46K Feb 25 17:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 14K Feb 25 17:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 25 17:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 65K Feb 26 14:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 340K Feb 26 14:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 75K Feb 26 14:45 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 324K Feb 26 14:45 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.9K Feb 25 17:24 UpperBounds.txt
-rw-r--r-- 1 mcc users 6.1K Feb 25 17:24 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 93K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z2T3N08-CTLFireability-00
FORMULA_NAME UtilityControlRoom-PT-Z2T3N08-CTLFireability-01
FORMULA_NAME UtilityControlRoom-PT-Z2T3N08-CTLFireability-02
FORMULA_NAME UtilityControlRoom-PT-Z2T3N08-CTLFireability-03
FORMULA_NAME UtilityControlRoom-PT-Z2T3N08-CTLFireability-04
FORMULA_NAME UtilityControlRoom-PT-Z2T3N08-CTLFireability-05
FORMULA_NAME UtilityControlRoom-PT-Z2T3N08-CTLFireability-06
FORMULA_NAME UtilityControlRoom-PT-Z2T3N08-CTLFireability-07
FORMULA_NAME UtilityControlRoom-PT-Z2T3N08-CTLFireability-08
FORMULA_NAME UtilityControlRoom-PT-Z2T3N08-CTLFireability-09
FORMULA_NAME UtilityControlRoom-PT-Z2T3N08-CTLFireability-10
FORMULA_NAME UtilityControlRoom-PT-Z2T3N08-CTLFireability-11
FORMULA_NAME UtilityControlRoom-PT-Z2T3N08-CTLFireability-12
FORMULA_NAME UtilityControlRoom-PT-Z2T3N08-CTLFireability-13
FORMULA_NAME UtilityControlRoom-PT-Z2T3N08-CTLFireability-14
FORMULA_NAME UtilityControlRoom-PT-Z2T3N08-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679232730130
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-PT-Z2T3N08
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 13:32:11] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 13:32:11] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 13:32:11] [INFO ] Load time of PNML (sax parser for PT used): 41 ms
[2023-03-19 13:32:11] [INFO ] Transformed 140 places.
[2023-03-19 13:32:11] [INFO ] Transformed 216 transitions.
[2023-03-19 13:32:11] [INFO ] Parsed PT model containing 140 places and 216 transitions and 680 arcs in 98 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 13 ms.
[2023-03-19 13:32:11] [INFO ] Reduced 8 identical enabling conditions.
[2023-03-19 13:32:11] [INFO ] Reduced 8 identical enabling conditions.
[2023-03-19 13:32:11] [INFO ] Reduced 8 identical enabling conditions.
[2023-03-19 13:32:11] [INFO ] Reduced 8 identical enabling conditions.
Ensure Unique test removed 32 transitions
Reduce redundant transitions removed 32 transitions.
Support contains 140 out of 140 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 184/184 transitions.
Applied a total of 0 rules in 10 ms. Remains 140 /140 variables (removed 0) and now considering 184/184 (removed 0) transitions.
// Phase 1: matrix 184 rows 140 cols
[2023-03-19 13:32:11] [INFO ] Computed 19 place invariants in 21 ms
[2023-03-19 13:32:12] [INFO ] Implicit Places using invariants in 201 ms returned []
[2023-03-19 13:32:12] [INFO ] Invariant cache hit.
[2023-03-19 13:32:12] [INFO ] Implicit Places using invariants and state equation in 94 ms returned []
Implicit Place search using SMT with State Equation took 531 ms to find 0 implicit places.
[2023-03-19 13:32:12] [INFO ] Invariant cache hit.
[2023-03-19 13:32:12] [INFO ] Dead Transitions using invariants and state equation in 112 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 655 ms. Remains : 140/140 places, 184/184 transitions.
Support contains 140 out of 140 places after structural reductions.
[2023-03-19 13:32:12] [INFO ] Flatten gal took : 44 ms
[2023-03-19 13:32:12] [INFO ] Flatten gal took : 24 ms
[2023-03-19 13:32:12] [INFO ] Input system was already deterministic with 184 transitions.
Finished random walk after 1610 steps, including 0 resets, run visited all 45 properties in 90 ms. (steps per millisecond=17 )
[2023-03-19 13:32:12] [INFO ] Flatten gal took : 13 ms
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 17 ms
[2023-03-19 13:32:13] [INFO ] Input system was already deterministic with 184 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 184/184 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 124 transition count 168
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 124 transition count 168
Applied a total of 32 rules in 8 ms. Remains 124 /140 variables (removed 16) and now considering 168/184 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 124/140 places, 168/184 transitions.
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 9 ms
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 11 ms
[2023-03-19 13:32:13] [INFO ] Input system was already deterministic with 168 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 184/184 transitions.
Applied a total of 0 rules in 3 ms. Remains 140 /140 variables (removed 0) and now considering 184/184 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 140/140 places, 184/184 transitions.
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 18 ms
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 11 ms
[2023-03-19 13:32:13] [INFO ] Input system was already deterministic with 184 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 184/184 transitions.
Applied a total of 0 rules in 2 ms. Remains 140 /140 variables (removed 0) and now considering 184/184 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 140/140 places, 184/184 transitions.
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 8 ms
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 9 ms
[2023-03-19 13:32:13] [INFO ] Input system was already deterministic with 184 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 184/184 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 124 transition count 168
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 124 transition count 168
Applied a total of 32 rules in 6 ms. Remains 124 /140 variables (removed 16) and now considering 168/184 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 124/140 places, 168/184 transitions.
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 7 ms
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 7 ms
[2023-03-19 13:32:13] [INFO ] Input system was already deterministic with 168 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 184/184 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 124 transition count 168
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 124 transition count 168
Applied a total of 32 rules in 5 ms. Remains 124 /140 variables (removed 16) and now considering 168/184 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 124/140 places, 168/184 transitions.
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 12 ms
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 7 ms
[2023-03-19 13:32:13] [INFO ] Input system was already deterministic with 168 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 184/184 transitions.
Applied a total of 0 rules in 2 ms. Remains 140 /140 variables (removed 0) and now considering 184/184 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 140/140 places, 184/184 transitions.
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 6 ms
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 7 ms
[2023-03-19 13:32:13] [INFO ] Input system was already deterministic with 184 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 184/184 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 124 transition count 168
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 124 transition count 168
Applied a total of 32 rules in 5 ms. Remains 124 /140 variables (removed 16) and now considering 168/184 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 124/140 places, 168/184 transitions.
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 6 ms
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 7 ms
[2023-03-19 13:32:13] [INFO ] Input system was already deterministic with 168 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 184/184 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 124 transition count 168
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 124 transition count 168
Applied a total of 32 rules in 5 ms. Remains 124 /140 variables (removed 16) and now considering 168/184 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 124/140 places, 168/184 transitions.
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 6 ms
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 6 ms
[2023-03-19 13:32:13] [INFO ] Input system was already deterministic with 168 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 184/184 transitions.
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 15 place count 125 transition count 169
Iterating global reduction 0 with 15 rules applied. Total rules applied 30 place count 125 transition count 169
Applied a total of 30 rules in 4 ms. Remains 125 /140 variables (removed 15) and now considering 169/184 (removed 15) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 125/140 places, 169/184 transitions.
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 6 ms
[2023-03-19 13:32:13] [INFO ] Input system was already deterministic with 169 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 184/184 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 124 transition count 168
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 124 transition count 168
Applied a total of 32 rules in 4 ms. Remains 124 /140 variables (removed 16) and now considering 168/184 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 124/140 places, 168/184 transitions.
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 6 ms
[2023-03-19 13:32:13] [INFO ] Input system was already deterministic with 168 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 140/140 places, 184/184 transitions.
Drop transitions removed 29 transitions
Trivial Post-agglo rules discarded 29 transitions
Performed 29 trivial Post agglomeration. Transition count delta: 29
Iterating post reduction 0 with 29 rules applied. Total rules applied 29 place count 140 transition count 155
Reduce places removed 29 places and 0 transitions.
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 1 with 44 rules applied. Total rules applied 73 place count 111 transition count 140
Performed 15 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 15 Pre rules applied. Total rules applied 73 place count 111 transition count 125
Deduced a syphon composed of 15 places in 0 ms
Reduce places removed 15 places and 0 transitions.
Iterating global reduction 2 with 30 rules applied. Total rules applied 103 place count 96 transition count 125
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 104 place count 95 transition count 124
Iterating global reduction 2 with 1 rules applied. Total rules applied 105 place count 95 transition count 124
Performed 8 Post agglomeration using F-continuation condition.Transition count delta: 8
Deduced a syphon composed of 8 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 2 with 16 rules applied. Total rules applied 121 place count 87 transition count 116
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 2 with 14 rules applied. Total rules applied 135 place count 80 transition count 109
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 136 place count 80 transition count 108
Applied a total of 136 rules in 29 ms. Remains 80 /140 variables (removed 60) and now considering 108/184 (removed 76) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 29 ms. Remains : 80/140 places, 108/184 transitions.
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 3 ms
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 4 ms
[2023-03-19 13:32:13] [INFO ] Input system was already deterministic with 108 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 184/184 transitions.
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 15 place count 125 transition count 169
Iterating global reduction 0 with 15 rules applied. Total rules applied 30 place count 125 transition count 169
Applied a total of 30 rules in 3 ms. Remains 125 /140 variables (removed 15) and now considering 169/184 (removed 15) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 125/140 places, 169/184 transitions.
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 6 ms
[2023-03-19 13:32:13] [INFO ] Input system was already deterministic with 169 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 184/184 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 124 transition count 168
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 124 transition count 168
Applied a total of 32 rules in 3 ms. Remains 124 /140 variables (removed 16) and now considering 168/184 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 124/140 places, 168/184 transitions.
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 6 ms
[2023-03-19 13:32:13] [INFO ] Input system was already deterministic with 168 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 140/140 places, 184/184 transitions.
Performed 32 Post agglomeration using F-continuation condition.Transition count delta: 32
Iterating post reduction 0 with 32 rules applied. Total rules applied 32 place count 140 transition count 152
Reduce places removed 32 places and 0 transitions.
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 48 rules applied. Total rules applied 80 place count 108 transition count 136
Performed 16 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 16 Pre rules applied. Total rules applied 80 place count 108 transition count 120
Deduced a syphon composed of 16 places in 0 ms
Reduce places removed 16 places and 0 transitions.
Iterating global reduction 2 with 32 rules applied. Total rules applied 112 place count 92 transition count 120
Performed 8 Post agglomeration using F-continuation condition.Transition count delta: 8
Deduced a syphon composed of 8 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 2 with 16 rules applied. Total rules applied 128 place count 84 transition count 112
Applied a total of 128 rules in 11 ms. Remains 84 /140 variables (removed 56) and now considering 112/184 (removed 72) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 84/140 places, 112/184 transitions.
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 4 ms
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 4 ms
[2023-03-19 13:32:13] [INFO ] Input system was already deterministic with 112 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 184/184 transitions.
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 15 place count 125 transition count 169
Iterating global reduction 0 with 15 rules applied. Total rules applied 30 place count 125 transition count 169
Applied a total of 30 rules in 3 ms. Remains 125 /140 variables (removed 15) and now considering 169/184 (removed 15) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 125/140 places, 169/184 transitions.
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:32:13] [INFO ] Input system was already deterministic with 169 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 184/184 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 124 transition count 168
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 124 transition count 168
Applied a total of 32 rules in 2 ms. Remains 124 /140 variables (removed 16) and now considering 168/184 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 124/140 places, 168/184 transitions.
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 5 ms
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 6 ms
[2023-03-19 13:32:13] [INFO ] Input system was already deterministic with 168 transitions.
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 10 ms
[2023-03-19 13:32:13] [INFO ] Flatten gal took : 9 ms
[2023-03-19 13:32:13] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 10 ms.
[2023-03-19 13:32:13] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 140 places, 184 transitions and 552 arcs took 1 ms.
Total runtime 2293 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT UtilityControlRoom-PT-Z2T3N08
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability
FORMULA UtilityControlRoom-PT-Z2T3N08-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N08-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N08-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N08-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N08-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N08-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N08-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N08-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N08-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N08-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-PT-Z2T3N08-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679233056118
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:463
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 18 (type EXCL) for 17 UtilityControlRoom-PT-Z2T3N08-CTLFireability-03
lola: time limit : 116 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 76 (type FNDP) for 6 UtilityControlRoom-PT-Z2T3N08-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type EQUN) for 6 UtilityControlRoom-PT-Z2T3N08-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 79 (type SRCH) for 6 UtilityControlRoom-PT-Z2T3N08-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 76 (type FNDP) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-02
lola: result : true
lola: fired transitions : 8
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 77 (type EQUN) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-02 (obsolete)
lola: CANCELED task # 79 (type SRCH) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-02 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 82 (type SKEL/FNDP) for 62 UtilityControlRoom-PT-Z2T3N08-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 84 (type SKEL/EQUN) for 62 UtilityControlRoom-PT-Z2T3N08-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 85 (type SKEL/SRCH) for 62 UtilityControlRoom-PT-Z2T3N08-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 85 (type SKEL/SRCH) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-14
lola: result : true
lola: markings : 7
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: CANCELED task # 82 (type FNDP) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-14 (obsolete)
lola: CANCELED task # 84 (type EQUN) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-14 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 82 (type SKEL/FNDP) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-14
lola: result : true
lola: fired transitions : 5
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/373/CTLFireability-84.sara.
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 88 (type FNDP) for 62 UtilityControlRoom-PT-Z2T3N08-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 89 (type EQUN) for 62 UtilityControlRoom-PT-Z2T3N08-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 91 (type SRCH) for 62 UtilityControlRoom-PT-Z2T3N08-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 84 (type SKEL/EQUN) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-14
lola: result : true
lola: FINISHED task # 88 (type FNDP) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-14
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 91 (type SRCH) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-14
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 89 (type EQUN) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-14 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
sara: try reading problem file /home/mcc/execution/373/CTLFireability-89.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 89 (type EQUN) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-14
lola: result : true
lola: FINISHED task # 18 (type EXCL) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-03
lola: result : true
lola: markings : 604915
lola: fired transitions : 1191040
lola: time used : 3.000000
lola: memory pages used : 3
lola: LAUNCH task # 74 (type EXCL) for 73 UtilityControlRoom-PT-Z2T3N08-CTLFireability-15
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: FINISHED task # 74 (type EXCL) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-15
lola: result : true
lola: markings : 58
lola: fired transitions : 179
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 65 (type EXCL) for 62 UtilityControlRoom-PT-Z2T3N08-CTLFireability-14
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 65 (type EXCL) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-14
lola: result : false
lola: markings : 113
lola: fired transitions : 124
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 57 (type EXCL) for 56 UtilityControlRoom-PT-Z2T3N08-CTLFireability-12
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EXCL) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-12
lola: result : true
lola: markings : 64
lola: fired transitions : 110
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 53 UtilityControlRoom-PT-Z2T3N08-CTLFireability-11
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-11
lola: result : true
lola: markings : 66
lola: fired transitions : 80
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 UtilityControlRoom-PT-Z2T3N08-CTLFireability-09
lola: time limit : 239 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T3N08-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-14: DISJ false DISJ
UtilityControlRoom-PT-Z2T3N08-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T3N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-02: DISJ 0 2 0 0 4 0 0 3
UtilityControlRoom-PT-Z2T3N08-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-06: DISJ 0 3 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-13: EGEF 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 2/239 2/32 UtilityControlRoom-PT-Z2T3N08-CTLFireability-09 307700 m, 61540 m/sec, 815240 t fired, .
Time elapsed: 6 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
sara: try reading problem file /home/mcc/execution/373/CTLFireability-77.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T3N08-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-14: DISJ false DISJ
UtilityControlRoom-PT-Z2T3N08-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T3N08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-02: DISJ 0 2 0 0 4 0 0 3
UtilityControlRoom-PT-Z2T3N08-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-06: DISJ 0 3 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-13: EGEF 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 7/239 4/32 UtilityControlRoom-PT-Z2T3N08-CTLFireability-09 837637 m, 105987 m/sec, 2448621 t fired, .
Time elapsed: 11 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T3N08-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-14: DISJ false DISJ
UtilityControlRoom-PT-Z2T3N08-CTLFireability-15: CTL true CTL model checker
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UtilityControlRoom-PT-Z2T3N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-06: DISJ 0 0 1 0 4 0 0 1
UtilityControlRoom-PT-Z2T3N08-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 AGEF EXCL 33/1105 30/32 UtilityControlRoom-PT-Z2T3N08-CTLFireability-06 7705266 m, 187180 m/sec, 20543522 t fired, .
Time elapsed: 316 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 39 (type EXCL) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T3N08-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-01: CTL false CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-13: EGEF true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-14: DISJ false DISJ
UtilityControlRoom-PT-Z2T3N08-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T3N08-CTLFireability-02: DISJ 0 1 0 0 6 0 0 2
UtilityControlRoom-PT-Z2T3N08-CTLFireability-04: CONJ 0 0 0 0 3 0 1 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-06: DISJ 0 0 0 0 4 0 1 1
UtilityControlRoom-PT-Z2T3N08-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T3N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 51 (type EXCL) for 50 UtilityControlRoom-PT-Z2T3N08-CTLFireability-10
lola: time limit : 1639 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-10
lola: result : false
lola: markings : 100
lola: fired transitions : 322
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 9 (type EXCL) for 6 UtilityControlRoom-PT-Z2T3N08-CTLFireability-02
lola: time limit : 3279 sec
lola: memory limit: 32 pages
lola: FINISHED task # 9 (type EXCL) for UtilityControlRoom-PT-Z2T3N08-CTLFireability-02
lola: result : false
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T3N08-CTLFireability-00: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-01: CTL false CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-02: DISJ false DISJ
UtilityControlRoom-PT-Z2T3N08-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-04: CONJ unknown CONJ
UtilityControlRoom-PT-Z2T3N08-CTLFireability-05: CTL unknown AGGR
UtilityControlRoom-PT-Z2T3N08-CTLFireability-06: DISJ unknown DISJ
UtilityControlRoom-PT-Z2T3N08-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-08: CTL unknown AGGR
UtilityControlRoom-PT-Z2T3N08-CTLFireability-09: CTL unknown AGGR
UtilityControlRoom-PT-Z2T3N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-13: EGEF true CTL model checker
UtilityControlRoom-PT-Z2T3N08-CTLFireability-14: DISJ false DISJ
UtilityControlRoom-PT-Z2T3N08-CTLFireability-15: CTL true CTL model checker
Time elapsed: 321 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z2T3N08"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is UtilityControlRoom-PT-Z2T3N08, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912704001106"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z2T3N08.tgz
mv UtilityControlRoom-PT-Z2T3N08 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;