Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703901042.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is UtilityControlRoom-COL-Z4T3N10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703901042
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 528K
-rw-r--r-- 1 mcc users 8.4K Feb 26 14:42 CTLCardinality.txt
-rw-r--r-- 1 mcc users 79K Feb 26 14:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.8K Feb 26 14:37 CTLFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 26 14:37 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.4K Feb 25 17:25 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 17:25 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Feb 25 17:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:25 LTLFireability.xml
-rw-r--r-- 1 mcc users 18K Feb 26 14:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 166K Feb 26 14:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 14:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 72K Feb 26 14:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 17:25 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 17:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 29K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-00
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-01
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-02
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-03
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-04
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-05
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-06
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-07
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-08
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-09
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-10
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-11
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-12
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-13
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-14
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679230459829

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-COL-Z4T3N10
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 12:54:21] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 12:54:21] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 12:54:21] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-19 12:54:21] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-19 12:54:21] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 600 ms
[2023-03-19 12:54:21] [INFO ] Imported 13 HL places and 12 HL transitions for a total of 376 PT places and 750.0 transition bindings in 14 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 11 ms.
[2023-03-19 12:54:21] [INFO ] Built PT skeleton of HLPN with 13 places and 12 transitions 37 arcs in 4 ms.
[2023-03-19 12:54:21] [INFO ] Skeletonized 16 HLPN properties in 2 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Remains 8 properties that can be checked using skeleton over-approximation.
Ensure Unique test removed 1 transitions
Reduce redundant transitions removed 1 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Finished random walk after 140 steps, including 0 resets, run visited all 12 properties in 15 ms. (steps per millisecond=9 )
[2023-03-19 12:54:22] [INFO ] Flatten gal took : 13 ms
[2023-03-19 12:54:22] [INFO ] Flatten gal took : 4 ms
Transition timeout forces synchronizations/join behavior on parameter c of sort Cli
Domain [Cli(10), Z(4), Z(4)] of place MovetoZ breaks symmetries in sort Z
[2023-03-19 12:54:22] [INFO ] Unfolded HLPN to a Petri net with 376 places and 750 transitions 2410 arcs in 21 ms.
[2023-03-19 12:54:22] [INFO ] Unfolded 16 HLPN properties in 2 ms.
[2023-03-19 12:54:22] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 12:54:22] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 12:54:22] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 12:54:22] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 12:54:22] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 12:54:22] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 12:54:22] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 12:54:22] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-19 12:54:22] [INFO ] Reduced 30 identical enabling conditions.
Ensure Unique test removed 160 transitions
Reduce redundant transitions removed 160 transitions.
Support contains 376 out of 376 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Applied a total of 0 rules in 10 ms. Remains 376 /376 variables (removed 0) and now considering 590/590 (removed 0) transitions.
// Phase 1: matrix 590 rows 376 cols
[2023-03-19 12:54:22] [INFO ] Computed 23 place invariants in 31 ms
[2023-03-19 12:54:22] [INFO ] Implicit Places using invariants in 225 ms returned []
[2023-03-19 12:54:22] [INFO ] Invariant cache hit.
[2023-03-19 12:54:22] [INFO ] Implicit Places using invariants and state equation in 213 ms returned []
Implicit Place search using SMT with State Equation took 460 ms to find 0 implicit places.
[2023-03-19 12:54:22] [INFO ] Invariant cache hit.
[2023-03-19 12:54:22] [INFO ] Dead Transitions using invariants and state equation in 270 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 743 ms. Remains : 376/376 places, 590/590 transitions.
Support contains 376 out of 376 places after structural reductions.
[2023-03-19 12:54:23] [INFO ] Flatten gal took : 75 ms
[2023-03-19 12:54:23] [INFO ] Flatten gal took : 81 ms
[2023-03-19 12:54:24] [INFO ] Input system was already deterministic with 590 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 181 ms. (steps per millisecond=55 ) properties (out of 36) seen :35
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 282 ms. (steps per millisecond=35 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-19 12:54:24] [INFO ] Invariant cache hit.
[2023-03-19 12:54:24] [INFO ] After 61ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-19 12:54:25] [INFO ] Flatten gal took : 43 ms
[2023-03-19 12:54:25] [INFO ] Flatten gal took : 65 ms
[2023-03-19 12:54:25] [INFO ] Input system was already deterministic with 590 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Performed 160 Post agglomeration using F-continuation condition.Transition count delta: 160
Iterating post reduction 0 with 160 rules applied. Total rules applied 160 place count 376 transition count 430
Reduce places removed 160 places and 0 transitions.
Ensure Unique test removed 40 transitions
Reduce isomorphic transitions removed 40 transitions.
Iterating post reduction 1 with 200 rules applied. Total rules applied 360 place count 216 transition count 390
Performed 40 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 40 Pre rules applied. Total rules applied 360 place count 216 transition count 350
Deduced a syphon composed of 40 places in 0 ms
Reduce places removed 40 places and 0 transitions.
Iterating global reduction 2 with 80 rules applied. Total rules applied 440 place count 176 transition count 350
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 2 with 20 rules applied. Total rules applied 460 place count 166 transition count 340
Applied a total of 460 rules in 55 ms. Remains 166 /376 variables (removed 210) and now considering 340/590 (removed 250) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 55 ms. Remains : 166/376 places, 340/590 transitions.
[2023-03-19 12:54:25] [INFO ] Flatten gal took : 15 ms
[2023-03-19 12:54:25] [INFO ] Flatten gal took : 15 ms
[2023-03-19 12:54:25] [INFO ] Input system was already deterministic with 340 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 11 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 12:54:25] [INFO ] Flatten gal took : 17 ms
[2023-03-19 12:54:25] [INFO ] Flatten gal took : 17 ms
[2023-03-19 12:54:26] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 11 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 16 ms
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 17 ms
[2023-03-19 12:54:26] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 18 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 18 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 15 ms
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 17 ms
[2023-03-19 12:54:26] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Performed 40 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 40 Pre rules applied. Total rules applied 0 place count 376 transition count 550
Deduced a syphon composed of 40 places in 0 ms
Reduce places removed 40 places and 0 transitions.
Iterating global reduction 0 with 80 rules applied. Total rules applied 80 place count 336 transition count 550
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 0 with 20 rules applied. Total rules applied 100 place count 326 transition count 540
Applied a total of 100 rules in 20 ms. Remains 326 /376 variables (removed 50) and now considering 540/590 (removed 50) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 20 ms. Remains : 326/376 places, 540/590 transitions.
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 14 ms
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 15 ms
[2023-03-19 12:54:26] [INFO ] Input system was already deterministic with 540 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Drop transitions removed 160 transitions
Trivial Post-agglo rules discarded 160 transitions
Performed 160 trivial Post agglomeration. Transition count delta: 160
Iterating post reduction 0 with 160 rules applied. Total rules applied 160 place count 376 transition count 430
Reduce places removed 160 places and 0 transitions.
Ensure Unique test removed 40 transitions
Reduce isomorphic transitions removed 40 transitions.
Iterating post reduction 1 with 200 rules applied. Total rules applied 360 place count 216 transition count 390
Performed 40 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 40 Pre rules applied. Total rules applied 360 place count 216 transition count 350
Deduced a syphon composed of 40 places in 1 ms
Reduce places removed 40 places and 0 transitions.
Iterating global reduction 2 with 80 rules applied. Total rules applied 440 place count 176 transition count 350
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 443 place count 173 transition count 230
Iterating global reduction 2 with 3 rules applied. Total rules applied 446 place count 173 transition count 230
Discarding 30 places :
Symmetric choice reduction at 2 with 30 rule applications. Total rules 476 place count 143 transition count 200
Iterating global reduction 2 with 30 rules applied. Total rules applied 506 place count 143 transition count 200
Discarding 30 places :
Symmetric choice reduction at 2 with 30 rule applications. Total rules 536 place count 113 transition count 140
Iterating global reduction 2 with 30 rules applied. Total rules applied 566 place count 113 transition count 140
Discarding 30 places :
Symmetric choice reduction at 2 with 30 rule applications. Total rules 596 place count 83 transition count 110
Iterating global reduction 2 with 30 rules applied. Total rules applied 626 place count 83 transition count 110
Ensure Unique test removed 30 transitions
Reduce isomorphic transitions removed 30 transitions.
Iterating post reduction 2 with 30 rules applied. Total rules applied 656 place count 83 transition count 80
Performed 10 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 10 Pre rules applied. Total rules applied 656 place count 83 transition count 70
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 3 with 20 rules applied. Total rules applied 676 place count 73 transition count 70
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 3 with 20 rules applied. Total rules applied 696 place count 63 transition count 60
Applied a total of 696 rules in 23 ms. Remains 63 /376 variables (removed 313) and now considering 60/590 (removed 530) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 23 ms. Remains : 63/376 places, 60/590 transitions.
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 1 ms
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 2 ms
[2023-03-19 12:54:26] [INFO ] Input system was already deterministic with 60 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 7 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 12 ms
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 13 ms
[2023-03-19 12:54:26] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 8 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 12 ms
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 13 ms
[2023-03-19 12:54:26] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 4 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 13 ms
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 13 ms
[2023-03-19 12:54:26] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 6 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 13 ms
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 17 ms
[2023-03-19 12:54:26] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Discarding 120 places :
Symmetric choice reduction at 0 with 120 rule applications. Total rules 120 place count 256 transition count 470
Iterating global reduction 0 with 120 rules applied. Total rules applied 240 place count 256 transition count 470
Applied a total of 240 rules in 7 ms. Remains 256 /376 variables (removed 120) and now considering 470/590 (removed 120) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 256/376 places, 470/590 transitions.
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 13 ms
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 14 ms
[2023-03-19 12:54:26] [INFO ] Input system was already deterministic with 470 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Applied a total of 0 rules in 2 ms. Remains 376 /376 variables (removed 0) and now considering 590/590 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 376/376 places, 590/590 transitions.
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 15 ms
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 17 ms
[2023-03-19 12:54:26] [INFO ] Input system was already deterministic with 590 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Applied a total of 0 rules in 2 ms. Remains 376 /376 variables (removed 0) and now considering 590/590 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 376/376 places, 590/590 transitions.
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 16 ms
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 20 ms
[2023-03-19 12:54:26] [INFO ] Input system was already deterministic with 590 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Applied a total of 0 rules in 2 ms. Remains 376 /376 variables (removed 0) and now considering 590/590 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 376/376 places, 590/590 transitions.
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 16 ms
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 17 ms
[2023-03-19 12:54:26] [INFO ] Input system was already deterministic with 590 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Performed 160 Post agglomeration using F-continuation condition.Transition count delta: 160
Iterating post reduction 0 with 160 rules applied. Total rules applied 160 place count 376 transition count 430
Reduce places removed 160 places and 0 transitions.
Ensure Unique test removed 40 transitions
Reduce isomorphic transitions removed 40 transitions.
Iterating post reduction 1 with 200 rules applied. Total rules applied 360 place count 216 transition count 390
Performed 40 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 40 Pre rules applied. Total rules applied 360 place count 216 transition count 350
Deduced a syphon composed of 40 places in 0 ms
Reduce places removed 40 places and 0 transitions.
Iterating global reduction 2 with 80 rules applied. Total rules applied 440 place count 176 transition count 350
Applied a total of 440 rules in 17 ms. Remains 176 /376 variables (removed 200) and now considering 350/590 (removed 240) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 17 ms. Remains : 176/376 places, 350/590 transitions.
[2023-03-19 12:54:26] [INFO ] Flatten gal took : 10 ms
[2023-03-19 12:54:27] [INFO ] Flatten gal took : 10 ms
[2023-03-19 12:54:27] [INFO ] Input system was already deterministic with 350 transitions.
Starting structural reductions in LTL mode, iteration 0 : 376/376 places, 590/590 transitions.
Applied a total of 0 rules in 2 ms. Remains 376 /376 variables (removed 0) and now considering 590/590 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 376/376 places, 590/590 transitions.
[2023-03-19 12:54:27] [INFO ] Flatten gal took : 17 ms
[2023-03-19 12:54:27] [INFO ] Flatten gal took : 20 ms
[2023-03-19 12:54:27] [INFO ] Input system was already deterministic with 590 transitions.
[2023-03-19 12:54:27] [INFO ] Flatten gal took : 47 ms
[2023-03-19 12:54:27] [INFO ] Flatten gal took : 46 ms
[2023-03-19 12:54:27] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 27 ms.
[2023-03-19 12:54:27] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 376 places, 590 transitions and 1770 arcs took 2 ms.
Total runtime 6666 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT UtilityControlRoom-COL-Z4T3N10
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/372
CTLFireability

FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679230755117

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/372/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/372/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/372/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
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lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
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lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
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lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:253
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lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
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lola: Rule S: 0 transitions removed,0 places removed
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lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 16 (type EXCL) for 15 UtilityControlRoom-COL-Z4T3N10-CTLFireability-05
lola: time limit : 162 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:730
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lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: rewrite Frontend/Parser/formula_rewrite.k:809
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

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UtilityControlRoom-COL-Z4T3N10-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-COL-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-05: AGEF 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-COL-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-12: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-13: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 5/199 4/32 UtilityControlRoom-COL-Z4T3N10-CTLFireability-05 637989 m, 127597 m/sec, 1584704 t fired, .

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UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 10/199 7/32 UtilityControlRoom-COL-Z4T3N10-CTLFireability-05 1289241 m, 130250 m/sec, 3315589 t fired, .

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16 AGEF EXCL 15/199 10/32 UtilityControlRoom-COL-Z4T3N10-CTLFireability-05 1912873 m, 124726 m/sec, 5015009 t fired, .

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UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 20/199 13/32 UtilityControlRoom-COL-Z4T3N10-CTLFireability-05 2515616 m, 120548 m/sec, 6687924 t fired, .

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UtilityControlRoom-COL-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-12: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-13: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 AGEF EXCL 25/199 16/32 UtilityControlRoom-COL-Z4T3N10-CTLFireability-05 3113034 m, 119483 m/sec, 8351391 t fired, .

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UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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UtilityControlRoom-COL-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-COL-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-09: CTL false CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-12: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-13: EFEG true state space /EFEG
UtilityControlRoom-COL-Z4T3N10-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T3N10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 45/3364 31/32 UtilityControlRoom-COL-Z4T3N10-CTLFireability-04 7233651 m, 146020 m/sec, 13670988 t fired, .

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lola: CANCELED task # 13 (type EXCL) for UtilityControlRoom-COL-Z4T3N10-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-COL-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-09: CTL false CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-12: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-13: EFEG true state space /EFEG
UtilityControlRoom-COL-Z4T3N10-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-COL-Z4T3N10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-05: AGEF 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T3N10-CTLFireability-00: EFEG true state space /EFEG
UtilityControlRoom-COL-Z4T3N10-CTLFireability-01: CTL true CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-02: CTL false CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-03: CTL unknown AGGR
UtilityControlRoom-COL-Z4T3N10-CTLFireability-04: CTL unknown AGGR
UtilityControlRoom-COL-Z4T3N10-CTLFireability-05: AGEF unknown AGGR
UtilityControlRoom-COL-Z4T3N10-CTLFireability-06: CTL false CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-08: CTL unknown AGGR
UtilityControlRoom-COL-Z4T3N10-CTLFireability-09: CTL false CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-11: CTL false CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-12: CONJ false CTL model checker
UtilityControlRoom-COL-Z4T3N10-CTLFireability-13: EFEG true state space /EFEG
UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL unknown AGGR
UtilityControlRoom-COL-Z4T3N10-CTLFireability-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-COL-Z4T3N10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is UtilityControlRoom-COL-Z4T3N10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703901042"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-COL-Z4T3N10.tgz
mv UtilityControlRoom-COL-Z4T3N10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;