About the Execution of LoLa+red for TwoPhaseLocking-PT-nC10000vD
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4063.479 | 108733.00 | 91907.00 | 651.40 | FF??T???FT?FT?T? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703700930.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is TwoPhaseLocking-PT-nC10000vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703700930
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 476K
-rw-r--r-- 1 mcc users 6.8K Feb 25 17:45 CTLCardinality.txt
-rw-r--r-- 1 mcc users 66K Feb 25 17:45 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.2K Feb 25 17:44 CTLFireability.txt
-rw-r--r-- 1 mcc users 44K Feb 25 17:44 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 17:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 17:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 25 17:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 160K Feb 25 17:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.9K Feb 25 17:46 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Feb 25 17:46 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:24 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:24 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679225626920
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC10000vD
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 11:33:48] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 11:33:48] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 11:33:48] [INFO ] Load time of PNML (sax parser for PT used): 16 ms
[2023-03-19 11:33:48] [INFO ] Transformed 8 places.
[2023-03-19 11:33:48] [INFO ] Transformed 6 transitions.
[2023-03-19 11:33:48] [INFO ] Parsed PT model containing 8 places and 6 transitions and 18 arcs in 68 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Support contains 8 out of 8 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 7 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
// Phase 1: matrix 6 rows 8 cols
[2023-03-19 11:33:48] [INFO ] Computed 3 place invariants in 3 ms
[2023-03-19 11:33:48] [INFO ] Implicit Places using invariants in 130 ms returned []
[2023-03-19 11:33:48] [INFO ] Invariant cache hit.
[2023-03-19 11:33:48] [INFO ] Implicit Places using invariants and state equation in 30 ms returned []
Implicit Place search using SMT with State Equation took 182 ms to find 0 implicit places.
[2023-03-19 11:33:48] [INFO ] Invariant cache hit.
[2023-03-19 11:33:48] [INFO ] Dead Transitions using invariants and state equation in 24 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 214 ms. Remains : 8/8 places, 6/6 transitions.
Support contains 8 out of 8 places after structural reductions.
[2023-03-19 11:33:48] [INFO ] Flatten gal took : 12 ms
[2023-03-19 11:33:48] [INFO ] Flatten gal took : 3 ms
[2023-03-19 11:33:48] [INFO ] Input system was already deterministic with 6 transitions.
Incomplete random walk after 10003 steps, including 1 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 22) seen :8
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 51 ms. (steps per millisecond=196 ) properties (out of 14) seen :12
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 35 ms. (steps per millisecond=285 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 54 ms. (steps per millisecond=185 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-19 11:33:49] [INFO ] Invariant cache hit.
[2023-03-19 11:33:49] [INFO ] [Real]Absence check using 3 positive place invariants in 7 ms returned sat
[2023-03-19 11:33:49] [INFO ] After 40ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:1
[2023-03-19 11:33:49] [INFO ] [Nat]Absence check using 3 positive place invariants in 1 ms returned sat
[2023-03-19 11:33:49] [INFO ] After 8ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :1
[2023-03-19 11:33:49] [INFO ] After 13ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :1
Attempting to minimize the solution found.
Minimization took 5 ms.
[2023-03-19 11:33:49] [INFO ] After 60ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :1
Fused 2 Parikh solutions to 1 different solutions.
Finished Parikh walk after 19998 steps, including 0 resets, run visited all 1 properties in 51 ms. (steps per millisecond=392 )
Parikh walk visited 1 properties in 51 ms.
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:33:49] [INFO ] Input system was already deterministic with 6 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 2 place count 7 transition count 4
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Applied a total of 4 rules in 4 ms. Remains 6 /8 variables (removed 2) and now considering 4/6 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 6/8 places, 4/6 transitions.
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:33:49] [INFO ] Input system was already deterministic with 4 transitions.
Finished random walk after 5001 steps, including 0 resets, run visited all 1 properties in 4 ms. (steps per millisecond=1250 )
FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-00 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 2 place count 7 transition count 4
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Applied a total of 4 rules in 2 ms. Remains 6 /8 variables (removed 2) and now considering 4/6 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 6/8 places, 4/6 transitions.
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:33:49] [INFO ] Input system was already deterministic with 4 transitions.
Finished random walk after 5001 steps, including 0 resets, run visited all 1 properties in 3 ms. (steps per millisecond=1667 )
FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-01 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 8 transition count 5
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 2 place count 7 transition count 5
Applied a total of 2 rules in 1 ms. Remains 7 /8 variables (removed 1) and now considering 5/6 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 7/8 places, 5/6 transitions.
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:33:49] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:33:49] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:33:49] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:33:49] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:33:49] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:33:49] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:33:49] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 2 place count 7 transition count 4
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Applied a total of 4 rules in 2 ms. Remains 6 /8 variables (removed 2) and now considering 4/6 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 6/8 places, 4/6 transitions.
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:33:49] [INFO ] Input system was already deterministic with 4 transitions.
Finished random walk after 5001 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=2500 )
FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-09 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:33:49] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 2 place count 7 transition count 4
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Applied a total of 4 rules in 2 ms. Remains 6 /8 variables (removed 2) and now considering 4/6 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 6/8 places, 4/6 transitions.
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 5 ms
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:33:49] [INFO ] Input system was already deterministic with 4 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:33:49] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:33:49] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:33:49] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:33:49] [INFO ] Input system was already deterministic with 6 transitions.
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:33:49] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:33:49] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-19 11:33:49] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 8 places, 6 transitions and 18 arcs took 0 ms.
Total runtime 1207 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC10000vD
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679225735653
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
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lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
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lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-12: CTL true CTL model checker
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-11: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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lola: LAUNCH task # 13 (type EXCL) for 12 TwoPhaseLocking-PT-nC10000vD-CTLFireability-06
lola: time limit : 443 sec
lola: memory limit: 32 pages
lola: CANCELED task # 13 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-CTLFireability-06 (memory limit exceeded)
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-12: CTL true CTL model checker
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-11: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 10 (type EXCL) for 9 TwoPhaseLocking-PT-nC10000vD-CTLFireability-05
lola: time limit : 506 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vD-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-11: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/506 28/32 TwoPhaseLocking-PT-nC10000vD-CTLFireability-05 6858162 m, 1371632 m/sec, 6869563 t fired, .
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lola: CANCELED task # 10 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-CTLFireability-05 (memory limit exceeded)
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-12: CTL true CTL model checker
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-11: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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lola: LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC10000vD-CTLFireability-04
lola: time limit : 589 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-CTLFireability-04
lola: result : true
lola: markings : 34998
lola: fired transitions : 35005
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 TwoPhaseLocking-PT-nC10000vD-CTLFireability-11
lola: time limit : 707 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-CTLFireability-11
lola: result : false
lola: markings : 10001
lola: fired transitions : 10000
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC10000vD-CTLFireability-02
lola: time limit : 883 sec
lola: memory limit: 32 pages
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-11: EG false state space / EG
TwoPhaseLocking-PT-nC10000vD-CTLFireability-12: CTL true CTL model checker
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/883 30/32 TwoPhaseLocking-PT-nC10000vD-CTLFireability-02 7157737 m, 1431547 m/sec, 7166472 t fired, .
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lola: CANCELED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-CTLFireability-02 (memory limit exceeded)
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-11: EG false state space / EG
TwoPhaseLocking-PT-nC10000vD-CTLFireability-12: CTL true CTL model checker
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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lola: LAUNCH task # 34 (type EXCL) for 33 TwoPhaseLocking-PT-nC10000vD-CTLFireability-14
lola: time limit : 1175 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-CTLFireability-14
lola: result : true
lola: markings : 19999
lola: fired transitions : 20000
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 TwoPhaseLocking-PT-nC10000vD-CTLFireability-08
lola: time limit : 1762 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-CTLFireability-08
lola: result : false
lola: markings : 19998
lola: fired transitions : 40000
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 TwoPhaseLocking-PT-nC10000vD-CTLFireability-10
lola: time limit : 3525 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-08: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-11: EG false state space / EG
TwoPhaseLocking-PT-nC10000vD-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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22 CTL EXCL 5/3525 8/32 TwoPhaseLocking-PT-nC10000vD-CTLFireability-10 1837234 m, 367446 m/sec, 7187671 t fired, .
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-08: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-11: EG false state space / EG
TwoPhaseLocking-PT-nC10000vD-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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22 CTL EXCL 10/3525 14/32 TwoPhaseLocking-PT-nC10000vD-CTLFireability-10 3335597 m, 299672 m/sec, 13522678 t fired, .
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-08: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-11: EG false state space / EG
TwoPhaseLocking-PT-nC10000vD-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 15/3525 19/32 TwoPhaseLocking-PT-nC10000vD-CTLFireability-10 4708044 m, 274489 m/sec, 19429604 t fired, .
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-08: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-11: EG false state space / EG
TwoPhaseLocking-PT-nC10000vD-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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22 CTL EXCL 20/3525 25/32 TwoPhaseLocking-PT-nC10000vD-CTLFireability-10 6066300 m, 271651 m/sec, 25194467 t fired, .
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-08: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-11: EG false state space / EG
TwoPhaseLocking-PT-nC10000vD-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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22 CTL EXCL 25/3525 30/32 TwoPhaseLocking-PT-nC10000vD-CTLFireability-10 7427545 m, 272249 m/sec, 31006407 t fired, .
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lola: CANCELED task # 22 (type EXCL) for TwoPhaseLocking-PT-nC10000vD-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-08: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-11: EG false state space / EG
TwoPhaseLocking-PT-nC10000vD-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-14: CTL true CTL model checker
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TwoPhaseLocking-PT-nC10000vD-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vD-CTLFireability-02: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vD-CTLFireability-03: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-05: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vD-CTLFireability-06: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vD-CTLFireability-07: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vD-CTLFireability-08: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-10: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vD-CTLFireability-11: EG false state space / EG
TwoPhaseLocking-PT-nC10000vD-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-13: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vD-CTLFireability-14: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vD-CTLFireability-15: CTL unknown AGGR
Time elapsed: 105 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC10000vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is TwoPhaseLocking-PT-nC10000vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703700930"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC10000vD.tgz
mv TwoPhaseLocking-PT-nC10000vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;