About the Execution of LoLa+red for TwoPhaseLocking-PT-nC05000vD
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3384.044 | 93840.00 | 80836.00 | 539.30 | FFFTTF??TFT???F? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703700914.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is TwoPhaseLocking-PT-nC05000vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703700914
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 464K
-rw-r--r-- 1 mcc users 7.0K Feb 25 17:56 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Feb 25 17:56 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Feb 25 17:55 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 25 17:55 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 17:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 17:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 17:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 17:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 17:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 125K Feb 25 17:57 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 17:56 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 88K Feb 25 17:56 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:24 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:24 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679225235042
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC05000vD
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 11:27:16] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 11:27:16] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 11:27:16] [INFO ] Load time of PNML (sax parser for PT used): 17 ms
[2023-03-19 11:27:16] [INFO ] Transformed 8 places.
[2023-03-19 11:27:16] [INFO ] Transformed 6 transitions.
[2023-03-19 11:27:16] [INFO ] Parsed PT model containing 8 places and 6 transitions and 18 arcs in 71 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Support contains 8 out of 8 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 8 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
// Phase 1: matrix 6 rows 8 cols
[2023-03-19 11:27:16] [INFO ] Computed 3 place invariants in 7 ms
[2023-03-19 11:27:16] [INFO ] Implicit Places using invariants in 124 ms returned []
[2023-03-19 11:27:16] [INFO ] Invariant cache hit.
[2023-03-19 11:27:16] [INFO ] Implicit Places using invariants and state equation in 32 ms returned []
Implicit Place search using SMT with State Equation took 179 ms to find 0 implicit places.
[2023-03-19 11:27:16] [INFO ] Invariant cache hit.
[2023-03-19 11:27:16] [INFO ] Dead Transitions using invariants and state equation in 28 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 220 ms. Remains : 8/8 places, 6/6 transitions.
Support contains 8 out of 8 places after structural reductions.
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 13 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 4 ms
[2023-03-19 11:27:17] [INFO ] Input system was already deterministic with 6 transitions.
Incomplete random walk after 10006 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=555 ) properties (out of 27) seen :19
Finished Best-First random walk after 112 steps, including 0 resets, run visited all 8 properties in 3 ms. (steps per millisecond=37 )
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:27:17] [INFO ] Input system was already deterministic with 6 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 2 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Applied a total of 2 rules in 3 ms. Remains 7 /8 variables (removed 1) and now considering 5/6 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 7/8 places, 5/6 transitions.
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:27:17] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:27:17] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Applied a total of 4 rules in 3 ms. Remains 6 /8 variables (removed 2) and now considering 4/6 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 6/8 places, 4/6 transitions.
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:27:17] [INFO ] Input system was already deterministic with 4 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Applied a total of 2 rules in 1 ms. Remains 7 /8 variables (removed 1) and now considering 5/6 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 7/8 places, 5/6 transitions.
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:27:17] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:27:17] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Input system was already deterministic with 6 transitions.
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:17] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-19 11:27:17] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 8 places, 6 transitions and 18 arcs took 1 ms.
Total runtime 964 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC05000vD
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679225328882
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC05000vD-CTLFireability-01
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
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lola: FINISHED task # 4 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-01
lola: result : false
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lola: LAUNCH task # 46 (type EXCL) for 45 TwoPhaseLocking-PT-nC05000vD-CTLFireability-15
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
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46 CTL EXCL 5/240 29/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-15 6782804 m, 1356560 m/sec, 6803337 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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lola: FINISHED task # 43 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-14
lola: result : false
lola: markings : 184899
lola: fired transitions : 467420
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lola: LAUNCH task # 40 (type EXCL) for 39 TwoPhaseLocking-PT-nC05000vD-CTLFireability-13
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker
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TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/276 10/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-13 2250977 m, 450195 m/sec, 6971047 t fired, .
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TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 10/276 17/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-13 4201683 m, 390141 m/sec, 13243793 t fired, .
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TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 15/276 25/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-13 6030516 m, 365766 m/sec, 19162609 t fired, .
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TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 20/276 32/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-13 7814751 m, 356847 m/sec, 24963647 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 5/297 26/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-12 6237589 m, 1247517 m/sec, 6273448 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 28 (type EXCL) for 27 TwoPhaseLocking-PT-nC05000vD-CTLFireability-09
lola: time limit : 323 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-09
lola: result : false
lola: markings : 15000
lola: fired transitions : 15002
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 TwoPhaseLocking-PT-nC05000vD-CTLFireability-08
lola: time limit : 355 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-08
lola: result : true
lola: markings : 24999
lola: fired transitions : 107503
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 TwoPhaseLocking-PT-nC05000vD-CTLFireability-04
lola: time limit : 395 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-04
lola: result : true
lola: markings : 6269997
lola: fired transitions : 6287498
lola: time used : 4.000000
lola: memory pages used : 26
lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC05000vD-CTLFireability-00
lola: time limit : 443 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-00
lola: result : false
lola: markings : 12497
lola: fired transitions : 15001
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 TwoPhaseLocking-PT-nC05000vD-CTLFireability-10
lola: time limit : 507 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-10
lola: result : true
lola: markings : 7501
lola: fired transitions : 7500
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 TwoPhaseLocking-PT-nC05000vD-CTLFireability-03
lola: time limit : 591 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-03
lola: result : true
lola: markings : 7501
lola: fired transitions : 7500
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 TwoPhaseLocking-PT-nC05000vD-CTLFireability-07
lola: time limit : 710 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 AGEF EXCL 1/710 4/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-07 1075333 m, 215066 m/sec, 1608181 t fired, .
Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 22 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 34 (type EXCL) for 33 TwoPhaseLocking-PT-nC05000vD-CTLFireability-11
lola: time limit : 886 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 5/886 22/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-11 5360804 m, 1072160 m/sec, 10765195 t fired, .
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# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 34 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 19 (type EXCL) for 18 TwoPhaseLocking-PT-nC05000vD-CTLFireability-06
lola: time limit : 1178 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/1178 8/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-06 1783498 m, 356699 m/sec, 6145383 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/1178 15/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-06 3528812 m, 349062 m/sec, 12156286 t fired, .
Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/1178 22/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-06 5243759 m, 342989 m/sec, 18062375 t fired, .
Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 20/1178 30/32 TwoPhaseLocking-PT-nC05000vD-CTLFireability-06 7081699 m, 367588 m/sec, 24392229 t fired, .
Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 19 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 16 (type EXCL) for 15 TwoPhaseLocking-PT-nC05000vD-CTLFireability-05
lola: time limit : 1755 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-05
lola: result : false
lola: markings : 15000
lola: fired transitions : 15000
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC05000vD-CTLFireability-02
lola: time limit : 3510 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLFireability-02
lola: result : false
lola: markings : 55044
lola: fired transitions : 150115
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-03: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-06: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vD-CTLFireability-07: AGEF unknown AGGR
TwoPhaseLocking-PT-nC05000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-10: EG true state space / EG
TwoPhaseLocking-PT-nC05000vD-CTLFireability-11: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vD-CTLFireability-12: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vD-CTLFireability-13: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vD-CTLFireability-14: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLFireability-15: CTL unknown AGGR
Time elapsed: 90 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC05000vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is TwoPhaseLocking-PT-nC05000vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703700914"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC05000vD.tgz
mv TwoPhaseLocking-PT-nC05000vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;