About the Execution of LoLa+red for TwoPhaseLocking-PT-nC05000vD
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3623.308 | 117995.00 | 265854.00 | 341.90 | T???FFF?F?TTFTTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703700913.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is TwoPhaseLocking-PT-nC05000vD, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703700913
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 464K
-rw-r--r-- 1 mcc users 7.0K Feb 25 17:56 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Feb 25 17:56 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Feb 25 17:55 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 25 17:55 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 17:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 17:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 17:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 17:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 17:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 125K Feb 25 17:57 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 17:56 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 88K Feb 25 17:56 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:24 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:24 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLCardinality-06
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLCardinality-08
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLCardinality-10
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLCardinality-12
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLCardinality-14
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15
=== Now, execution of the tool begins
BK_START 1679225230894
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC05000vD
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 11:27:12] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLCardinality, -timeout, 360, -rebuildPNML]
[2023-03-19 11:27:12] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 11:27:12] [INFO ] Load time of PNML (sax parser for PT used): 16 ms
[2023-03-19 11:27:12] [INFO ] Transformed 8 places.
[2023-03-19 11:27:12] [INFO ] Transformed 6 transitions.
[2023-03-19 11:27:12] [INFO ] Parsed PT model containing 8 places and 6 transitions and 18 arcs in 67 ms.
Parsed 16 properties from file /home/mcc/execution/CTLCardinality.xml in 11 ms.
Support contains 8 out of 8 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 7 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
// Phase 1: matrix 6 rows 8 cols
[2023-03-19 11:27:12] [INFO ] Computed 3 place invariants in 5 ms
[2023-03-19 11:27:12] [INFO ] Implicit Places using invariants in 139 ms returned []
[2023-03-19 11:27:12] [INFO ] Invariant cache hit.
[2023-03-19 11:27:12] [INFO ] Implicit Places using invariants and state equation in 36 ms returned []
Implicit Place search using SMT with State Equation took 199 ms to find 0 implicit places.
[2023-03-19 11:27:12] [INFO ] Invariant cache hit.
[2023-03-19 11:27:12] [INFO ] Dead Transitions using invariants and state equation in 23 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 231 ms. Remains : 8/8 places, 6/6 transitions.
Support contains 8 out of 8 places after structural reductions.
[2023-03-19 11:27:12] [INFO ] Flatten gal took : 11 ms
[2023-03-19 11:27:12] [INFO ] Flatten gal took : 4 ms
[2023-03-19 11:27:12] [INFO ] Input system was already deterministic with 6 transitions.
Incomplete random walk after 10006 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 78) seen :21
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 49 ms. (steps per millisecond=20 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 57) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 55) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 53) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 53) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 50) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 50) seen :0
Running SMT prover for 50 properties.
[2023-03-19 11:27:13] [INFO ] Invariant cache hit.
[2023-03-19 11:27:13] [INFO ] [Real]Absence check using 3 positive place invariants in 1 ms returned sat
[2023-03-19 11:27:13] [INFO ] After 41ms SMT Verify possible using state equation in real domain returned unsat :22 sat :3 real:25
[2023-03-19 11:27:13] [INFO ] After 47ms SMT Verify possible using trap constraints in real domain returned unsat :22 sat :2 real:26
Attempting to minimize the solution found.
Minimization took 4 ms.
[2023-03-19 11:27:13] [INFO ] After 169ms SMT Verify possible using all constraints in real domain returned unsat :22 sat :2 real:26
[2023-03-19 11:27:13] [INFO ] [Nat]Absence check using 3 positive place invariants in 0 ms returned sat
[2023-03-19 11:27:13] [INFO ] After 27ms SMT Verify possible using state equation in natural domain returned unsat :22 sat :28
[2023-03-19 11:27:13] [INFO ] After 71ms SMT Verify possible using trap constraints in natural domain returned unsat :22 sat :28
Attempting to minimize the solution found.
Minimization took 49 ms.
[2023-03-19 11:27:13] [INFO ] After 182ms SMT Verify possible using all constraints in natural domain returned unsat :22 sat :28
Fused 50 Parikh solutions to 28 different solutions.
Finished Parikh walk after 9790 steps, including 0 resets, run visited all 1 properties in 8 ms. (steps per millisecond=1223 )
Parikh walk visited 28 properties in 2748 ms.
Successfully simplified 22 atomic propositions for a total of 16 simplifications.
Initial state reduction rules removed 1 formulas.
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLCardinality-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 11:27:16] [INFO ] Initial state reduction rules for CTL removed 2 formulas.
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 13 ms
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLCardinality-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLCardinality-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:27:16] [INFO ] Input system was already deterministic with 6 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 4 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:27:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:27:16] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 8 transition count 4
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Applied a total of 4 rules in 1 ms. Remains 6 /8 variables (removed 2) and now considering 4/6 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 6/8 places, 4/6 transitions.
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:16] [INFO ] Input system was already deterministic with 4 transitions.
Incomplete random walk after 10006 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=2501 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=1111 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 4801781 steps, run timeout after 3001 ms. (steps per millisecond=1600 ) properties seen :{}
Probabilistic random walk after 4801781 steps, saw 1887898 distinct states, run finished after 3002 ms. (steps per millisecond=1599 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 4 rows 6 cols
[2023-03-19 11:27:19] [INFO ] Computed 3 place invariants in 1 ms
[2023-03-19 11:27:19] [INFO ] [Real]Absence check using 3 positive place invariants in 0 ms returned sat
[2023-03-19 11:27:19] [INFO ] After 7ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 11:27:19] [INFO ] After 9ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 8 ms.
[2023-03-19 11:27:19] [INFO ] After 49ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :1
Finished Parikh walk after 6514 steps, including 0 resets, run visited all 1 properties in 8 ms. (steps per millisecond=814 )
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLCardinality-10 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 1 properties in 7 ms.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:19] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:27:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:19] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:19] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 8 transition count 4
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Applied a total of 4 rules in 1 ms. Remains 6 /8 variables (removed 2) and now considering 4/6 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 6/8 places, 4/6 transitions.
[2023-03-19 11:27:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:19] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:27:19] [INFO ] Input system was already deterministic with 4 transitions.
Incomplete random walk after 10006 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=2501 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=2500 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 4781830 steps, run timeout after 3001 ms. (steps per millisecond=1593 ) properties seen :{}
Probabilistic random walk after 4781830 steps, saw 1880562 distinct states, run finished after 3001 ms. (steps per millisecond=1593 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-19 11:27:22] [INFO ] Invariant cache hit.
[2023-03-19 11:27:22] [INFO ] [Real]Absence check using 3 positive place invariants in 1 ms returned sat
[2023-03-19 11:27:22] [INFO ] After 3ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 11:27:22] [INFO ] After 6ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 6 ms.
[2023-03-19 11:27:22] [INFO ] After 34ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :1
Finished Parikh walk after 3024 steps, including 0 resets, run visited all 1 properties in 4 ms. (steps per millisecond=756 )
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLCardinality-14 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 1 properties in 4 ms.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:27:22] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:22] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:22] [INFO ] Input system was already deterministic with 6 transitions.
[2023-03-19 11:27:22] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:22] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:27:22] [INFO ] Export to MCC of 11 properties in file /home/mcc/execution/CTLCardinality.sr.xml took 1 ms.
[2023-03-19 11:27:22] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 8 places, 6 transitions and 18 arcs took 1 ms.
Total runtime 10511 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC05000vD
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/367
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679225348889
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/367/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/367/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/367/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: LAUNCH task # 13 (type EXCL) for 6 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 13 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 24 (type EXCL) for 23 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: LAUNCH task # 44 (type FNDP) for 38 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 45 (type FNDP) for 20 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 24 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05
lola: result : false
lola: markings : 10000
lola: fired transitions : 9999
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 35 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13
lola: result : true
lola: markings : 10000
lola: fired transitions : 9999
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 33 (type EXCL) for 32 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11
lola: time limit : 360 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11
lola: result : true
lola: markings : 7034
lola: fired transitions : 26109
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 29 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09
lola: time limit : 400 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 2 0 0 4 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 5/400 9/32 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09 2219136 m, 443827 m/sec, 8028276 t fired, .
44 EF DL FNDP 5/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15 11266734 t fired, 12 attempts, .
45 EF DL FNDP 5/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04 11312561 t fired, 12 attempts, .
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TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 2 0 0 4 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 10/400 18/32 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09 4276966 m, 411566 m/sec, 15486938 t fired, .
44 EF DL FNDP 10/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15 22514147 t fired, 23 attempts, .
45 EF DL FNDP 10/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04 22612501 t fired, 23 attempts, .
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TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 2 0 0 4 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 15/400 26/32 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09 6293538 m, 403314 m/sec, 22796615 t fired, .
44 EF DL FNDP 15/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15 33763407 t fired, 34 attempts, .
45 EF DL FNDP 15/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04 33991679 t fired, 34 attempts, .
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lola: CANCELED task # 30 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 2 0 0 4 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 EF DL FNDP 20/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15 44857820 t fired, 45 attempts, .
45 EF DL FNDP 20/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04 45363506 t fired, 46 attempts, .
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lola: LAUNCH task # 27 (type EXCL) for 26 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07
lola: time limit : 447 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 2 0 0 4 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 5/447 7/32 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07 1566148 m, 313229 m/sec, 7890881 t fired, .
44 EF DL FNDP 25/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15 55939113 t fired, 56 attempts, .
45 EF DL FNDP 25/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04 56697896 t fired, 57 attempts, .
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TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 2 0 0 4 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 10/447 12/32 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07 2950326 m, 276835 m/sec, 15066550 t fired, .
44 EF DL FNDP 30/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15 67279292 t fired, 68 attempts, .
45 EF DL FNDP 30/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04 68178282 t fired, 69 attempts, .
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TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 2 0 0 4 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 15/447 17/32 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07 4215386 m, 253012 m/sec, 21662347 t fired, .
44 EF DL FNDP 35/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15 78465045 t fired, 79 attempts, .
45 EF DL FNDP 35/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04 79595849 t fired, 80 attempts, .
Time elapsed: 35 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 11
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TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 2 0 0 4 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 20/447 23/32 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07 5490860 m, 255094 m/sec, 28331397 t fired, .
44 EF DL FNDP 40/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15 89804386 t fired, 90 attempts, .
45 EF DL FNDP 40/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04 90956579 t fired, 91 attempts, .
Time elapsed: 40 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 11
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TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 2 0 0 4 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 25/447 28/32 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07 6723024 m, 246432 m/sec, 34781863 t fired, .
44 EF DL FNDP 45/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15 101100015 t fired, 102 attempts, .
45 EF DL FNDP 45/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04 102286240 t fired, 103 attempts, .
Time elapsed: 45 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 11
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TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 2 0 0 4 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 30/447 32/32 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07 7935171 m, 242429 m/sec, 41146483 t fired, .
44 EF DL FNDP 50/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15 112456084 t fired, 113 attempts, .
45 EF DL FNDP 50/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04 113615407 t fired, 114 attempts, .
Time elapsed: 50 secs. Pages in use: 32
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lola: CANCELED task # 27 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 2 0 0 4 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 EF DL FNDP 55/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15 123837197 t fired, 124 attempts, .
45 EF DL FNDP 55/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04 125090811 t fired, 126 attempts, .
Time elapsed: 55 secs. Pages in use: 32
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lola: LAUNCH task # 15 (type EXCL) for 6 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02
lola: time limit : 506 sec
lola: memory limit: 32 pages
lola: CANCELED task # 15 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 1 0 0 4 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 EF DL FNDP 60/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15 135217370 t fired, 136 attempts, .
45 EF DL FNDP 60/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04 136498034 t fired, 137 attempts, .
Time elapsed: 60 secs. Pages in use: 32
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lola: LAUNCH task # 9 (type EXCL) for 6 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02
lola: time limit : 590 sec
lola: memory limit: 32 pages
lola: FINISHED task # 9 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01
lola: time limit : 708 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 0 0 0 5 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/708 14/32 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01 3156499 m, 631299 m/sec, 9153855 t fired, .
44 EF DL FNDP 65/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15 146548303 t fired, 147 attempts, .
45 EF DL FNDP 65/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04 147866819 t fired, 148 attempts, .
Time elapsed: 65 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 11
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TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 0 0 0 5 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/708 24/32 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01 5704631 m, 509626 m/sec, 16622448 t fired, .
44 EF DL FNDP 70/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15 157796668 t fired, 158 attempts, .
45 EF DL FNDP 70/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04 159128508 t fired, 160 attempts, .
Time elapsed: 70 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 11
lola: CANCELED task # 4 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 0 0 0 5 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 EF DL FNDP 75/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15 169075919 t fired, 170 attempts, .
45 EF DL FNDP 75/3600 0/5 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04 170432429 t fired, 171 attempts, .
Time elapsed: 75 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 11
lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00
lola: time limit : 881 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00
lola: result : true
lola: markings : 858
lola: fired transitions : 857
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 38 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15
lola: time limit : 1175 sec
lola: memory limit: 32 pages
lola: FINISHED task # 43 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15
lola: result : true
lola: markings : 7501
lola: fired transitions : 7500
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 44 (type FNDP) for TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15 (obsolete)
lola: LAUNCH task # 42 (type EXCL) for 20 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04
lola: time limit : 1762 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type FNDP) for TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15
lola: result : unknown
lola: fired transitions : 169098668
lola: tried executions : 171
lola: time used : 75.000000
lola: memory pages used : 0
lola: FINISHED task # 42 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04
lola: result : true
lola: markings : 7501
lola: fired transitions : 7500
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 45 (type FNDP) for TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04 (obsolete)
lola: LAUNCH task # 18 (type EXCL) for 17 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03
lola: time limit : 3525 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type FNDP) for TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04
lola: result : unknown
lola: fired transitions : 170499923
lola: tried executions : 172
lola: time used : 75.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL false state space
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 0 0 0 5 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 5/3525 8/32 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03 1961955 m, 392391 m/sec, 9162416 t fired, .
Time elapsed: 80 secs. Pages in use: 32
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TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL false state space
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 0 0 0 5 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 10/3525 15/32 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03 3607227 m, 329054 m/sec, 17105377 t fired, .
Time elapsed: 85 secs. Pages in use: 32
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TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL false state space
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 0 0 0 5 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 15/3525 21/32 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03 5107473 m, 300049 m/sec, 24392917 t fired, .
Time elapsed: 90 secs. Pages in use: 32
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL false state space
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 0 0 0 5 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 20/3525 27/32 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03 6547841 m, 288073 m/sec, 31400316 t fired, .
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TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL false state space
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 0 0 0 5 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 25/3525 32/32 TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03 7914506 m, 273333 m/sec, 38084524 t fired, .
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TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL false state space
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ 0 0 0 0 5 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-01: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-02: CONJ unknown CONJ
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-03: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-04: AG NODL false state space
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-07: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-09: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-11: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-13: EXEF true state space /EXEF
TwoPhaseLocking-PT-nC05000vD-CTLCardinality-15: EF DL true state space
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC05000vD"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is TwoPhaseLocking-PT-nC05000vD, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703700913"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC05000vD.tgz
mv TwoPhaseLocking-PT-nC05000vD execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;