Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703700905.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is TwoPhaseLocking-PT-nC02000vN, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703700905
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 460K
-rw-r--r-- 1 mcc users 6.9K Feb 25 17:56 CTLCardinality.txt
-rw-r--r-- 1 mcc users 64K Feb 25 17:56 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K Feb 25 17:55 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K Feb 25 17:55 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 17:23 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:23 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 17:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 17:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 129K Feb 25 17:57 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 17:57 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 88K Feb 25 17:57 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:24 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:24 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLCardinality-10
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15

=== Now, execution of the tool begins

BK_START 1679225048127

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC02000vN
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 11:24:09] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLCardinality, -timeout, 360, -rebuildPNML]
[2023-03-19 11:24:09] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 11:24:09] [INFO ] Load time of PNML (sax parser for PT used): 17 ms
[2023-03-19 11:24:09] [INFO ] Transformed 8 places.
[2023-03-19 11:24:09] [INFO ] Transformed 6 transitions.
[2023-03-19 11:24:09] [INFO ] Parsed PT model containing 8 places and 6 transitions and 18 arcs in 74 ms.
Parsed 16 properties from file /home/mcc/execution/CTLCardinality.xml in 11 ms.
Support contains 8 out of 8 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 8 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
// Phase 1: matrix 6 rows 8 cols
[2023-03-19 11:24:09] [INFO ] Computed 3 place invariants in 6 ms
[2023-03-19 11:24:09] [INFO ] Implicit Places using invariants in 135 ms returned []
[2023-03-19 11:24:09] [INFO ] Invariant cache hit.
[2023-03-19 11:24:09] [INFO ] Implicit Places using invariants and state equation in 34 ms returned []
Implicit Place search using SMT with State Equation took 196 ms to find 0 implicit places.
[2023-03-19 11:24:09] [INFO ] Invariant cache hit.
[2023-03-19 11:24:09] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 231 ms. Remains : 8/8 places, 6/6 transitions.
Support contains 8 out of 8 places after structural reductions.
[2023-03-19 11:24:10] [INFO ] Flatten gal took : 11 ms
[2023-03-19 11:24:10] [INFO ] Flatten gal took : 3 ms
[2023-03-19 11:24:10] [INFO ] Input system was already deterministic with 6 transitions.
Incomplete random walk after 10012 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=385 ) properties (out of 66) seen :38
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=21 ) properties (out of 28) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 28) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 28) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 28) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 28) seen :2
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 26) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 25) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 25) seen :0
Running SMT prover for 25 properties.
[2023-03-19 11:24:10] [INFO ] Invariant cache hit.
[2023-03-19 11:24:10] [INFO ] [Real]Absence check using 3 positive place invariants in 1 ms returned sat
[2023-03-19 11:24:10] [INFO ] After 12ms SMT Verify possible using state equation in real domain returned unsat :11 sat :2 real:12
[2023-03-19 11:24:10] [INFO ] After 16ms SMT Verify possible using trap constraints in real domain returned unsat :11 sat :2 real:12
Attempting to minimize the solution found.
Minimization took 5 ms.
[2023-03-19 11:24:10] [INFO ] After 102ms SMT Verify possible using all constraints in real domain returned unsat :11 sat :2 real:12
[2023-03-19 11:24:10] [INFO ] [Nat]Absence check using 3 positive place invariants in 3 ms returned sat
[2023-03-19 11:24:10] [INFO ] After 31ms SMT Verify possible using state equation in natural domain returned unsat :12 sat :13
[2023-03-19 11:24:10] [INFO ] After 50ms SMT Verify possible using trap constraints in natural domain returned unsat :12 sat :13
Attempting to minimize the solution found.
Minimization took 20 ms.
[2023-03-19 11:24:10] [INFO ] After 134ms SMT Verify possible using all constraints in natural domain returned unsat :12 sat :13
Fused 25 Parikh solutions to 12 different solutions.
Finished Parikh walk after 3528 steps, including 0 resets, run visited all 1 properties in 4 ms. (steps per millisecond=882 )
Parikh walk visited 13 properties in 823 ms.
Successfully simplified 12 atomic propositions for a total of 16 simplifications.
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:24:11] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA TwoPhaseLocking-PT-nC02000vN-CTLCardinality-10 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 11:24:11] [INFO ] Input system was already deterministic with 6 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 2 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 17 ms
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:24:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 2 place count 7 transition count 4
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Applied a total of 4 rules in 5 ms. Remains 6 /8 variables (removed 2) and now considering 4/6 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 6/8 places, 4/6 transitions.
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:24:11] [INFO ] Input system was already deterministic with 4 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:24:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:24:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 5
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 5
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 6 transition count 4
Applied a total of 4 rules in 2 ms. Remains 6 /8 variables (removed 2) and now considering 4/6 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 6/8 places, 4/6 transitions.
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 0 ms
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Input system was already deterministic with 4 transitions.
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Flatten gal took : 1 ms
[2023-03-19 11:24:11] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLCardinality.sr.xml took 2 ms.
[2023-03-19 11:24:11] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 8 places, 6 transitions and 18 arcs took 1 ms.
Total runtime 2389 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC02000vN
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679225188026

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 10 (type EXCL) for 9 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 58 (type FNDP) for 42 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 10 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03
lola: result : false
lola: markings : 1833350
lola: fired transitions : 2004964
lola: time used : 2.000000
lola: memory pages used : 8
lola: LAUNCH task # 52 (type EXCL) for 51 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14
lola: time limit : 211 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ 0 4 0 0 4 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 3/211 5/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14 1190422 m, 238084 m/sec, 6582839 t fired, .
58 EF DL FNDP 5/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 56344874 t fired, 57 attempts, .

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ 0 4 0 0 4 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 8/211 11/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14 2563111 m, 274537 m/sec, 14428133 t fired, .
58 EF DL FNDP 10/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 113801298 t fired, 114 attempts, .

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ 0 4 0 0 4 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 13/211 16/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14 3898145 m, 267006 m/sec, 22107502 t fired, .
58 EF DL FNDP 15/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 171112582 t fired, 172 attempts, .

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ 0 4 0 0 4 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 18/211 21/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14 5197484 m, 259867 m/sec, 29621235 t fired, .
58 EF DL FNDP 20/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 229142933 t fired, 230 attempts, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ 0 4 0 0 4 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 23/211 27/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14 6494917 m, 259486 m/sec, 37143874 t fired, .
58 EF DL FNDP 25/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 286510597 t fired, 287 attempts, .

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ 0 4 0 0 4 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 28/211 32/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14 7766689 m, 254354 m/sec, 44560568 t fired, .
58 EF DL FNDP 30/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 343874672 t fired, 344 attempts, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ 0 4 0 0 4 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EF DL FNDP 35/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 403510342 t fired, 404 attempts, .

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lola: LAUNCH task # 49 (type EXCL) for 48 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13
lola: time limit : 222 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13
lola: result : true
lola: markings : 4005
lola: fired transitions : 12014
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 24 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08
lola: time limit : 237 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08
lola: result : true
lola: markings : 790692
lola: fired transitions : 1480018
lola: time used : 1.000000
lola: memory pages used : 4
lola: LAUNCH task # 22 (type EXCL) for 21 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07
lola: time limit : 324 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 4/324 14/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07 3295752 m, 659150 m/sec, 7150047 t fired, .
58 EF DL FNDP 40/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 463880875 t fired, 464 attempts, .

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 9/324 21/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07 4964726 m, 333794 m/sec, 15296354 t fired, .
58 EF DL FNDP 45/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 521017685 t fired, 522 attempts, .

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 14/324 27/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07 6453533 m, 297761 m/sec, 23277213 t fired, .
58 EF DL FNDP 50/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 578361363 t fired, 579 attempts, .

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EF DL FNDP 55/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 635770566 t fired, 636 attempts, .

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lola: LAUNCH task # 19 (type EXCL) for 18 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06
lola: time limit : 354 sec
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lola: FINISHED task # 19 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06
lola: result : true
lola: markings : 4003
lola: fired transitions : 4730
lola: time used : 0.000000
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lola: LAUNCH task # 16 (type EXCL) for 15 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05
lola: time limit : 393 sec
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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/393 17/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05 3903263 m, 780652 m/sec, 7577894 t fired, .
58 EF DL FNDP 60/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 693200869 t fired, 694 attempts, .

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/393 29/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05 6792947 m, 577936 m/sec, 13297563 t fired, .
58 EF DL FNDP 65/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 750629132 t fired, 751 attempts, .

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EF DL FNDP 70/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 808054316 t fired, 809 attempts, .

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lola: LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02
lola: time limit : 441 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02
lola: result : true
lola: markings : 370150
lola: fired transitions : 391544
lola: time used : 1.000000
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lola: LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01
lola: time limit : 504 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01
lola: result : false
lola: markings : 968345
lola: fired transitions : 969570
lola: time used : 0.000000
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lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 4/588 8/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00 1843451 m, 368690 m/sec, 7509455 t fired, .
58 EF DL FNDP 75/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 865518537 t fired, 866 attempts, .

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 9/588 15/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00 3573545 m, 346018 m/sec, 14764756 t fired, .
58 EF DL FNDP 80/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 922970124 t fired, 923 attempts, .

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 14/588 21/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00 5178921 m, 321075 m/sec, 21541897 t fired, .
58 EF DL FNDP 85/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 980399961 t fired, 981 attempts, .

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 19/588 27/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00 6714132 m, 307042 m/sec, 28046400 t fired, .
58 EF DL FNDP 90/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 1037848488 t fired, 1038 attempts, .

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL 0 1 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 EF DL FNDP 95/3600 0/5 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11 1096218901 t fired, 1097 attempts, .

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lola: FINISHED task # 57 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11
lola: result : false
lola: markings : 4000
lola: fired transitions : 5999
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lola: time limit : 876 sec
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lola: FINISHED task # 58 (type FNDP) for TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11
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lola: tried executions : 1098
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lola: FINISHED task # 55 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15
lola: result : true
lola: markings : 3005
lola: fired transitions : 3005
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lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F false state space / EG
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL false state space
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG true state space /EFEG

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 5/1752 8/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12 1885428 m, 377085 m/sec, 10256489 t fired, .

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F false state space / EG
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL false state space
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG true state space /EFEG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 10/1752 14/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12 3469026 m, 316719 m/sec, 19068829 t fired, .

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F false state space / EG
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL false state space
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG true state space /EFEG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 15/1752 20/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12 4919638 m, 290122 m/sec, 27180353 t fired, .

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F false state space / EG
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL false state space
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG true state space /EFEG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 20/1752 26/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12 6313770 m, 278826 m/sec, 34997306 t fired, .

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TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F false state space / EG
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL false state space
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG true state space /EFEG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 25/1752 31/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12 7622765 m, 261799 m/sec, 42347718 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F false state space / EG
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL false state space
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG true state space /EFEG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F false state space / EG
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL false state space
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG true state space /EFEG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/3475 18/32 TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09 4191821 m, 838364 m/sec, 12517325 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F false state space / EG
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL false state space
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG true state space /EFEG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-00: CTL unknown AGGR
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-02: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-04: F false state space / EG
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-05: CTL unknown AGGR
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-07: CTL unknown AGGR
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-08: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-09: CTL unknown AGGR
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-11: EF DL false state space
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-12: CTL unknown AGGR
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-14: CTL unknown AGGR
TwoPhaseLocking-PT-nC02000vN-CTLCardinality-15: EFEG true state space /EFEG


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC02000vN"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is TwoPhaseLocking-PT-nC02000vN, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703700905"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC02000vN.tgz
mv TwoPhaseLocking-PT-nC02000vN execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;