fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r487-tall-167912703500770
Last Updated
May 14, 2023

About the Execution of LoLa+red for TwoPhaseLocking-PT-nC00004vD

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
206.264 3580.00 5046.00 223.80 TTTFFTFFTTFFFTFT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703500770.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is TwoPhaseLocking-PT-nC00004vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703500770
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 404K
-rw-r--r-- 1 mcc users 8.5K Feb 25 17:52 CTLCardinality.txt
-rw-r--r-- 1 mcc users 91K Feb 25 17:52 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.6K Feb 25 17:52 CTLFireability.txt
-rw-r--r-- 1 mcc users 36K Feb 25 17:52 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:22 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 17:22 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 17:22 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:22 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 17:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 123K Feb 25 17:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Feb 25 17:52 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 32K Feb 25 17:52 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:22 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:22 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC00004vD-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC00004vD-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC00004vD-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC00004vD-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC00004vD-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC00004vD-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC00004vD-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC00004vD-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC00004vD-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC00004vD-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC00004vD-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC00004vD-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC00004vD-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC00004vD-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC00004vD-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC00004vD-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679223534954

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC00004vD
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 10:58:56] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 10:58:56] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 10:58:56] [INFO ] Load time of PNML (sax parser for PT used): 17 ms
[2023-03-19 10:58:56] [INFO ] Transformed 8 places.
[2023-03-19 10:58:56] [INFO ] Transformed 6 transitions.
[2023-03-19 10:58:56] [INFO ] Parsed PT model containing 8 places and 6 transitions and 18 arcs in 77 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Initial state reduction rules removed 4 formulas.
FORMULA TwoPhaseLocking-PT-nC00004vD-CTLFireability-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA TwoPhaseLocking-PT-nC00004vD-CTLFireability-02 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA TwoPhaseLocking-PT-nC00004vD-CTLFireability-03 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA TwoPhaseLocking-PT-nC00004vD-CTLFireability-08 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA TwoPhaseLocking-PT-nC00004vD-CTLFireability-15 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 8 out of 8 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 9 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
// Phase 1: matrix 6 rows 8 cols
[2023-03-19 10:58:56] [INFO ] Computed 3 place invariants in 5 ms
[2023-03-19 10:58:56] [INFO ] Implicit Places using invariants in 122 ms returned []
[2023-03-19 10:58:56] [INFO ] Invariant cache hit.
[2023-03-19 10:58:56] [INFO ] Implicit Places using invariants and state equation in 33 ms returned []
Implicit Place search using SMT with State Equation took 178 ms to find 0 implicit places.
[2023-03-19 10:58:56] [INFO ] Invariant cache hit.
[2023-03-19 10:58:56] [INFO ] Dead Transitions using invariants and state equation in 39 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 229 ms. Remains : 8/8 places, 6/6 transitions.
Support contains 8 out of 8 places after structural reductions.
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 12 ms
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 4 ms
[2023-03-19 10:58:57] [INFO ] Input system was already deterministic with 6 transitions.
Finished random walk after 13 steps, including 0 resets, run visited all 13 properties in 11 ms. (steps per millisecond=1 )
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 2 ms
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 2 ms
[2023-03-19 10:58:57] [INFO ] Input system was already deterministic with 6 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 1 ms
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 0 ms
[2023-03-19 10:58:57] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 1 ms
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 0 ms
[2023-03-19 10:58:57] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 1 ms
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 1 ms
[2023-03-19 10:58:57] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 1 ms
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 1 ms
[2023-03-19 10:58:57] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 1 ms
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 1 ms
[2023-03-19 10:58:57] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 1 ms
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 1 ms
[2023-03-19 10:58:57] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 1 ms
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 1 ms
[2023-03-19 10:58:57] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 1 ms
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 1 ms
[2023-03-19 10:58:57] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 0 ms
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 0 ms
[2023-03-19 10:58:57] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 1 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 1 ms
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 1 ms
[2023-03-19 10:58:57] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 8/8 places, 6/6 transitions.
Applied a total of 0 rules in 0 ms. Remains 8 /8 variables (removed 0) and now considering 6/6 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/8 places, 6/6 transitions.
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 6 ms
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 0 ms
[2023-03-19 10:58:57] [INFO ] Input system was already deterministic with 6 transitions.
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 1 ms
[2023-03-19 10:58:57] [INFO ] Flatten gal took : 2 ms
[2023-03-19 10:58:57] [INFO ] Export to MCC of 11 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-19 10:58:57] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 8 places, 6 transitions and 18 arcs took 1 ms.
Total runtime 940 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC00004vD
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA TwoPhaseLocking-PT-nC00004vD-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00004vD-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00004vD-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00004vD-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00004vD-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00004vD-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00004vD-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00004vD-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00004vD-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00004vD-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC00004vD-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679223538534

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC00004vD-CTLFireability-05
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 7 (type EXCL) for TwoPhaseLocking-PT-nC00004vD-CTLFireability-05
lola: result : true
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 22 (type EXCL) for 21 TwoPhaseLocking-PT-nC00004vD-CTLFireability-11
lola: time limit : 300 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 22 (type EXCL) for TwoPhaseLocking-PT-nC00004vD-CTLFireability-11
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 28 (type EXCL) for 27 TwoPhaseLocking-PT-nC00004vD-CTLFireability-13
lola: time limit : 400 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 28 (type EXCL) for TwoPhaseLocking-PT-nC00004vD-CTLFireability-13
lola: result : true
lola: markings : 11
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 31 (type EXCL) for 30 TwoPhaseLocking-PT-nC00004vD-CTLFireability-14
lola: time limit : 450 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for TwoPhaseLocking-PT-nC00004vD-CTLFireability-14
lola: result : false
lola: markings : 27
lola: fired transitions : 81
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 TwoPhaseLocking-PT-nC00004vD-CTLFireability-12
lola: time limit : 514 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for TwoPhaseLocking-PT-nC00004vD-CTLFireability-12
lola: result : false
lola: markings : 5
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 TwoPhaseLocking-PT-nC00004vD-CTLFireability-09
lola: time limit : 600 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 16 (type EXCL) for TwoPhaseLocking-PT-nC00004vD-CTLFireability-09
lola: result : true
lola: markings : 32
lola: fired transitions : 198
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 TwoPhaseLocking-PT-nC00004vD-CTLFireability-10
lola: time limit : 720 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for TwoPhaseLocking-PT-nC00004vD-CTLFireability-10
lola: result : false
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 TwoPhaseLocking-PT-nC00004vD-CTLFireability-07
lola: time limit : 900 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for TwoPhaseLocking-PT-nC00004vD-CTLFireability-07
lola: result : false
lola: markings : 23
lola: fired transitions : 64
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 TwoPhaseLocking-PT-nC00004vD-CTLFireability-06
lola: time limit : 1200 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for TwoPhaseLocking-PT-nC00004vD-CTLFireability-06
lola: result : false
lola: markings : 21
lola: fired transitions : 60
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC00004vD-CTLFireability-04
lola: time limit : 1800 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for TwoPhaseLocking-PT-nC00004vD-CTLFireability-04
lola: result : false
lola: markings : 12
lola: fired transitions : 24
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC00004vD-CTLFireability-00
lola: time limit : 3600 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC00004vD-CTLFireability-00
lola: result : true
lola: markings : 27
lola: fired transitions : 78
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC00004vD-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC00004vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC00004vD-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC00004vD-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC00004vD-CTLFireability-07: CTL false CTL model checker
TwoPhaseLocking-PT-nC00004vD-CTLFireability-09: CTL true CTL model checker
TwoPhaseLocking-PT-nC00004vD-CTLFireability-10: CTL false CTL model checker
TwoPhaseLocking-PT-nC00004vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC00004vD-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC00004vD-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC00004vD-CTLFireability-14: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC00004vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is TwoPhaseLocking-PT-nC00004vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703500770"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC00004vD.tgz
mv TwoPhaseLocking-PT-nC00004vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;