Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703200514.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is TCPcondis-PT-15, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703200514
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 492K
-rw-r--r-- 1 mcc users 7.9K Feb 26 16:09 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K Feb 26 16:09 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K Feb 26 16:08 CTLFireability.txt
-rw-r--r-- 1 mcc users 43K Feb 26 16:08 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 17:19 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 25 17:19 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 17:20 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:20 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 16:10 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 131K Feb 26 16:10 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.8K Feb 26 16:10 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 76K Feb 26 16:10 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 17:20 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 17:20 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rwxr-xr-x 1 mcc users 24K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TCPcondis-PT-15-CTLFireability-00
FORMULA_NAME TCPcondis-PT-15-CTLFireability-01
FORMULA_NAME TCPcondis-PT-15-CTLFireability-02
FORMULA_NAME TCPcondis-PT-15-CTLFireability-03
FORMULA_NAME TCPcondis-PT-15-CTLFireability-04
FORMULA_NAME TCPcondis-PT-15-CTLFireability-05
FORMULA_NAME TCPcondis-PT-15-CTLFireability-06
FORMULA_NAME TCPcondis-PT-15-CTLFireability-07
FORMULA_NAME TCPcondis-PT-15-CTLFireability-08
FORMULA_NAME TCPcondis-PT-15-CTLFireability-09
FORMULA_NAME TCPcondis-PT-15-CTLFireability-10
FORMULA_NAME TCPcondis-PT-15-CTLFireability-11
FORMULA_NAME TCPcondis-PT-15-CTLFireability-12
FORMULA_NAME TCPcondis-PT-15-CTLFireability-13
FORMULA_NAME TCPcondis-PT-15-CTLFireability-14
FORMULA_NAME TCPcondis-PT-15-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679201937559

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TCPcondis-PT-15
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 04:58:59] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 04:58:59] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 04:58:59] [WARNING] Skipping unknown tool specific annotation : Tina
[2023-03-19 04:58:59] [WARNING] Unknown XML tag in source file: size
[2023-03-19 04:58:59] [WARNING] Unknown XML tag in source file: color
[2023-03-19 04:58:59] [INFO ] Load time of PNML (sax parser for PT used): 29 ms
[2023-03-19 04:58:59] [INFO ] Transformed 30 places.
[2023-03-19 04:58:59] [INFO ] Transformed 32 transitions.
[2023-03-19 04:58:59] [INFO ] Parsed PT model containing 30 places and 32 transitions and 108 arcs in 117 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Support contains 29 out of 30 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 30/30 places, 32/32 transitions.
Applied a total of 0 rules in 8 ms. Remains 30 /30 variables (removed 0) and now considering 32/32 (removed 0) transitions.
// Phase 1: matrix 32 rows 30 cols
[2023-03-19 04:58:59] [INFO ] Computed 9 place invariants in 9 ms
[2023-03-19 04:58:59] [INFO ] Implicit Places using invariants in 150 ms returned []
[2023-03-19 04:58:59] [INFO ] Invariant cache hit.
[2023-03-19 04:58:59] [INFO ] Implicit Places using invariants and state equation in 56 ms returned []
Implicit Place search using SMT with State Equation took 231 ms to find 0 implicit places.
[2023-03-19 04:58:59] [INFO ] Invariant cache hit.
[2023-03-19 04:58:59] [INFO ] Dead Transitions using invariants and state equation in 49 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 290 ms. Remains : 30/30 places, 32/32 transitions.
Support contains 29 out of 30 places after structural reductions.
[2023-03-19 04:58:59] [INFO ] Flatten gal took : 19 ms
[2023-03-19 04:58:59] [INFO ] Flatten gal took : 6 ms
[2023-03-19 04:58:59] [INFO ] Input system was already deterministic with 32 transitions.
Incomplete random walk after 10001 steps, including 2 resets, run finished after 111 ms. (steps per millisecond=90 ) properties (out of 46) seen :45
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-19 04:59:00] [INFO ] Invariant cache hit.
[2023-03-19 04:59:00] [INFO ] After 29ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 4 ms
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 4 ms
[2023-03-19 04:59:00] [INFO ] Input system was already deterministic with 32 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 30/30 places, 32/32 transitions.
Applied a total of 0 rules in 1 ms. Remains 30 /30 variables (removed 0) and now considering 32/32 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 30/30 places, 32/32 transitions.
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Input system was already deterministic with 32 transitions.
Starting structural reductions in LTL mode, iteration 0 : 30/30 places, 32/32 transitions.
Applied a total of 0 rules in 1 ms. Remains 30 /30 variables (removed 0) and now considering 32/32 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 30/30 places, 32/32 transitions.
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Input system was already deterministic with 32 transitions.
Starting structural reductions in LTL mode, iteration 0 : 30/30 places, 32/32 transitions.
Applied a total of 0 rules in 1 ms. Remains 30 /30 variables (removed 0) and now considering 32/32 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 30/30 places, 32/32 transitions.
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Input system was already deterministic with 32 transitions.
Starting structural reductions in LTL mode, iteration 0 : 30/30 places, 32/32 transitions.
Applied a total of 0 rules in 0 ms. Remains 30 /30 variables (removed 0) and now considering 32/32 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 30/30 places, 32/32 transitions.
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Input system was already deterministic with 32 transitions.
Starting structural reductions in LTL mode, iteration 0 : 30/30 places, 32/32 transitions.
Applied a total of 0 rules in 1 ms. Remains 30 /30 variables (removed 0) and now considering 32/32 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 30/30 places, 32/32 transitions.
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Input system was already deterministic with 32 transitions.
Starting structural reductions in LTL mode, iteration 0 : 30/30 places, 32/32 transitions.
Applied a total of 0 rules in 1 ms. Remains 30 /30 variables (removed 0) and now considering 32/32 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 30/30 places, 32/32 transitions.
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Input system was already deterministic with 32 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 30/30 places, 32/32 transitions.
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 0 with 6 rules applied. Total rules applied 6 place count 27 transition count 29
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 7 place count 26 transition count 28
Iterating global reduction 0 with 1 rules applied. Total rules applied 8 place count 26 transition count 28
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 0 with 2 rules applied. Total rules applied 10 place count 26 transition count 26
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 2 Pre rules applied. Total rules applied 10 place count 26 transition count 24
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 4 rules applied. Total rules applied 14 place count 24 transition count 24
Applied a total of 14 rules in 13 ms. Remains 24 /30 variables (removed 6) and now considering 24/32 (removed 8) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 24/30 places, 24/32 transitions.
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Input system was already deterministic with 24 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 30/30 places, 32/32 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 8 place count 26 transition count 28
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 10 place count 24 transition count 26
Iterating global reduction 0 with 2 rules applied. Total rules applied 12 place count 24 transition count 26
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 13 place count 24 transition count 25
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 13 place count 24 transition count 24
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 15 place count 23 transition count 24
Applied a total of 15 rules in 6 ms. Remains 23 /30 variables (removed 7) and now considering 24/32 (removed 8) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 23/30 places, 24/32 transitions.
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:59:00] [INFO ] Input system was already deterministic with 24 transitions.
Starting structural reductions in LTL mode, iteration 0 : 30/30 places, 32/32 transitions.
Applied a total of 0 rules in 0 ms. Remains 30 /30 variables (removed 0) and now considering 32/32 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 30/30 places, 32/32 transitions.
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Input system was already deterministic with 32 transitions.
Starting structural reductions in LTL mode, iteration 0 : 30/30 places, 32/32 transitions.
Applied a total of 0 rules in 0 ms. Remains 30 /30 variables (removed 0) and now considering 32/32 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 30/30 places, 32/32 transitions.
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Input system was already deterministic with 32 transitions.
Starting structural reductions in LTL mode, iteration 0 : 30/30 places, 32/32 transitions.
Applied a total of 0 rules in 0 ms. Remains 30 /30 variables (removed 0) and now considering 32/32 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 30/30 places, 32/32 transitions.
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Input system was already deterministic with 32 transitions.
Starting structural reductions in LTL mode, iteration 0 : 30/30 places, 32/32 transitions.
Applied a total of 0 rules in 0 ms. Remains 30 /30 variables (removed 0) and now considering 32/32 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 30/30 places, 32/32 transitions.
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Input system was already deterministic with 32 transitions.
Starting structural reductions in LTL mode, iteration 0 : 30/30 places, 32/32 transitions.
Applied a total of 0 rules in 0 ms. Remains 30 /30 variables (removed 0) and now considering 32/32 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 30/30 places, 32/32 transitions.
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:59:00] [INFO ] Input system was already deterministic with 32 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 30/30 places, 32/32 transitions.
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 0 with 6 rules applied. Total rules applied 6 place count 27 transition count 29
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 7 place count 26 transition count 28
Iterating global reduction 0 with 1 rules applied. Total rules applied 8 place count 26 transition count 28
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 0 with 2 rules applied. Total rules applied 10 place count 26 transition count 26
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 10 place count 26 transition count 25
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 12 place count 25 transition count 25
Applied a total of 12 rules in 6 ms. Remains 25 /30 variables (removed 5) and now considering 25/32 (removed 7) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 25/30 places, 25/32 transitions.
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Input system was already deterministic with 25 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 30/30 places, 32/32 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 4 rules applied. Total rules applied 4 place count 28 transition count 30
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 6 place count 26 transition count 28
Iterating global reduction 0 with 2 rules applied. Total rules applied 8 place count 26 transition count 28
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 9 place count 26 transition count 27
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 9 place count 26 transition count 26
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 11 place count 25 transition count 26
Applied a total of 11 rules in 5 ms. Remains 25 /30 variables (removed 5) and now considering 26/32 (removed 6) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 25/30 places, 26/32 transitions.
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Input system was already deterministic with 26 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 30/30 places, 32/32 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 8 place count 26 transition count 28
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 10 place count 24 transition count 26
Iterating global reduction 0 with 2 rules applied. Total rules applied 12 place count 24 transition count 26
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 0 with 2 rules applied. Total rules applied 14 place count 24 transition count 24
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 2 Pre rules applied. Total rules applied 14 place count 24 transition count 22
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 4 rules applied. Total rules applied 18 place count 22 transition count 22
Applied a total of 18 rules in 5 ms. Remains 22 /30 variables (removed 8) and now considering 22/32 (removed 10) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 22/30 places, 22/32 transitions.
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Input system was already deterministic with 22 transitions.
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:59:00] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-19 04:59:00] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 30 places, 32 transitions and 108 arcs took 1 ms.
Total runtime 1279 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT TCPcondis-PT-15
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA TCPcondis-PT-15-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TCPcondis-PT-15-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TCPcondis-PT-15-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TCPcondis-PT-15-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TCPcondis-PT-15-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TCPcondis-PT-15-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TCPcondis-PT-15-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TCPcondis-PT-15-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TCPcondis-PT-15-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TCPcondis-PT-15-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TCPcondis-PT-15-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TCPcondis-PT-15-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679202056677

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 20 (type EXCL) for TCPcondis-PT-15-CTLFireability-03
lola: result : true
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 37 (type EXCL) for 36 TCPcondis-PT-15-CTLFireability-08
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lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:736
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: Created skeleton in 0.000000 secs.
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lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 5/211 10/32 TCPcondis-PT-15-CTLFireability-08 2346988 m, 469397 m/sec, 8069086 t fired, .

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37 CTL EXCL 10/211 19/32 TCPcondis-PT-15-CTLFireability-08 4382128 m, 407028 m/sec, 15575948 t fired, .

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37 CTL EXCL 15/211 27/32 TCPcondis-PT-15-CTLFireability-08 6380986 m, 399771 m/sec, 22933201 t fired, .

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43 CTL EXCL 5/255 9/32 TCPcondis-PT-15-CTLFireability-10 2111735 m, 422347 m/sec, 4408649 t fired, .

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43 CTL EXCL 10/255 18/32 TCPcondis-PT-15-CTLFireability-10 4090284 m, 395709 m/sec, 8689158 t fired, .

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43 CTL EXCL 15/255 26/32 TCPcondis-PT-15-CTLFireability-10 6021112 m, 386165 m/sec, 12863785 t fired, .

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28 CTL EXCL 5/296 5/32 TCPcondis-PT-15-CTLFireability-05 1040859 m, 208171 m/sec, 6124794 t fired, .

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28 CTL EXCL 10/296 8/32 TCPcondis-PT-15-CTLFireability-05 1895103 m, 170848 m/sec, 11500658 t fired, .

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28 CTL EXCL 15/296 12/32 TCPcondis-PT-15-CTLFireability-05 2687965 m, 158572 m/sec, 16597951 t fired, .

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28 CTL EXCL 20/296 15/32 TCPcondis-PT-15-CTLFireability-05 3440255 m, 150458 m/sec, 21515289 t fired, .

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28 CTL EXCL 25/296 18/32 TCPcondis-PT-15-CTLFireability-05 4184155 m, 148780 m/sec, 26418729 t fired, .

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28 CTL EXCL 30/296 21/32 TCPcondis-PT-15-CTLFireability-05 4895702 m, 142309 m/sec, 31156445 t fired, .

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28 CTL EXCL 35/296 24/32 TCPcondis-PT-15-CTLFireability-05 5591010 m, 139061 m/sec, 35813070 t fired, .

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28 CTL EXCL 40/296 27/32 TCPcondis-PT-15-CTLFireability-05 6271372 m, 136072 m/sec, 40400623 t fired, .

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28 CTL EXCL 45/296 30/32 TCPcondis-PT-15-CTLFireability-05 6943374 m, 134400 m/sec, 44948687 t fired, .

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28 CTL EXCL 50/296 32/32 TCPcondis-PT-15-CTLFireability-05 7605667 m, 132458 m/sec, 49464224 t fired, .

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1 CTL EXCL 10/500 18/32 TCPcondis-PT-15-CTLFireability-00 4152483 m, 388112 m/sec, 14065880 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TCPcondis-PT-15-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TCPcondis-PT-15-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TCPcondis-PT-15-CTLFireability-06: EGEF 0 1 0 0 1 0 0 0
TCPcondis-PT-15-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TCPcondis-PT-15-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TCPcondis-PT-15-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TCPcondis-PT-15-CTLFireability-13: F 0 1 0 0 1 0 0 0
TCPcondis-PT-15-CTLFireability-14: DISJ 0 2 0 0 2 0 0 0
TCPcondis-PT-15-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 64 (type EXCL) for 51 TCPcondis-PT-15-CTLFireability-13
lola: time limit : 580 sec
lola: memory limit: 32 pages
lola: FINISHED task # 64 (type EXCL) for TCPcondis-PT-15-CTLFireability-13
lola: result : true
lola: markings : 72
lola: fired transitions : 72
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 TCPcondis-PT-15-CTLFireability-06
lola: time limit : 697 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for TCPcondis-PT-15-CTLFireability-06
lola: result : true
lola: markings : 156
lola: fired transitions : 465
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 62 (type EXCL) for 61 TCPcondis-PT-15-CTLFireability-15
lola: time limit : 871 sec
lola: memory limit: 32 pages
lola: FINISHED task # 62 (type EXCL) for TCPcondis-PT-15-CTLFireability-15
lola: result : false
lola: markings : 141
lola: fired transitions : 282
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 57 (type EXCL) for 54 TCPcondis-PT-15-CTLFireability-14
lola: time limit : 1161 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EXCL) for TCPcondis-PT-15-CTLFireability-14
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 TCPcondis-PT-15-CTLFireability-07
lola: time limit : 1742 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for TCPcondis-PT-15-CTLFireability-07
lola: result : false
lola: markings : 141
lola: fired transitions : 142
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 59 (type EXCL) for 54 TCPcondis-PT-15-CTLFireability-14
lola: time limit : 3485 sec
lola: memory limit: 32 pages
lola: FINISHED task # 59 (type EXCL) for TCPcondis-PT-15-CTLFireability-14
lola: result : true
lola: markings : 147
lola: fired transitions : 432
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TCPcondis-PT-15-CTLFireability-00: CTL unknown AGGR
TCPcondis-PT-15-CTLFireability-01: CTL true CTL model checker
TCPcondis-PT-15-CTLFireability-02: CTL true CTL model checker
TCPcondis-PT-15-CTLFireability-03: CONJ true CONJ
TCPcondis-PT-15-CTLFireability-04: CTL true CTL model checker
TCPcondis-PT-15-CTLFireability-05: CTL unknown AGGR
TCPcondis-PT-15-CTLFireability-06: EGEF true CTL model checker
TCPcondis-PT-15-CTLFireability-07: CTL false CTL model checker
TCPcondis-PT-15-CTLFireability-08: CTL unknown AGGR
TCPcondis-PT-15-CTLFireability-09: CTL false CTL model checker
TCPcondis-PT-15-CTLFireability-10: CTL unknown AGGR
TCPcondis-PT-15-CTLFireability-11: CTL false CTL model checker
TCPcondis-PT-15-CTLFireability-12: CTL true CTL model checker
TCPcondis-PT-15-CTLFireability-13: F false state space / EG
TCPcondis-PT-15-CTLFireability-14: DISJ true CTL model checker
TCPcondis-PT-15-CTLFireability-15: AFAG false CTL model checker


Time elapsed: 115 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TCPcondis-PT-15"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is TCPcondis-PT-15, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703200514"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TCPcondis-PT-15.tgz
mv TCPcondis-PT-15 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;