fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r487-tall-167912703000410
Last Updated
May 14, 2023

About the Execution of LoLa+red for Szymanski-PT-a04

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
5101.584 181796.00 181057.00 737.80 T?TT?TT?TT?F?FTF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r487-tall-167912703000410.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Szymanski-PT-a04, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r487-tall-167912703000410
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 488K
-rw-r--r-- 1 mcc users 6.4K Feb 26 16:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 69K Feb 26 16:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Feb 26 16:56 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 26 16:56 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K Feb 25 17:18 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 17:18 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 17:18 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:18 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.7K Feb 26 16:59 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 104K Feb 26 16:59 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Feb 26 16:58 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 26 16:58 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 17:18 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 17:18 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 101K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Szymanski-PT-a04-CTLFireability-00
FORMULA_NAME Szymanski-PT-a04-CTLFireability-01
FORMULA_NAME Szymanski-PT-a04-CTLFireability-02
FORMULA_NAME Szymanski-PT-a04-CTLFireability-03
FORMULA_NAME Szymanski-PT-a04-CTLFireability-04
FORMULA_NAME Szymanski-PT-a04-CTLFireability-05
FORMULA_NAME Szymanski-PT-a04-CTLFireability-06
FORMULA_NAME Szymanski-PT-a04-CTLFireability-07
FORMULA_NAME Szymanski-PT-a04-CTLFireability-08
FORMULA_NAME Szymanski-PT-a04-CTLFireability-09
FORMULA_NAME Szymanski-PT-a04-CTLFireability-10
FORMULA_NAME Szymanski-PT-a04-CTLFireability-11
FORMULA_NAME Szymanski-PT-a04-CTLFireability-12
FORMULA_NAME Szymanski-PT-a04-CTLFireability-13
FORMULA_NAME Szymanski-PT-a04-CTLFireability-14
FORMULA_NAME Szymanski-PT-a04-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679187194087

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Szymanski-PT-a04
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 00:53:15] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 00:53:15] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 00:53:15] [INFO ] Load time of PNML (sax parser for PT used): 60 ms
[2023-03-19 00:53:15] [INFO ] Transformed 61 places.
[2023-03-19 00:53:15] [INFO ] Transformed 224 transitions.
[2023-03-19 00:53:15] [INFO ] Parsed PT model containing 61 places and 224 transitions and 900 arcs in 130 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 11 ms.
Deduced a syphon composed of 12 places in 1 ms
Reduce places removed 12 places and 8 transitions.
Initial state reduction rules removed 1 formulas.
FORMULA Szymanski-PT-a04-CTLFireability-03 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 42 out of 49 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 49/49 places, 216/216 transitions.
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 47 transition count 216
Applied a total of 2 rules in 13 ms. Remains 47 /49 variables (removed 2) and now considering 216/216 (removed 0) transitions.
[2023-03-19 00:53:15] [INFO ] Flow matrix only has 79 transitions (discarded 137 similar events)
// Phase 1: matrix 79 rows 47 cols
[2023-03-19 00:53:15] [INFO ] Computed 1 place invariants in 10 ms
[2023-03-19 00:53:16] [INFO ] Implicit Places using invariants in 379 ms returned []
[2023-03-19 00:53:16] [INFO ] Flow matrix only has 79 transitions (discarded 137 similar events)
[2023-03-19 00:53:16] [INFO ] Invariant cache hit.
[2023-03-19 00:53:16] [INFO ] State equation strengthened by 9 read => feed constraints.
[2023-03-19 00:53:16] [INFO ] Implicit Places using invariants and state equation in 77 ms returned []
Implicit Place search using SMT with State Equation took 483 ms to find 0 implicit places.
[2023-03-19 00:53:16] [INFO ] Flow matrix only has 79 transitions (discarded 137 similar events)
[2023-03-19 00:53:16] [INFO ] Invariant cache hit.
[2023-03-19 00:53:16] [INFO ] Dead Transitions using invariants and state equation in 98 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 47/49 places, 216/216 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 597 ms. Remains : 47/49 places, 216/216 transitions.
Support contains 42 out of 47 places after structural reductions.
[2023-03-19 00:53:16] [INFO ] Flatten gal took : 38 ms
[2023-03-19 00:53:16] [INFO ] Flatten gal took : 16 ms
[2023-03-19 00:53:16] [INFO ] Input system was already deterministic with 216 transitions.
Incomplete random walk after 10001 steps, including 22 resets, run finished after 328 ms. (steps per millisecond=30 ) properties (out of 62) seen :36
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 26) seen :1
Running SMT prover for 25 properties.
[2023-03-19 00:53:17] [INFO ] Flow matrix only has 79 transitions (discarded 137 similar events)
[2023-03-19 00:53:17] [INFO ] Invariant cache hit.
[2023-03-19 00:53:17] [INFO ] [Real]Absence check using 0 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-19 00:53:17] [INFO ] After 41ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1 real:24
[2023-03-19 00:53:17] [INFO ] State equation strengthened by 9 read => feed constraints.
[2023-03-19 00:53:17] [INFO ] After 4ms SMT Verify possible using 9 Read/Feed constraints in real domain returned unsat :0 sat :0 real:25
[2023-03-19 00:53:17] [INFO ] After 151ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:25
[2023-03-19 00:53:17] [INFO ] [Nat]Absence check using 0 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-19 00:53:17] [INFO ] After 125ms SMT Verify possible using state equation in natural domain returned unsat :3 sat :22
[2023-03-19 00:53:17] [INFO ] After 83ms SMT Verify possible using 9 Read/Feed constraints in natural domain returned unsat :3 sat :22
[2023-03-19 00:53:17] [INFO ] After 230ms SMT Verify possible using trap constraints in natural domain returned unsat :3 sat :22
Attempting to minimize the solution found.
Minimization took 87 ms.
[2023-03-19 00:53:17] [INFO ] After 552ms SMT Verify possible using all constraints in natural domain returned unsat :3 sat :22
Fused 25 Parikh solutions to 20 different solutions.
Parikh walk visited 0 properties in 52 ms.
Support contains 23 out of 47 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 44 transition count 204
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 44 transition count 204
Drop transitions removed 16 transitions
Redundant transition composition rules discarded 16 transitions
Iterating global reduction 0 with 16 rules applied. Total rules applied 22 place count 44 transition count 188
Applied a total of 22 rules in 21 ms. Remains 44 /47 variables (removed 3) and now considering 188/216 (removed 28) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 21 ms. Remains : 44/47 places, 188/216 transitions.
Incomplete random walk after 10000 steps, including 20 resets, run finished after 120 ms. (steps per millisecond=83 ) properties (out of 22) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 20) seen :0
Probabilistic random walk after 1000001 steps, saw 523388 distinct states, run finished after 1519 ms. (steps per millisecond=658 ) properties seen :19
Running SMT prover for 1 properties.
[2023-03-19 00:53:19] [INFO ] Flow matrix only has 72 transitions (discarded 116 similar events)
// Phase 1: matrix 72 rows 44 cols
[2023-03-19 00:53:19] [INFO ] Computed 1 place invariants in 1 ms
[2023-03-19 00:53:19] [INFO ] [Real]Absence check using 0 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-19 00:53:19] [INFO ] After 46ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 00:53:19] [INFO ] State equation strengthened by 9 read => feed constraints.
[2023-03-19 00:53:19] [INFO ] After 6ms SMT Verify possible using 9 Read/Feed constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 00:53:19] [INFO ] After 162ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 00:53:19] [INFO ] [Nat]Absence check using 0 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-19 00:53:19] [INFO ] After 17ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 00:53:19] [INFO ] After 4ms SMT Verify possible using 9 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 00:53:19] [INFO ] After 28ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 5 ms.
[2023-03-19 00:53:19] [INFO ] After 86ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 0 ms.
Support contains 3 out of 44 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 44/44 places, 188/188 transitions.
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 44 transition count 186
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 5 place count 41 transition count 174
Iterating global reduction 1 with 3 rules applied. Total rules applied 8 place count 41 transition count 174
Applied a total of 8 rules in 10 ms. Remains 41 /44 variables (removed 3) and now considering 174/188 (removed 14) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 12 ms. Remains : 41/44 places, 174/188 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=1250 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=2000 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2185174 steps, run timeout after 3001 ms. (steps per millisecond=728 ) properties seen :{}
Probabilistic random walk after 2185174 steps, saw 1011857 distinct states, run finished after 3002 ms. (steps per millisecond=727 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-19 00:53:22] [INFO ] Flow matrix only has 67 transitions (discarded 107 similar events)
// Phase 1: matrix 67 rows 41 cols
[2023-03-19 00:53:22] [INFO ] Computed 1 place invariants in 5 ms
[2023-03-19 00:53:22] [INFO ] [Real]Absence check using 0 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-19 00:53:23] [INFO ] After 36ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 00:53:23] [INFO ] State equation strengthened by 9 read => feed constraints.
[2023-03-19 00:53:23] [INFO ] After 4ms SMT Verify possible using 9 Read/Feed constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 00:53:23] [INFO ] After 86ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 00:53:23] [INFO ] [Nat]Absence check using 0 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-19 00:53:23] [INFO ] After 17ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 00:53:23] [INFO ] After 5ms SMT Verify possible using 9 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 00:53:23] [INFO ] After 10ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 3 ms.
[2023-03-19 00:53:23] [INFO ] After 88ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 0 ms.
Support contains 3 out of 41 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 41/41 places, 174/174 transitions.
Applied a total of 0 rules in 14 ms. Remains 41 /41 variables (removed 0) and now considering 174/174 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 14 ms. Remains : 41/41 places, 174/174 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 41/41 places, 174/174 transitions.
Applied a total of 0 rules in 5 ms. Remains 41 /41 variables (removed 0) and now considering 174/174 (removed 0) transitions.
[2023-03-19 00:53:23] [INFO ] Flow matrix only has 67 transitions (discarded 107 similar events)
[2023-03-19 00:53:23] [INFO ] Invariant cache hit.
[2023-03-19 00:53:23] [INFO ] Implicit Places using invariants in 72 ms returned []
[2023-03-19 00:53:23] [INFO ] Flow matrix only has 67 transitions (discarded 107 similar events)
[2023-03-19 00:53:23] [INFO ] Invariant cache hit.
[2023-03-19 00:53:23] [INFO ] State equation strengthened by 9 read => feed constraints.
[2023-03-19 00:53:23] [INFO ] Implicit Places using invariants and state equation in 86 ms returned []
Implicit Place search using SMT with State Equation took 160 ms to find 0 implicit places.
[2023-03-19 00:53:23] [INFO ] Redundant transitions in 5 ms returned []
[2023-03-19 00:53:23] [INFO ] Flow matrix only has 67 transitions (discarded 107 similar events)
[2023-03-19 00:53:23] [INFO ] Invariant cache hit.
[2023-03-19 00:53:23] [INFO ] Dead Transitions using invariants and state equation in 102 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 284 ms. Remains : 41/41 places, 174/174 transitions.
Graph (trivial) has 131 edges and 41 vertex of which 22 / 41 are part of one of the 5 SCC in 3 ms
Free SCC test removed 17 places
Drop transitions removed 95 transitions
Ensure Unique test removed 37 transitions
Reduce isomorphic transitions removed 132 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 0 with 5 rules applied. Total rules applied 6 place count 24 transition count 37
Reduce places removed 5 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 6 rules applied. Total rules applied 12 place count 19 transition count 36
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 13 place count 18 transition count 36
Partial Free-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 14 place count 18 transition count 36
Applied a total of 14 rules in 7 ms. Remains 18 /41 variables (removed 23) and now considering 36/174 (removed 138) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 36 rows 18 cols
[2023-03-19 00:53:23] [INFO ] Computed 1 place invariants in 1 ms
[2023-03-19 00:53:23] [INFO ] [Real]Absence check using 0 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-19 00:53:23] [INFO ] After 9ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 00:53:23] [INFO ] State equation strengthened by 3 read => feed constraints.
[2023-03-19 00:53:23] [INFO ] After 5ms SMT Verify possible using 3 Read/Feed constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 00:53:23] [INFO ] After 36ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 00:53:23] [INFO ] [Nat]Absence check using 0 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-19 00:53:23] [INFO ] After 9ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 00:53:23] [INFO ] After 3ms SMT Verify possible using 3 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 00:53:23] [INFO ] After 5ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 3 ms.
[2023-03-19 00:53:23] [INFO ] After 37ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Successfully simplified 3 atomic propositions for a total of 14 simplifications.
[2023-03-19 00:53:23] [INFO ] Flatten gal took : 10 ms
[2023-03-19 00:53:23] [INFO ] Flatten gal took : 36 ms
[2023-03-19 00:53:23] [INFO ] Input system was already deterministic with 216 transitions.
Computed a total of 9 stabilizing places and 36 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 43 transition count 200
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 43 transition count 200
Applied a total of 8 rules in 2 ms. Remains 43 /47 variables (removed 4) and now considering 200/216 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 43/47 places, 200/216 transitions.
[2023-03-19 00:53:23] [INFO ] Flatten gal took : 14 ms
[2023-03-19 00:53:23] [INFO ] Flatten gal took : 27 ms
[2023-03-19 00:53:23] [INFO ] Input system was already deterministic with 200 transitions.
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 43 transition count 200
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 43 transition count 200
Applied a total of 8 rules in 1 ms. Remains 43 /47 variables (removed 4) and now considering 200/216 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 43/47 places, 200/216 transitions.
[2023-03-19 00:53:23] [INFO ] Flatten gal took : 9 ms
[2023-03-19 00:53:23] [INFO ] Flatten gal took : 10 ms
[2023-03-19 00:53:23] [INFO ] Input system was already deterministic with 200 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 43 transition count 200
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 43 transition count 200
Drop transitions removed 16 transitions
Redundant transition composition rules discarded 16 transitions
Iterating global reduction 0 with 16 rules applied. Total rules applied 24 place count 43 transition count 184
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 26 place count 41 transition count 176
Iterating global reduction 0 with 2 rules applied. Total rules applied 28 place count 41 transition count 176
Applied a total of 28 rules in 13 ms. Remains 41 /47 variables (removed 6) and now considering 176/216 (removed 40) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 41/47 places, 176/216 transitions.
[2023-03-19 00:53:23] [INFO ] Flatten gal took : 8 ms
[2023-03-19 00:53:23] [INFO ] Flatten gal took : 21 ms
[2023-03-19 00:53:23] [INFO ] Input system was already deterministic with 176 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 42 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 42 transition count 196
Drop transitions removed 16 transitions
Redundant transition composition rules discarded 16 transitions
Iterating global reduction 0 with 16 rules applied. Total rules applied 26 place count 42 transition count 180
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 28 place count 40 transition count 172
Iterating global reduction 0 with 2 rules applied. Total rules applied 30 place count 40 transition count 172
Applied a total of 30 rules in 11 ms. Remains 40 /47 variables (removed 7) and now considering 172/216 (removed 44) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 40/47 places, 172/216 transitions.
[2023-03-19 00:53:23] [INFO ] Flatten gal took : 8 ms
[2023-03-19 00:53:23] [INFO ] Flatten gal took : 8 ms
[2023-03-19 00:53:23] [INFO ] Input system was already deterministic with 172 transitions.
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 42 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 42 transition count 196
Applied a total of 10 rules in 3 ms. Remains 42 /47 variables (removed 5) and now considering 196/216 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 42/47 places, 196/216 transitions.
[2023-03-19 00:53:23] [INFO ] Flatten gal took : 7 ms
[2023-03-19 00:53:23] [INFO ] Flatten gal took : 7 ms
[2023-03-19 00:53:23] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 42 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 42 transition count 196
Drop transitions removed 16 transitions
Redundant transition composition rules discarded 16 transitions
Iterating global reduction 0 with 16 rules applied. Total rules applied 26 place count 42 transition count 180
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 28 place count 40 transition count 172
Iterating global reduction 0 with 2 rules applied. Total rules applied 30 place count 40 transition count 172
Applied a total of 30 rules in 12 ms. Remains 40 /47 variables (removed 7) and now considering 172/216 (removed 44) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 40/47 places, 172/216 transitions.
[2023-03-19 00:53:23] [INFO ] Flatten gal took : 6 ms
[2023-03-19 00:53:23] [INFO ] Flatten gal took : 7 ms
[2023-03-19 00:53:24] [INFO ] Input system was already deterministic with 172 transitions.
Incomplete random walk after 10002 steps, including 12 resets, run finished after 8 ms. (steps per millisecond=1250 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 7 resets, run finished after 6 ms. (steps per millisecond=1666 ) properties (out of 1) seen :0
Finished probabilistic random walk after 4643 steps, run visited all 1 properties in 12 ms. (steps per millisecond=386 )
Probabilistic random walk after 4643 steps, saw 3386 distinct states, run finished after 12 ms. (steps per millisecond=386 ) properties seen :1
FORMULA Szymanski-PT-a04-CTLFireability-06 TRUE TECHNIQUES TOPOLOGICAL PROBABILISTIC_WALK
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 43 transition count 200
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 43 transition count 200
Applied a total of 8 rules in 2 ms. Remains 43 /47 variables (removed 4) and now considering 200/216 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 43/47 places, 200/216 transitions.
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 7 ms
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 7 ms
[2023-03-19 00:53:24] [INFO ] Input system was already deterministic with 200 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 42 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 42 transition count 196
Drop transitions removed 12 transitions
Redundant transition composition rules discarded 12 transitions
Iterating global reduction 0 with 12 rules applied. Total rules applied 22 place count 42 transition count 184
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 23 place count 41 transition count 180
Iterating global reduction 0 with 1 rules applied. Total rules applied 24 place count 41 transition count 180
Applied a total of 24 rules in 11 ms. Remains 41 /47 variables (removed 6) and now considering 180/216 (removed 36) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 41/47 places, 180/216 transitions.
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 5 ms
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 6 ms
[2023-03-19 00:53:24] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 42 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 42 transition count 196
Applied a total of 10 rules in 2 ms. Remains 42 /47 variables (removed 5) and now considering 196/216 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 42/47 places, 196/216 transitions.
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 5 ms
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 6 ms
[2023-03-19 00:53:24] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 2 place count 45 transition count 208
Iterating global reduction 0 with 2 rules applied. Total rules applied 4 place count 45 transition count 208
Applied a total of 4 rules in 2 ms. Remains 45 /47 variables (removed 2) and now considering 208/216 (removed 8) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 45/47 places, 208/216 transitions.
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 5 ms
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 7 ms
[2023-03-19 00:53:24] [INFO ] Input system was already deterministic with 208 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 42 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 42 transition count 196
Drop transitions removed 16 transitions
Redundant transition composition rules discarded 16 transitions
Iterating global reduction 0 with 16 rules applied. Total rules applied 26 place count 42 transition count 180
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 28 place count 40 transition count 172
Iterating global reduction 0 with 2 rules applied. Total rules applied 30 place count 40 transition count 172
Applied a total of 30 rules in 22 ms. Remains 40 /47 variables (removed 7) and now considering 172/216 (removed 44) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 22 ms. Remains : 40/47 places, 172/216 transitions.
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 5 ms
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 22 ms
[2023-03-19 00:53:24] [INFO ] Input system was already deterministic with 172 transitions.
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 44 transition count 204
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 44 transition count 204
Applied a total of 6 rules in 18 ms. Remains 44 /47 variables (removed 3) and now considering 204/216 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 18 ms. Remains : 44/47 places, 204/216 transitions.
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 6 ms
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 6 ms
[2023-03-19 00:53:24] [INFO ] Input system was already deterministic with 204 transitions.
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 5 place count 42 transition count 196
Iterating global reduction 0 with 5 rules applied. Total rules applied 10 place count 42 transition count 196
Applied a total of 10 rules in 2 ms. Remains 42 /47 variables (removed 5) and now considering 196/216 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 42/47 places, 196/216 transitions.
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 21 ms
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 5 ms
[2023-03-19 00:53:24] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 43 transition count 200
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 43 transition count 200
Drop transitions removed 16 transitions
Redundant transition composition rules discarded 16 transitions
Iterating global reduction 0 with 16 rules applied. Total rules applied 24 place count 43 transition count 184
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 25 place count 42 transition count 180
Iterating global reduction 0 with 1 rules applied. Total rules applied 26 place count 42 transition count 180
Applied a total of 26 rules in 10 ms. Remains 42 /47 variables (removed 5) and now considering 180/216 (removed 36) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 42/47 places, 180/216 transitions.
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 21 ms
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 5 ms
[2023-03-19 00:53:24] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 216/216 transitions.
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 2 place count 45 transition count 208
Iterating global reduction 0 with 2 rules applied. Total rules applied 4 place count 45 transition count 208
Applied a total of 4 rules in 1 ms. Remains 45 /47 variables (removed 2) and now considering 208/216 (removed 8) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 45/47 places, 208/216 transitions.
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 5 ms
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 6 ms
[2023-03-19 00:53:24] [INFO ] Input system was already deterministic with 208 transitions.
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 7 ms
[2023-03-19 00:53:24] [INFO ] Flatten gal took : 7 ms
[2023-03-19 00:53:24] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-19 00:53:24] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 47 places, 216 transitions and 860 arcs took 1 ms.
Total runtime 8953 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Szymanski-PT-a04
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA Szymanski-PT-a04-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Szymanski-PT-a04-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Szymanski-PT-a04-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Szymanski-PT-a04-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Szymanski-PT-a04-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Szymanski-PT-a04-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Szymanski-PT-a04-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Szymanski-PT-a04-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Szymanski-PT-a04-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679187375883

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 40 (type EXCL) for 39 Szymanski-PT-a04-CTLFireability-15
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for Szymanski-PT-a04-CTLFireability-15
lola: result : false
lola: markings : 74
lola: fired transitions : 166
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 1 (type EXCL) for 0 Szymanski-PT-a04-CTLFireability-00
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 1 (type EXCL) for Szymanski-PT-a04-CTLFireability-00
lola: result : true
lola: markings : 437
lola: fired transitions : 1003
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 Szymanski-PT-a04-CTLFireability-02
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 7 (type EXCL) for Szymanski-PT-a04-CTLFireability-02
lola: result : true
lola: markings : 437
lola: fired transitions : 575
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 Szymanski-PT-a04-CTLFireability-09
lola: time limit : 300 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for Szymanski-PT-a04-CTLFireability-09
lola: result : true
lola: markings : 116
lola: fired transitions : 128
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 Szymanski-PT-a04-CTLFireability-14
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for Szymanski-PT-a04-CTLFireability-14
lola: result : true
lola: markings : 24
lola: fired transitions : 68
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:746
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 16 (type EXCL) for 15 Szymanski-PT-a04-CTLFireability-07
lola: time limit : 360 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/400 7/32 Szymanski-PT-a04-CTLFireability-07 1510194 m, 302038 m/sec, 3793839 t fired, .

Time elapsed: 5 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/400 13/32 Szymanski-PT-a04-CTLFireability-07 2940422 m, 286045 m/sec, 7427859 t fired, .

Time elapsed: 10 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 15/400 18/32 Szymanski-PT-a04-CTLFireability-07 4355971 m, 283109 m/sec, 10987221 t fired, .

Time elapsed: 15 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 20/400 24/32 Szymanski-PT-a04-CTLFireability-07 5714833 m, 271772 m/sec, 14500979 t fired, .

Time elapsed: 20 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 25/400 29/32 Szymanski-PT-a04-CTLFireability-07 7022085 m, 261450 m/sec, 17972606 t fired, .

Time elapsed: 25 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 16 (type EXCL) for Szymanski-PT-a04-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 34 (type EXCL) for 33 Szymanski-PT-a04-CTLFireability-13
lola: time limit : 446 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for Szymanski-PT-a04-CTLFireability-13
lola: result : false
lola: markings : 116
lola: fired transitions : 128
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 Szymanski-PT-a04-CTLFireability-12
lola: time limit : 510 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/510 5/32 Szymanski-PT-a04-CTLFireability-12 1066888 m, 213377 m/sec, 2784636 t fired, .

Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 10/510 9/32 Szymanski-PT-a04-CTLFireability-12 2050694 m, 196761 m/sec, 5314546 t fired, .

Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 15/510 13/32 Szymanski-PT-a04-CTLFireability-12 3085806 m, 207022 m/sec, 7919697 t fired, .

Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 20/510 17/32 Szymanski-PT-a04-CTLFireability-12 4124000 m, 207638 m/sec, 10531824 t fired, .

Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 25/510 22/32 Szymanski-PT-a04-CTLFireability-12 5137924 m, 202784 m/sec, 13125712 t fired, .

Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 30/510 26/32 Szymanski-PT-a04-CTLFireability-12 6117119 m, 195839 m/sec, 15691839 t fired, .

Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 35/510 30/32 Szymanski-PT-a04-CTLFireability-12 7069366 m, 190449 m/sec, 18228410 t fired, .

Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 31 (type EXCL) for Szymanski-PT-a04-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 25 (type EXCL) for 24 Szymanski-PT-a04-CTLFireability-10
lola: time limit : 588 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/588 4/32 Szymanski-PT-a04-CTLFireability-10 933101 m, 186620 m/sec, 5045127 t fired, .

Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 10/588 8/32 Szymanski-PT-a04-CTLFireability-10 1817654 m, 176910 m/sec, 9721735 t fired, .

Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 15/588 12/32 Szymanski-PT-a04-CTLFireability-10 2683453 m, 173159 m/sec, 14333978 t fired, .

Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 20/588 15/32 Szymanski-PT-a04-CTLFireability-10 3578245 m, 178958 m/sec, 19006080 t fired, .

Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 25/588 19/32 Szymanski-PT-a04-CTLFireability-10 4463609 m, 177072 m/sec, 23633883 t fired, .

Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 30/588 22/32 Szymanski-PT-a04-CTLFireability-10 5321675 m, 171613 m/sec, 28160336 t fired, .

Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 35/588 26/32 Szymanski-PT-a04-CTLFireability-10 6158652 m, 167395 m/sec, 32610971 t fired, .

Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 40/588 29/32 Szymanski-PT-a04-CTLFireability-10 6974215 m, 163112 m/sec, 36988791 t fired, .

Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 45/588 32/32 Szymanski-PT-a04-CTLFireability-10 7770103 m, 159177 m/sec, 41308502 t fired, .

Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 25 (type EXCL) for Szymanski-PT-a04-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 13 (type EXCL) for 12 Szymanski-PT-a04-CTLFireability-05
lola: time limit : 696 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for Szymanski-PT-a04-CTLFireability-05
lola: result : true
lola: markings : 11673
lola: fired transitions : 41978
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 Szymanski-PT-a04-CTLFireability-01
lola: time limit : 870 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-05: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/870 9/32 Szymanski-PT-a04-CTLFireability-01 1944669 m, 388933 m/sec, 4918213 t fired, .

Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-05: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/870 16/32 Szymanski-PT-a04-CTLFireability-01 3732598 m, 357585 m/sec, 9411231 t fired, .

Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-05: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/870 23/32 Szymanski-PT-a04-CTLFireability-01 5440378 m, 341556 m/sec, 13784811 t fired, .

Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-05: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/870 29/32 Szymanski-PT-a04-CTLFireability-01 7015514 m, 315027 m/sec, 17953989 t fired, .

Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 4 (type EXCL) for Szymanski-PT-a04-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-05: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-11: AGEFAG 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 42 (type EXCL) for 27 Szymanski-PT-a04-CTLFireability-11
lola: time limit : 1151 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for Szymanski-PT-a04-CTLFireability-11
lola: result : true
lola: markings : 118
lola: fired transitions : 131
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 Szymanski-PT-a04-CTLFireability-04
lola: time limit : 1727 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-05: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-11: AGEFAG false tscc_search
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/1727 9/32 Szymanski-PT-a04-CTLFireability-04 1958981 m, 391796 m/sec, 4954260 t fired, .

Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-05: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-11: AGEFAG false tscc_search
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/1727 16/32 Szymanski-PT-a04-CTLFireability-04 3776576 m, 363519 m/sec, 9523141 t fired, .

Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-05: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-11: AGEFAG false tscc_search
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/1727 23/32 Szymanski-PT-a04-CTLFireability-04 5500049 m, 344694 m/sec, 13939573 t fired, .

Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-05: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-11: AGEFAG false tscc_search
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 0 1 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/1727 30/32 Szymanski-PT-a04-CTLFireability-04 7091240 m, 318238 m/sec, 18158012 t fired, .

Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 10 (type EXCL) for Szymanski-PT-a04-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-05: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-11: AGEFAG false tscc_search
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-a04-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-04: AFAG 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-a04-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Szymanski-PT-a04-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 19 (type EXCL) for 18 Szymanski-PT-a04-CTLFireability-08
lola: time limit : 3430 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for Szymanski-PT-a04-CTLFireability-08
lola: result : true
lola: markings : 404
lola: fired transitions : 575
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 14

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-a04-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-01: CTL unknown AGGR
Szymanski-PT-a04-CTLFireability-02: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-04: AFAG unknown AGGR
Szymanski-PT-a04-CTLFireability-05: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-07: CTL unknown AGGR
Szymanski-PT-a04-CTLFireability-08: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-09: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-10: CTL unknown AGGR
Szymanski-PT-a04-CTLFireability-11: AGEFAG false tscc_search
Szymanski-PT-a04-CTLFireability-12: CTL unknown AGGR
Szymanski-PT-a04-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-a04-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-a04-CTLFireability-15: CTL false CTL model checker


Time elapsed: 170 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Szymanski-PT-a04"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Szymanski-PT-a04, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r487-tall-167912703000410"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Szymanski-PT-a04.tgz
mv Szymanski-PT-a04 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;