fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r486-tall-167912702201138
Last Updated
May 14, 2023

About the Execution of LoLA for UtilityControlRoom-PT-Z2T4N06

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
2250.023 241199.00 235468.00 545.60 F?TFTT?FTTTTFT?T normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r486-tall-167912702201138.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is UtilityControlRoom-PT-Z2T4N06, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r486-tall-167912702201138
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 968K
-rw-r--r-- 1 mcc users 18K Feb 26 14:45 CTLCardinality.txt
-rw-r--r-- 1 mcc users 115K Feb 26 14:45 CTLCardinality.xml
-rw-r--r-- 1 mcc users 29K Feb 26 14:43 CTLFireability.txt
-rw-r--r-- 1 mcc users 146K Feb 26 14:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 9.6K Feb 25 17:25 LTLCardinality.txt
-rw-r--r-- 1 mcc users 40K Feb 25 17:25 LTLCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 25 17:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 42K Feb 25 17:25 LTLFireability.xml
-rw-r--r-- 1 mcc users 43K Feb 26 14:48 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 218K Feb 26 14:48 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 33K Feb 26 14:47 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 146K Feb 26 14:47 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 17:25 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.2K Feb 25 17:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 70K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-00
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-01
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-02
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-03
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-04
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-05
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-06
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-07
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-08
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-09
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-10
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-11
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-12
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-13
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-14
FORMULA_NAME UtilityControlRoom-PT-Z2T4N06-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679279625099

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-PT-Z2T4N06
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT UtilityControlRoom-PT-Z2T4N06
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA UtilityControlRoom-PT-Z2T4N06-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N06-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N06-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N06-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N06-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N06-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N06-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N06-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N06-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N06-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N06-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N06-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-PT-Z2T4N06-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679279866298

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:463
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: LAUNCH task # 69 (type SKEL/SRCH) for 31 UtilityControlRoom-PT-Z2T4N06-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 69 (type SKEL/SRCH) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-05
lola: result : false
lola: markings : 536
lola: fired transitions : 1203
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 3 UtilityControlRoom-PT-Z2T4N06-CTLFireability-01
lola: time limit : 102 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 10 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-01
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 19 (type EXCL) for 18 UtilityControlRoom-PT-Z2T4N06-CTLFireability-02
lola: time limit : 105 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 19 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-02
lola: result : true
lola: markings : 30443
lola: fired transitions : 90626
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 63 (type EXCL) for 62 UtilityControlRoom-PT-Z2T4N06-CTLFireability-14
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 5/189 4/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-14 823417 m, 164683 m/sec, 3131318 t fired, .

Time elapsed: 5 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 10/189 7/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-14 1570107 m, 149338 m/sec, 6106408 t fired, .

Time elapsed: 10 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 15/189 10/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-14 2284478 m, 142874 m/sec, 9044834 t fired, .

Time elapsed: 15 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 20/189 13/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-14 2970951 m, 137294 m/sec, 11960913 t fired, .

Time elapsed: 20 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 25/189 16/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-14 3643378 m, 134485 m/sec, 14910747 t fired, .

Time elapsed: 25 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 30/189 19/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-14 4291155 m, 129555 m/sec, 17871492 t fired, .

Time elapsed: 30 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 35/189 22/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-14 4934262 m, 128621 m/sec, 20967950 t fired, .

Time elapsed: 35 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 40/189 24/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-14 5536984 m, 120544 m/sec, 24213115 t fired, .

Time elapsed: 40 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 45/189 26/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-14 6041202 m, 100843 m/sec, 27223156 t fired, .

Time elapsed: 45 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 50/189 28/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-14 6516411 m, 95041 m/sec, 30145726 t fired, .

Time elapsed: 50 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 55/189 30/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-14 6980832 m, 92884 m/sec, 33095496 t fired, .

Time elapsed: 55 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 60/189 32/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-14 7430289 m, 89891 m/sec, 36091561 t fired, .

Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 63 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 60 (type EXCL) for 59 UtilityControlRoom-PT-Z2T4N06-CTLFireability-13
lola: time limit : 196 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-13
lola: result : true
lola: markings : 251685
lola: fired transitions : 875839
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 57 (type EXCL) for 56 UtilityControlRoom-PT-Z2T4N06-CTLFireability-12
lola: time limit : 207 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-12
lola: result : false
lola: markings : 969459
lola: fired transitions : 2729882
lola: time used : 4.000000
lola: memory pages used : 5
lola: LAUNCH task # 48 (type EXCL) for 47 UtilityControlRoom-PT-Z2T4N06-CTLFireability-09
lola: time limit : 220 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-09
lola: result : true
lola: markings : 36
lola: fired transitions : 37
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 44 UtilityControlRoom-PT-Z2T4N06-CTLFireability-08
lola: time limit : 235 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 0/235 1/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-08 139840 m, 27968 m/sec, 359463 t fired, .

Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 5/235 5/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-08 950742 m, 162180 m/sec, 3844848 t fired, .

Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 10/235 8/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-08 1755392 m, 160930 m/sec, 7149486 t fired, .

Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 15/235 11/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-08 2520100 m, 152941 m/sec, 10391877 t fired, .

Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 20/235 14/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-08 3253269 m, 146633 m/sec, 13620684 t fired, .

Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 25/235 17/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-08 3960152 m, 141376 m/sec, 16888208 t fired, .

Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 30/235 20/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-08 4621078 m, 132185 m/sec, 20291286 t fired, .

Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 35/235 22/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-08 5165403 m, 108865 m/sec, 23508177 t fired, .

Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 40/235 25/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-08 5686504 m, 104220 m/sec, 26720583 t fired, .

Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 45/235 27/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-08 6174664 m, 97632 m/sec, 29845163 t fired, .

Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 50/235 29/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-08 6647041 m, 94475 m/sec, 33050256 t fired, .

Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 45 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-08
lola: result : true
lola: markings : 6739217
lola: fired transitions : 33725209
lola: time used : 51.000000
lola: memory pages used : 29
lola: LAUNCH task # 42 (type EXCL) for 41 UtilityControlRoom-PT-Z2T4N06-CTLFireability-07
lola: time limit : 248 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-07
lola: result : false
lola: markings : 8387
lola: fired transitions : 25393
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 UtilityControlRoom-PT-Z2T4N06-CTLFireability-06
lola: time limit : 267 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 4/267 3/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-06 653930 m, 130786 m/sec, 2680450 t fired, .

Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 9/267 7/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-06 1385957 m, 146405 m/sec, 5824514 t fired, .

Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 14/267 10/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-06 2071107 m, 137030 m/sec, 8860975 t fired, .

Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 19/267 12/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-06 2727611 m, 131300 m/sec, 11844095 t fired, .

Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 24/267 15/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-06 3360933 m, 126664 m/sec, 14793863 t fired, .

Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 29/267 18/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-06 3972028 m, 122219 m/sec, 17706814 t fired, .

Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 34/267 20/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-06 4585074 m, 122609 m/sec, 20694080 t fired, .

Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 39/267 23/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-06 5186896 m, 120364 m/sec, 23690947 t fired, .

Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 44/267 25/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-06 5756303 m, 113881 m/sec, 26581605 t fired, .

Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 49/267 28/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-06 6309684 m, 110676 m/sec, 29446122 t fired, .

Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 54/267 30/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-06 6854081 m, 108879 m/sec, 32316749 t fired, .

Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 59/267 32/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-06 7388311 m, 106846 m/sec, 35181419 t fired, .

Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 39 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 3 0 0 5 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 34 (type EXCL) for 31 UtilityControlRoom-PT-Z2T4N06-CTLFireability-05
lola: time limit : 284 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-05
lola: result : true
lola: markings : 36
lola: fired transitions : 36
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 UtilityControlRoom-PT-Z2T4N06-CTLFireability-04
lola: time limit : 341 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-04
lola: result : true
lola: markings : 250957
lola: fired transitions : 1154440
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 26 (type EXCL) for 21 UtilityControlRoom-PT-Z2T4N06-CTLFireability-03
lola: time limit : 379 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-03
lola: result : false
lola: markings : 38
lola: fired transitions : 39
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 3 UtilityControlRoom-PT-Z2T4N06-CTLFireability-01
lola: time limit : 426 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-01
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 3 UtilityControlRoom-PT-Z2T4N06-CTLFireability-01
lola: time limit : 487 sec
lola: memory limit: 32 pages
lola: FINISHED task # 14 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-01
lola: result : false
lola: markings : 33
lola: fired transitions : 47
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 6 (type EXCL) for 3 UtilityControlRoom-PT-Z2T4N06-CTLFireability-01
lola: time limit : 569 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 0 1 0 7 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 4/569 4/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-01 764822 m, 152964 m/sec, 3605695 t fired, .

Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 0 1 0 7 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 9/569 7/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-01 1574586 m, 161952 m/sec, 8551312 t fired, .

Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 0 1 0 7 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 14/569 10/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-01 2273948 m, 139872 m/sec, 13601650 t fired, .

Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 0 1 0 7 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 19/569 13/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-01 2967886 m, 138787 m/sec, 18575343 t fired, .

Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 0 1 0 7 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 24/569 16/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-01 3569324 m, 120287 m/sec, 23595620 t fired, .

Time elapsed: 210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 0 1 0 7 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 29/569 19/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-01 4310778 m, 148290 m/sec, 28142474 t fired, .

Time elapsed: 215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 0 1 0 7 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 34/569 22/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-01 5105042 m, 158852 m/sec, 33016563 t fired, .

Time elapsed: 220 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 0 1 0 7 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 39/569 25/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-01 5812544 m, 141500 m/sec, 37975745 t fired, .

Time elapsed: 225 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 0 1 0 7 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 44/569 28/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-01 6493660 m, 136223 m/sec, 42834608 t fired, .

Time elapsed: 230 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 0 1 0 7 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 49/569 31/32 UtilityControlRoom-PT-Z2T4N06-CTLFireability-01 7088027 m, 118873 m/sec, 47763805 t fired, .

Time elapsed: 235 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 6 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ 0 0 0 0 7 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 240 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 1 (type EXCL) for 0 UtilityControlRoom-PT-Z2T4N06-CTLFireability-00
lola: time limit : 672 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-00
lola: result : false
lola: markings : 360
lola: fired transitions : 680
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 51 (type EXCL) for 50 UtilityControlRoom-PT-Z2T4N06-CTLFireability-10
lola: time limit : 840 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-10
lola: result : true
lola: markings : 555
lola: fired transitions : 910
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 53 UtilityControlRoom-PT-Z2T4N06-CTLFireability-11
lola: time limit : 1120 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-11
lola: result : true
lola: markings : 81139
lola: fired transitions : 400358
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 21 UtilityControlRoom-PT-Z2T4N06-CTLFireability-03
lola: time limit : 1679 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-03
lola: result : false
lola: markings : 2054
lola: fired transitions : 2462
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 66 (type EXCL) for 65 UtilityControlRoom-PT-Z2T4N06-CTLFireability-15
lola: time limit : 3359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 66 (type EXCL) for UtilityControlRoom-PT-Z2T4N06-CTLFireability-15
lola: result : true
lola: markings : 31
lola: fired transitions : 44
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-PT-Z2T4N06-CTLFireability-00: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-01: DISJ unknown DISJ
UtilityControlRoom-PT-Z2T4N06-CTLFireability-02: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-03: DISJ false DISJ
UtilityControlRoom-PT-Z2T4N06-CTLFireability-04: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-05: DISJ true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-06: CTL unknown AGGR
UtilityControlRoom-PT-Z2T4N06-CTLFireability-07: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-08: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-09: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-10: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-11: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-12: CTL false CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-13: CTL true CTL model checker
UtilityControlRoom-PT-Z2T4N06-CTLFireability-14: CTL unknown AGGR
UtilityControlRoom-PT-Z2T4N06-CTLFireability-15: CTL true CTL model checker


Time elapsed: 241 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-PT-Z2T4N06"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-PT-Z2T4N06, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r486-tall-167912702201138"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-PT-Z2T4N06.tgz
mv UtilityControlRoom-PT-Z2T4N06 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;