About the Execution of LoLA for UtilityControlRoom-COL-Z4T3N10
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 8543.936 | 284393.00 | 277655.00 | 923.80 | TTF???FF?FTFFT?F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r486-tall-167912702001042.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is UtilityControlRoom-COL-Z4T3N10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r486-tall-167912702001042
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 528K
-rw-r--r-- 1 mcc users 8.4K Feb 26 14:42 CTLCardinality.txt
-rw-r--r-- 1 mcc users 79K Feb 26 14:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.8K Feb 26 14:37 CTLFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 26 14:37 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.4K Feb 25 17:25 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 17:25 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Feb 25 17:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:25 LTLFireability.xml
-rw-r--r-- 1 mcc users 18K Feb 26 14:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 166K Feb 26 14:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 14:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 72K Feb 26 14:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 17:25 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 17:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 29K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-00
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-01
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-02
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-03
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-04
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-05
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-06
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-07
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-08
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-09
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-10
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-11
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-12
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-13
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-14
FORMULA_NAME UtilityControlRoom-COL-Z4T3N10-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679271606888
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-COL-Z4T3N10
Not applying reductions.
Model is COL
CTLFireability PT
[2023-03-20 00:20:08] [INFO ] Running its-tools with arguments : [-pnfolder, ., -examination, CTLFireability, --reduce-single, STATESPACE]
[2023-03-20 00:20:08] [INFO ] Parsing pnml file : /home/mcc/execution/./model.pnml
[2023-03-20 00:20:08] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-20 00:20:08] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-20 00:20:08] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 409 ms
[2023-03-20 00:20:08] [INFO ] Imported 13 HL places and 12 HL transitions for a total of 376 PT places and 750.0 transition bindings in 12 ms.
Parsed 16 properties from file ./CTLFireability.xml in 12 ms.
[2023-03-20 00:20:08] [INFO ] Unfolded HLPN to a Petri net with 376 places and 750 transitions 2410 arcs in 24 ms.
[2023-03-20 00:20:08] [INFO ] Unfolded 16 HLPN properties in 2 ms.
[2023-03-20 00:20:08] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 00:20:08] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 00:20:08] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 00:20:08] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 00:20:08] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 00:20:08] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 00:20:08] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 00:20:08] [INFO ] Reduced 30 identical enabling conditions.
[2023-03-20 00:20:08] [INFO ] Reduced 30 identical enabling conditions.
Ensure Unique test removed 160 transitions
Reduce isomorphic transitions removed 160 transitions.
Drop transitions removed 40 transitions
Redundant transition composition rules discarded 40 transitions
[2023-03-20 00:20:08] [INFO ] Export to MCC of 16 properties in file ./CTLFireability.STATESPACE.xml took 92 ms.
[2023-03-20 00:20:08] [INFO ] Export to PNML in file ./model.STATESPACE.pnml of net with 376 places, 550 transitions and 1610 arcs took 3 ms.
Total runtime 707 ms.
starting LoLA
BK_INPUT UtilityControlRoom-COL-Z4T3N10
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution/unfCTLFireability
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA UtilityControlRoom-COL-Z4T3N10-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679271891281
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/unfCTLFireability/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/unfCTLFireability/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/unfCTLFireability/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 1 (type EXCL) for 0 UtilityControlRoom-COL-Z4T3N10-CTLFireability-00
lola: time limit : 123 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 1 (type EXCL) for UtilityControlRoom-COL-Z4T3N10-CTLFireability-00
lola: result : true
lola: markings : 770
lola: fired transitions : 787
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 UtilityControlRoom-COL-Z4T3N10-CTLFireability-10
lola: time limit : 128 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
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lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:703
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
UtilityControlRoom-COL-Z4T3N10-CTLFireability-00: CTL true CTL model checker
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UtilityControlRoom-COL-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-12: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-13: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/210 8/32 UtilityControlRoom-COL-Z4T3N10-CTLFireability-10 1392750 m, 278550 m/sec, 1781412 t fired, .
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UtilityControlRoom-COL-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-12: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-13: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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31 CTL EXCL 10/210 10/32 UtilityControlRoom-COL-Z4T3N10-CTLFireability-10 1839434 m, 89336 m/sec, 3196499 t fired, .
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UtilityControlRoom-COL-Z4T3N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-12: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-13: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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31 CTL EXCL 15/210 13/32 UtilityControlRoom-COL-Z4T3N10-CTLFireability-10 2265927 m, 85298 m/sec, 4625667 t fired, .
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lola: FINISHED task # 31 (type EXCL) for UtilityControlRoom-COL-Z4T3N10-CTLFireability-10
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lola: fired transitions : 5621862
lola: time used : 19.000000
lola: memory pages used : 14
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UtilityControlRoom-COL-Z4T3N10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-12: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-13: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
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UtilityControlRoom-COL-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-12: CONJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-13: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
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UtilityControlRoom-COL-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-13: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-COL-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-13: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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25 CTL EXCL 8/355 6/32 UtilityControlRoom-COL-Z4T3N10-CTLFireability-08 1075496 m, 127958 m/sec, 2466783 t fired, .
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UtilityControlRoom-COL-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-13: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-COL-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-13: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-COL-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-13: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-COL-Z4T3N10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-13: EFEG 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z4T3N10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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FINAL RESULTS
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-COL-Z4T3N10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-COL-Z4T3N10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r486-tall-167912702001042"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-COL-Z4T3N10.tgz
mv UtilityControlRoom-COL-Z4T3N10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;