fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r486-tall-167912701900970
Last Updated
May 14, 2023

About the Execution of LoLA for UtilityControlRoom-COL-Z2T3N08

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
5053.915 284818.00 270846.00 901.70 T?FT???TF?F?T?TF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r486-tall-167912701900970.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is UtilityControlRoom-COL-Z2T3N08, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r486-tall-167912701900970
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 536K
-rw-r--r-- 1 mcc users 8.1K Feb 26 14:42 CTLCardinality.txt
-rw-r--r-- 1 mcc users 74K Feb 26 14:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Feb 26 14:40 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 26 14:40 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.4K Feb 25 17:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 17:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Feb 25 17:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 26 14:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 156K Feb 26 14:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 26 14:45 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 90K Feb 26 14:45 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 17:24 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 17:24 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_pt
-rw-r--r-- 1 mcc users 8 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 29K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME UtilityControlRoom-COL-Z2T3N08-CTLFireability-00
FORMULA_NAME UtilityControlRoom-COL-Z2T3N08-CTLFireability-01
FORMULA_NAME UtilityControlRoom-COL-Z2T3N08-CTLFireability-02
FORMULA_NAME UtilityControlRoom-COL-Z2T3N08-CTLFireability-03
FORMULA_NAME UtilityControlRoom-COL-Z2T3N08-CTLFireability-04
FORMULA_NAME UtilityControlRoom-COL-Z2T3N08-CTLFireability-05
FORMULA_NAME UtilityControlRoom-COL-Z2T3N08-CTLFireability-06
FORMULA_NAME UtilityControlRoom-COL-Z2T3N08-CTLFireability-07
FORMULA_NAME UtilityControlRoom-COL-Z2T3N08-CTLFireability-08
FORMULA_NAME UtilityControlRoom-COL-Z2T3N08-CTLFireability-09
FORMULA_NAME UtilityControlRoom-COL-Z2T3N08-CTLFireability-10
FORMULA_NAME UtilityControlRoom-COL-Z2T3N08-CTLFireability-11
FORMULA_NAME UtilityControlRoom-COL-Z2T3N08-CTLFireability-12
FORMULA_NAME UtilityControlRoom-COL-Z2T3N08-CTLFireability-13
FORMULA_NAME UtilityControlRoom-COL-Z2T3N08-CTLFireability-14
FORMULA_NAME UtilityControlRoom-COL-Z2T3N08-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679263913069

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=UtilityControlRoom-COL-Z2T3N08
Not applying reductions.
Model is COL
CTLFireability PT
[2023-03-19 22:11:54] [INFO ] Running its-tools with arguments : [-pnfolder, ., -examination, CTLFireability, --reduce-single, STATESPACE]
[2023-03-19 22:11:54] [INFO ] Parsing pnml file : /home/mcc/execution/./model.pnml
[2023-03-19 22:11:54] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-19 22:11:54] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-19 22:11:55] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 631 ms
[2023-03-19 22:11:55] [INFO ] Imported 13 HL places and 12 HL transitions for a total of 140 PT places and 216.0 transition bindings in 17 ms.
Parsed 16 properties from file ./CTLFireability.xml in 16 ms.
[2023-03-19 22:11:55] [INFO ] Unfolded HLPN to a Petri net with 140 places and 216 transitions 680 arcs in 17 ms.
[2023-03-19 22:11:55] [INFO ] Unfolded 16 HLPN properties in 3 ms.
[2023-03-19 22:11:55] [INFO ] Reduced 8 identical enabling conditions.
[2023-03-19 22:11:55] [INFO ] Reduced 8 identical enabling conditions.
[2023-03-19 22:11:55] [INFO ] Reduced 8 identical enabling conditions.
[2023-03-19 22:11:55] [INFO ] Reduced 8 identical enabling conditions.
[2023-03-19 22:11:55] [INFO ] Reduced 8 identical enabling conditions.
[2023-03-19 22:11:55] [INFO ] Reduced 8 identical enabling conditions.
[2023-03-19 22:11:55] [INFO ] Reduced 8 identical enabling conditions.
Ensure Unique test removed 32 transitions
Reduce isomorphic transitions removed 32 transitions.
Drop transitions removed 16 transitions
Redundant transition composition rules discarded 16 transitions
[2023-03-19 22:11:55] [INFO ] Export to MCC of 16 properties in file ./CTLFireability.STATESPACE.xml took 22 ms.
[2023-03-19 22:11:55] [INFO ] Export to PNML in file ./model.STATESPACE.pnml of net with 140 places, 168 transitions and 488 arcs took 8 ms.
Total runtime 830 ms.
starting LoLA
BK_INPUT UtilityControlRoom-COL-Z2T3N08
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution/unfCTLFireability

FORMULA UtilityControlRoom-COL-Z2T3N08-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N08-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N08-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N08-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N08-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N08-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N08-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N08-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA UtilityControlRoom-COL-Z2T3N08-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679264197887

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/unfCTLFireability/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/unfCTLFireability/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/unfCTLFireability/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:463
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 64 (type EXCL) for 63 UtilityControlRoom-COL-Z2T3N08-CTLFireability-13
lola: time limit : 99 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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sara: try reading problem file /home/mcc/execution/unfCTLFireability/CTLCardinality-79.sara.
sara: place or transition ordering is non-deterministic

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UtilityControlRoom-COL-Z2T3N08-CTLFireability-02: DISJ 0 2 0 0 5 0 0 2
UtilityControlRoom-COL-Z2T3N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-06: DISJ 0 3 0 0 3 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-COL-Z2T3N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 5/179 6/32 UtilityControlRoom-COL-Z2T3N08-CTLFireability-13 1220373 m, 244074 m/sec, 3383278 t fired, .

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UtilityControlRoom-COL-Z2T3N08-CTLFireability-02: DISJ 0 2 0 0 5 0 0 2
UtilityControlRoom-COL-Z2T3N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-COL-Z2T3N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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64 CTL EXCL 10/179 11/32 UtilityControlRoom-COL-Z2T3N08-CTLFireability-13 2255788 m, 207083 m/sec, 6596428 t fired, .

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UtilityControlRoom-COL-Z2T3N08-CTLFireability-02: DISJ 0 2 0 0 5 0 0 2
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UtilityControlRoom-COL-Z2T3N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-06: DISJ 0 3 0 0 3 0 0 0
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UtilityControlRoom-COL-Z2T3N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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64 CTL EXCL 15/179 16/32 UtilityControlRoom-COL-Z2T3N08-CTLFireability-13 3219582 m, 192758 m/sec, 9736948 t fired, .

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UtilityControlRoom-COL-Z2T3N08-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-06: DISJ 0 3 0 0 3 0 0 0
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UtilityControlRoom-COL-Z2T3N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-COL-Z2T3N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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64 CTL EXCL 20/179 20/32 UtilityControlRoom-COL-Z2T3N08-CTLFireability-13 4116802 m, 179444 m/sec, 12751215 t fired, .

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UtilityControlRoom-COL-Z2T3N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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64 CTL EXCL 25/179 24/32 UtilityControlRoom-COL-Z2T3N08-CTLFireability-13 4970760 m, 170791 m/sec, 15694868 t fired, .

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UtilityControlRoom-COL-Z2T3N08-CTLFireability-02: DISJ 0 2 0 0 5 0 0 2
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UtilityControlRoom-COL-Z2T3N08-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-06: DISJ 0 3 0 0 3 0 0 0
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UtilityControlRoom-COL-Z2T3N08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-11: DISJ 0 1 0 0 5 0 0 1
UtilityControlRoom-COL-Z2T3N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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64 CTL EXCL 30/179 28/32 UtilityControlRoom-COL-Z2T3N08-CTLFireability-13 5801261 m, 166100 m/sec, 18610664 t fired, .

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UtilityControlRoom-COL-Z2T3N08-CTLFireability-02: DISJ 0 2 0 0 5 0 0 2
UtilityControlRoom-COL-Z2T3N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-06: DISJ 0 3 0 0 3 0 0 0
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UtilityControlRoom-COL-Z2T3N08-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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64 CTL EXCL 35/179 32/32 UtilityControlRoom-COL-Z2T3N08-CTLFireability-13 6602156 m, 160179 m/sec, 21466461 t fired, .

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UtilityControlRoom-COL-Z2T3N08-CTLFireability-11: DISJ 0 1 0 0 5 0 0 1
UtilityControlRoom-COL-Z2T3N08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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lola: result : false
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UtilityControlRoom-COL-Z2T3N08-CTLFireability-02: DISJ 0 2 0 0 5 0 0 2
UtilityControlRoom-COL-Z2T3N08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
UtilityControlRoom-COL-Z2T3N08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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UtilityControlRoom-COL-Z2T3N08-CTLFireability-03: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N08-CTLFireability-04: CONJ unknown CONJ
UtilityControlRoom-COL-Z2T3N08-CTLFireability-05: CTL unknown AGGR
UtilityControlRoom-COL-Z2T3N08-CTLFireability-06: DISJ unknown DISJ
UtilityControlRoom-COL-Z2T3N08-CTLFireability-07: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N08-CTLFireability-08: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N08-CTLFireability-09: CTL unknown AGGR
UtilityControlRoom-COL-Z2T3N08-CTLFireability-10: CTL false CTL model checker
UtilityControlRoom-COL-Z2T3N08-CTLFireability-11: DISJ unknown DISJ
UtilityControlRoom-COL-Z2T3N08-CTLFireability-12: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N08-CTLFireability-13: CTL unknown AGGR
UtilityControlRoom-COL-Z2T3N08-CTLFireability-14: CTL true CTL model checker
UtilityControlRoom-COL-Z2T3N08-CTLFireability-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="UtilityControlRoom-COL-Z2T3N08"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is UtilityControlRoom-COL-Z2T3N08, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r486-tall-167912701900970"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/UtilityControlRoom-COL-Z2T3N08.tgz
mv UtilityControlRoom-COL-Z2T3N08 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;