About the Execution of LoLA for TwoPhaseLocking-PT-nC05000vN
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
4006.004 | 89466.00 | 83438.00 | 336.10 | TF?TTFF?T??FFT?F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r486-tall-167912701900922.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is TwoPhaseLocking-PT-nC05000vN, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r486-tall-167912701900922
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 464K
-rw-r--r-- 1 mcc users 8.1K Feb 25 17:53 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K Feb 25 17:53 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Feb 25 17:52 CTLFireability.txt
-rw-r--r-- 1 mcc users 42K Feb 25 17:52 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 17:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 17:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 17:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 109K Feb 25 17:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 17:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 93K Feb 25 17:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:24 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:24 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC05000vN-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679257418857
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC05000vN
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC05000vN
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC05000vN-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679257508323
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 13 (type EXCL) for 12 TwoPhaseLocking-PT-nC05000vN-CTLFireability-04
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 13 (type EXCL) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-04
lola: result : true
lola: markings : 4998
lola: fired transitions : 4997
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 TwoPhaseLocking-PT-nC05000vN-CTLFireability-10
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 54 (type FNDP) for 3 TwoPhaseLocking-PT-nC05000vN-CTLFireability-01
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lola: LAUNCH task # 57 (type SRCH) for 3 TwoPhaseLocking-PT-nC05000vN-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 57 (type SRCH) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-01
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 54 (type FNDP) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-01
lola: result : true
lola: fired transitions : 2499
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 55 (type EQUN) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-01 (obsolete)
lola: FINISHED task # 55 (type EQUN) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-01
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/240 19/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-10 4506996 m, 901399 m/sec, 6753608 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: FINISHED task # 50 (type EXCL) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-15
lola: result : false
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lola: fired transitions : 4998
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lola: FINISHED task # 48 (type EXCL) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-15
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: DISJ false DISJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 5/299 9/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-14 2109600 m, 421920 m/sec, 6322982 t fired, .
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: DISJ false DISJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 10/299 18/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-14 4161673 m, 410414 m/sec, 12486320 t fired, .
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: DISJ false DISJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 15/299 26/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-14 6178976 m, 403460 m/sec, 18543995 t fired, .
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: DISJ false DISJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
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lola: FINISHED task # 40 (type EXCL) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-13
lola: result : true
lola: markings : 4998
lola: fired transitions : 4997
lola: time used : 0.000000
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lola: FINISHED task # 37 (type EXCL) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-12
lola: result : false
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lola: fired transitions : 15005
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lola: LAUNCH task # 22 (type EXCL) for 21 TwoPhaseLocking-PT-nC05000vN-CTLFireability-07
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: DISJ false DISJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-05: CTL false CTL model checker
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
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10 CTL EXCL 5/508 15/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-03 3375344 m, 675068 m/sec, 11820736 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 0/591 3/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-02 495248 m, 99049 m/sec, 1161311 t fired, .
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: DISJ false DISJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/591 19/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-02 4411188 m, 783188 m/sec, 10624011 t fired, .
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lola: CANCELED task # 7 (type EXCL) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: DISJ false DISJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC05000vN-CTLFireability-00
lola: time limit : 708 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-00
lola: result : true
lola: markings : 5000
lola: fired transitions : 5000
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 52 (type EXCL) for 24 TwoPhaseLocking-PT-nC05000vN-CTLFireability-08
lola: time limit : 885 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-08
lola: result : false
lola: markings : 5001
lola: fired transitions : 5000
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 TwoPhaseLocking-PT-nC05000vN-CTLFireability-06
lola: time limit : 1180 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-06
lola: result : false
lola: markings : 17504
lola: fired transitions : 32516
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 TwoPhaseLocking-PT-nC05000vN-CTLFireability-09
lola: time limit : 1770 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F true state space / EG
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: DISJ false DISJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vN-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/1770 8/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-09 1898713 m, 379742 m/sec, 8121900 t fired, .
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F true state space / EG
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: DISJ false DISJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vN-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/1770 15/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-09 3633052 m, 346867 m/sec, 15802238 t fired, .
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F true state space / EG
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: DISJ false DISJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vN-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 15/1770 22/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-09 5360654 m, 345520 m/sec, 23404312 t fired, .
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TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F true state space / EG
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: DISJ false DISJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vN-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 20/1770 29/32 TwoPhaseLocking-PT-nC05000vN-CTLFireability-09 7046287 m, 337126 m/sec, 30895287 t fired, .
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lola: CANCELED task # 28 (type EXCL) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F true state space / EG
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: DISJ false DISJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vN-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 34 (type EXCL) for 33 TwoPhaseLocking-PT-nC05000vN-CTLFireability-11
lola: time limit : 3515 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for TwoPhaseLocking-PT-nC05000vN-CTLFireability-11
lola: result : false
lola: markings : 6265010
lola: fired transitions : 9443784
lola: time used : 5.000000
lola: memory pages used : 27
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vN-CTLFireability-00: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-01: AG false findpath
TwoPhaseLocking-PT-nC05000vN-CTLFireability-02: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vN-CTLFireability-03: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-04: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-05: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-07: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vN-CTLFireability-08: F true state space / EG
TwoPhaseLocking-PT-nC05000vN-CTLFireability-09: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vN-CTLFireability-10: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vN-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-12: CTL false CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-13: CTL true CTL model checker
TwoPhaseLocking-PT-nC05000vN-CTLFireability-14: CTL unknown AGGR
TwoPhaseLocking-PT-nC05000vN-CTLFireability-15: DISJ false DISJ
Time elapsed: 90 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC05000vN"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC05000vN, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r486-tall-167912701900922"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC05000vN.tgz
mv TwoPhaseLocking-PT-nC05000vN execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;