fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r486-tall-167912701900916
Last Updated
May 14, 2023

About the Execution of LoLA for TwoPhaseLocking-PT-nC05000vD

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
1360.123 25130.00 22266.00 186.90 FFFT?TTFFFFFTF?? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r486-tall-167912701900916.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is TwoPhaseLocking-PT-nC05000vD, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r486-tall-167912701900916
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 464K
-rw-r--r-- 1 mcc users 7.0K Feb 25 17:56 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Feb 25 17:56 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Feb 25 17:55 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 25 17:55 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 17:24 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 17:24 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 17:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 17:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 17:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 125K Feb 25 17:57 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 17:56 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 88K Feb 25 17:56 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:24 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:24 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-LTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-LTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-LTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-LTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-LTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-LTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-LTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-LTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-LTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-LTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-LTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-LTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-LTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-LTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-LTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC05000vD-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1679257182865

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC05000vD
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC05000vD
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability

FORMULA TwoPhaseLocking-PT-nC05000vD-LTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-LTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-LTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-LTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC05000vD-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679257207995

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:496
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:424
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 19 (type EXCL) for 18 TwoPhaseLocking-PT-nC05000vD-LTLFireability-06
lola: time limit : 116 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 65 (type FNDP) for 24 TwoPhaseLocking-PT-nC05000vD-LTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 66 (type EQUN) for 24 TwoPhaseLocking-PT-nC05000vD-LTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 68 (type SRCH) for 24 TwoPhaseLocking-PT-nC05000vD-LTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 19 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-06
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 TwoPhaseLocking-PT-nC05000vD-LTLFireability-07
lola: time limit : 124 sec
lola: memory limit: 32 pages
lola: FINISHED task # 68 (type SRCH) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-08
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 65 (type FNDP) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-08
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 66 (type EQUN) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-08 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 66 (type EQUN) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-08
lola: result : unknown
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 22 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-07
lola: result : false
lola: markings : 10001
lola: fired transitions : 10001
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 62 (type EXCL) for 61 TwoPhaseLocking-PT-nC05000vD-LTLFireability-15
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: CANCELED task # 62 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-LTLFireability-06: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-07: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-08: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-09: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-15: LTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 5 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 53 (type EXCL) for 52 TwoPhaseLocking-PT-nC05000vD-LTLFireability-12
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: FINISHED task # 53 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-12
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 50 (type EXCL) for 49 TwoPhaseLocking-PT-nC05000vD-LTLFireability-11
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-11
lola: result : false
lola: markings : 10004
lola: fired transitions : 10005
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 42 TwoPhaseLocking-PT-nC05000vD-LTLFireability-10
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-10
lola: result : false
lola: markings : 10001
lola: fired transitions : 10001
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 35 TwoPhaseLocking-PT-nC05000vD-LTLFireability-09
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-09
lola: result : false
lola: markings : 10001
lola: fired transitions : 10001
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 TwoPhaseLocking-PT-nC05000vD-LTLFireability-05
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-05
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 TwoPhaseLocking-PT-nC05000vD-LTLFireability-03
lola: time limit : 513 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-03
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC05000vD-LTLFireability-02
lola: time limit : 599 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-02
lola: result : false
lola: markings : 10001
lola: fired transitions : 10001
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC05000vD-LTLFireability-01
lola: time limit : 719 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-01
lola: result : false
lola: markings : 10001
lola: fired transitions : 10001
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 56 (type EXCL) for 55 TwoPhaseLocking-PT-nC05000vD-LTLFireability-13
lola: time limit : 898 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-13
lola: result : false
lola: markings : 5002
lola: fired transitions : 5002
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 TwoPhaseLocking-PT-nC05000vD-LTLFireability-04
lola: time limit : 1198 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-LTLFireability-01: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-02: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-03: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-05: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-06: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-07: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-08: CONJ false findpath
TwoPhaseLocking-PT-nC05000vD-LTLFireability-09: CONJ false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-10: CONJ false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-11: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-12: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-13: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-15: LTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 LTL EXCL 5/1198 19/32 TwoPhaseLocking-PT-nC05000vD-LTLFireability-04 2809350 m, 561870 m/sec, 11073659 t fired, .

Time elapsed: 10 secs. Pages in use: 32
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lola: CANCELED task # 13 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-LTLFireability-01: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-02: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-03: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-05: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-06: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-07: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-08: CONJ false findpath
TwoPhaseLocking-PT-nC05000vD-LTLFireability-09: CONJ false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-10: CONJ false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-11: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-12: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-13: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-15: LTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 15 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC05000vD-LTLFireability-00
lola: time limit : 1792 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-00
lola: result : false
lola: markings : 20001
lola: fired transitions : 25001
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 59 (type EXCL) for 58 TwoPhaseLocking-PT-nC05000vD-LTLFireability-14
lola: time limit : 3585 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-LTLFireability-00: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-01: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-02: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-03: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-05: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-06: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-07: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-08: CONJ false findpath
TwoPhaseLocking-PT-nC05000vD-LTLFireability-09: CONJ false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-10: CONJ false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-11: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-12: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-13: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-15: LTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
59 LTL EXCL 5/3585 19/32 TwoPhaseLocking-PT-nC05000vD-LTLFireability-14 2865444 m, 573088 m/sec, 8576546 t fired, .

Time elapsed: 20 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 59 (type EXCL) for TwoPhaseLocking-PT-nC05000vD-LTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-LTLFireability-00: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-01: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-02: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-03: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-05: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-06: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-07: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-08: CONJ false findpath
TwoPhaseLocking-PT-nC05000vD-LTLFireability-09: CONJ false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-10: CONJ false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-11: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-12: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-13: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC05000vD-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC05000vD-LTLFireability-15: LTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC05000vD-LTLFireability-00: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-01: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-02: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-03: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-04: LTL unknown AGGR
TwoPhaseLocking-PT-nC05000vD-LTLFireability-05: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-06: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-07: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-08: CONJ false findpath
TwoPhaseLocking-PT-nC05000vD-LTLFireability-09: CONJ false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-10: CONJ false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-11: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-12: LTL true LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-13: LTL false LTL model checker
TwoPhaseLocking-PT-nC05000vD-LTLFireability-14: LTL unknown AGGR
TwoPhaseLocking-PT-nC05000vD-LTLFireability-15: LTL unknown AGGR


Time elapsed: 25 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC05000vD"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC05000vD, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r486-tall-167912701900916"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC05000vD.tgz
mv TwoPhaseLocking-PT-nC05000vD execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;