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Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r486-tall-167912701900906
Last Updated
May 14, 2023

About the Execution of LoLA for TwoPhaseLocking-PT-nC02000vN

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
2909.976 70246.00 55988.00 260.70 ??FF?T?TF?TTTTTT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r486-tall-167912701900906.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is TwoPhaseLocking-PT-nC02000vN, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r486-tall-167912701900906
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 460K
-rw-r--r-- 1 mcc users 6.9K Feb 25 17:56 CTLCardinality.txt
-rw-r--r-- 1 mcc users 64K Feb 25 17:56 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K Feb 25 17:55 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K Feb 25 17:55 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 17:23 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:23 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 17:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 17:24 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 17:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 129K Feb 25 17:57 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 17:57 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 88K Feb 25 17:57 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:24 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:24 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 4.6K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC02000vN-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679256913778

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=TwoPhaseLocking-PT-nC02000vN
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC02000vN
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC02000vN-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679256984024

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 10 (type EXCL) for 9 TwoPhaseLocking-PT-nC02000vN-CTLFireability-03
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:754
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 10 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-03
lola: result : false
lola: markings : 4006
lola: fired transitions : 8015
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 57 (type EXCL) for 37 TwoPhaseLocking-PT-nC02000vN-CTLFireability-11
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 57 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-11
lola: result : false
lola: markings : 2000
lola: fired transitions : 1999
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 51 (type EXCL) for 50 TwoPhaseLocking-PT-nC02000vN-CTLFireability-14
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 59 (type FNDP) for 24 TwoPhaseLocking-PT-nC02000vN-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type EQUN) for 24 TwoPhaseLocking-PT-nC02000vN-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type SRCH) for 24 TwoPhaseLocking-PT-nC02000vN-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 62 (type SRCH) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-08
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 51 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-14
lola: result : true
lola: markings : 2002
lola: fired transitions : 2005
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 43 TwoPhaseLocking-PT-nC02000vN-CTLFireability-13
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: FINISHED task # 59 (type FNDP) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-08
lola: result : true
lola: fired transitions : 999
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 60 (type EQUN) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-08 (obsolete)
lola: FINISHED task # 48 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-13
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 TwoPhaseLocking-PT-nC02000vN-CTLFireability-12
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type EQUN) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-08
lola: result : unknown
lola: FINISHED task # 41 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-12
lola: result : true
lola: markings : 504511
lola: fired transitions : 507510
lola: time used : 1.000000
lola: memory pages used : 3
lola: LAUNCH task # 35 (type EXCL) for 30 TwoPhaseLocking-PT-nC02000vN-CTLFireability-10
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-10
lola: result : true
lola: markings : 6004
lola: fired transitions : 6005
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 TwoPhaseLocking-PT-nC02000vN-CTLFireability-07
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-07
lola: result : true
lola: markings : 4004
lola: fired transitions : 8008
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 TwoPhaseLocking-PT-nC02000vN-CTLFireability-06
lola: time limit : 359 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vN-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-08: AG false findpath
TwoPhaseLocking-PT-nC02000vN-CTLFireability-11: AXAF true state space /EXEG
TwoPhaseLocking-PT-nC02000vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-14: CTL true CTL model checker

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TwoPhaseLocking-PT-nC02000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-10: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 4/359 14/32 TwoPhaseLocking-PT-nC02000vN-CTLFireability-06 3419018 m, 683803 m/sec, 7258175 t fired, .

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TwoPhaseLocking-PT-nC02000vN-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-08: AG false findpath
TwoPhaseLocking-PT-nC02000vN-CTLFireability-11: AXAF true state space /EXEG
TwoPhaseLocking-PT-nC02000vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC02000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-10: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 9/359 27/32 TwoPhaseLocking-PT-nC02000vN-CTLFireability-06 6460115 m, 608219 m/sec, 13661394 t fired, .

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lola: CANCELED task # 19 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vN-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-08: AG false findpath
TwoPhaseLocking-PT-nC02000vN-CTLFireability-11: AXAF true state space /EXEG
TwoPhaseLocking-PT-nC02000vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-14: CTL true CTL model checker

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TwoPhaseLocking-PT-nC02000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-10: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 13 (type EXCL) for 12 TwoPhaseLocking-PT-nC02000vN-CTLFireability-04
lola: time limit : 398 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vN-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-08: AG false findpath
TwoPhaseLocking-PT-nC02000vN-CTLFireability-11: AXAF true state space /EXEG
TwoPhaseLocking-PT-nC02000vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC02000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-10: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/398 23/32 TwoPhaseLocking-PT-nC02000vN-CTLFireability-04 5612633 m, 1122526 m/sec, 10471977 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vN-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-08: AG false findpath
TwoPhaseLocking-PT-nC02000vN-CTLFireability-11: AXAF true state space /EXEG
TwoPhaseLocking-PT-nC02000vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-14: CTL true CTL model checker

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TwoPhaseLocking-PT-nC02000vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-10: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC02000vN-CTLFireability-02
lola: time limit : 446 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-02
lola: result : false
lola: markings : 1002000
lola: fired transitions : 1501501
lola: time used : 1.000000
lola: memory pages used : 5
lola: LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC02000vN-CTLFireability-01
lola: time limit : 510 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-08: AG false findpath
TwoPhaseLocking-PT-nC02000vN-CTLFireability-11: AXAF true state space /EXEG
TwoPhaseLocking-PT-nC02000vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-14: CTL true CTL model checker

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TwoPhaseLocking-PT-nC02000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-10: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 4/510 17/32 TwoPhaseLocking-PT-nC02000vN-CTLFireability-01 4014766 m, 802953 m/sec, 8958661 t fired, .

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TwoPhaseLocking-PT-nC02000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-08: AG false findpath
TwoPhaseLocking-PT-nC02000vN-CTLFireability-11: AXAF true state space /EXEG
TwoPhaseLocking-PT-nC02000vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-14: CTL true CTL model checker

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TwoPhaseLocking-PT-nC02000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-10: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 9/510 32/32 TwoPhaseLocking-PT-nC02000vN-CTLFireability-01 7622855 m, 721617 m/sec, 17451527 t fired, .

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TwoPhaseLocking-PT-nC02000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-08: AG false findpath
TwoPhaseLocking-PT-nC02000vN-CTLFireability-11: AXAF true state space /EXEG
TwoPhaseLocking-PT-nC02000vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-14: CTL true CTL model checker

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TwoPhaseLocking-PT-nC02000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
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TwoPhaseLocking-PT-nC02000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-10: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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lola: time limit : 593 sec
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TwoPhaseLocking-PT-nC02000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-08: AG false findpath
TwoPhaseLocking-PT-nC02000vN-CTLFireability-11: AXAF true state space /EXEG
TwoPhaseLocking-PT-nC02000vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-14: CTL true CTL model checker

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TwoPhaseLocking-PT-nC02000vN-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
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TwoPhaseLocking-PT-nC02000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
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TwoPhaseLocking-PT-nC02000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-10: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/593 27/32 TwoPhaseLocking-PT-nC02000vN-CTLFireability-00 6323724 m, 1264744 m/sec, 9133309 t fired, .

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TwoPhaseLocking-PT-nC02000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-08: AG false findpath
TwoPhaseLocking-PT-nC02000vN-CTLFireability-11: AXAF true state space /EXEG
TwoPhaseLocking-PT-nC02000vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-14: CTL true CTL model checker

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TwoPhaseLocking-PT-nC02000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-10: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-13: CONJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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lola: FINISHED task # 56 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-10
lola: result : false
lola: markings : 2001
lola: fired transitions : 2000
lola: time used : 0.000000
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lola: FINISHED task # 46 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-13
lola: result : true
lola: markings : 1003004
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TwoPhaseLocking-PT-nC02000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-08: AG false findpath
TwoPhaseLocking-PT-nC02000vN-CTLFireability-10: CONJ true CONJ
TwoPhaseLocking-PT-nC02000vN-CTLFireability-11: AXAF true state space /EXEG
TwoPhaseLocking-PT-nC02000vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-13: CONJ true CONJ
TwoPhaseLocking-PT-nC02000vN-CTLFireability-14: CTL true CTL model checker

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TwoPhaseLocking-PT-nC02000vN-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 4/1183 8/32 TwoPhaseLocking-PT-nC02000vN-CTLFireability-09 1855572 m, 371114 m/sec, 6336234 t fired, .

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# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-08: AG false findpath
TwoPhaseLocking-PT-nC02000vN-CTLFireability-10: CONJ true CONJ
TwoPhaseLocking-PT-nC02000vN-CTLFireability-11: AXAF true state space /EXEG
TwoPhaseLocking-PT-nC02000vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-13: CONJ true CONJ
TwoPhaseLocking-PT-nC02000vN-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 9/1183 17/32 TwoPhaseLocking-PT-nC02000vN-CTLFireability-09 3901488 m, 409183 m/sec, 13259815 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-08: AG false findpath
TwoPhaseLocking-PT-nC02000vN-CTLFireability-10: CONJ true CONJ
TwoPhaseLocking-PT-nC02000vN-CTLFireability-11: AXAF true state space /EXEG
TwoPhaseLocking-PT-nC02000vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-13: CONJ true CONJ
TwoPhaseLocking-PT-nC02000vN-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 14/1183 26/32 TwoPhaseLocking-PT-nC02000vN-CTLFireability-09 6148157 m, 449333 m/sec, 20856469 t fired, .

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# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 28 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-08: AG false findpath
TwoPhaseLocking-PT-nC02000vN-CTLFireability-10: CONJ true CONJ
TwoPhaseLocking-PT-nC02000vN-CTLFireability-11: AXAF true state space /EXEG
TwoPhaseLocking-PT-nC02000vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-13: CONJ true CONJ
TwoPhaseLocking-PT-nC02000vN-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vN-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 16 (type EXCL) for 15 TwoPhaseLocking-PT-nC02000vN-CTLFireability-05
lola: time limit : 1765 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-05
lola: result : true
lola: markings : 6012
lola: fired transitions : 18048
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 53 TwoPhaseLocking-PT-nC02000vN-CTLFireability-15
lola: time limit : 3530 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for TwoPhaseLocking-PT-nC02000vN-CTLFireability-15
lola: result : true
lola: markings : 8007
lola: fired transitions : 16008
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vN-CTLFireability-00: CTL unknown AGGR
TwoPhaseLocking-PT-nC02000vN-CTLFireability-01: CTL unknown AGGR
TwoPhaseLocking-PT-nC02000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-03: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-04: CTL unknown AGGR
TwoPhaseLocking-PT-nC02000vN-CTLFireability-05: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-06: CTL unknown AGGR
TwoPhaseLocking-PT-nC02000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-08: AG false findpath
TwoPhaseLocking-PT-nC02000vN-CTLFireability-09: CTL unknown AGGR
TwoPhaseLocking-PT-nC02000vN-CTLFireability-10: CONJ true CONJ
TwoPhaseLocking-PT-nC02000vN-CTLFireability-11: AXAF true state space /EXEG
TwoPhaseLocking-PT-nC02000vN-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-13: CONJ true CONJ
TwoPhaseLocking-PT-nC02000vN-CTLFireability-14: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vN-CTLFireability-15: CTL true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC02000vN"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC02000vN, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r486-tall-167912701900906"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC02000vN.tgz
mv TwoPhaseLocking-PT-nC02000vN execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;