fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r486-tall-167912701300482
Last Updated
May 14, 2023

About the Execution of LoLA for Szymanski-PT-b10

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
6701.176 3600000.00 6967144.00 7993.50 T??FT?T?FFF?TFTF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r486-tall-167912701300482.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is Szymanski-PT-b10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r486-tall-167912701300482
=====================================================================


--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.0M
-rw-r--r-- 1 mcc users 6.9K Feb 26 17:01 CTLCardinality.txt
-rw-r--r-- 1 mcc users 75K Feb 26 17:01 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.1K Feb 26 16:59 CTLFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 26 16:59 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 17:19 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 17:19 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 17:19 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 17:19 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.2K Feb 26 17:04 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 83K Feb 26 17:04 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.2K Feb 26 17:02 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 68K Feb 26 17:02 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 17:19 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 17:19 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 3.7M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Szymanski-PT-b10-CTLFireability-00
FORMULA_NAME Szymanski-PT-b10-CTLFireability-01
FORMULA_NAME Szymanski-PT-b10-CTLFireability-02
FORMULA_NAME Szymanski-PT-b10-CTLFireability-03
FORMULA_NAME Szymanski-PT-b10-CTLFireability-04
FORMULA_NAME Szymanski-PT-b10-CTLFireability-05
FORMULA_NAME Szymanski-PT-b10-CTLFireability-06
FORMULA_NAME Szymanski-PT-b10-CTLFireability-07
FORMULA_NAME Szymanski-PT-b10-CTLFireability-08
FORMULA_NAME Szymanski-PT-b10-CTLFireability-09
FORMULA_NAME Szymanski-PT-b10-CTLFireability-10
FORMULA_NAME Szymanski-PT-b10-CTLFireability-11
FORMULA_NAME Szymanski-PT-b10-CTLFireability-12
FORMULA_NAME Szymanski-PT-b10-CTLFireability-13
FORMULA_NAME Szymanski-PT-b10-CTLFireability-14
FORMULA_NAME Szymanski-PT-b10-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679223711139

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Szymanski-PT-b10
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT Szymanski-PT-b10
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA Szymanski-PT-b10-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Szymanski-PT-b10-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Szymanski-PT-b10-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Szymanski-PT-b10-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Szymanski-PT-b10-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Szymanski-PT-b10-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Szymanski-PT-b10-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Szymanski-PT-b10-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Szymanski-PT-b10-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Szymanski-PT-b10-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Szymanski-PT-b10-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393232 kB
MemFree: 9507116 kB
After kill :
MemTotal: 16393232 kB
MemFree: 16161692 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:182
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:122
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 256 transitions removed,260 places removed
lola: Created skeleton in 0.000000 secs.
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lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 15 (type CNST) for 6 Szymanski-PT-b10-CTLFireability-02
lola: time limit : 0 sec
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lola: LAUNCH INITIAL
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lola: FINISHED task # 15 (type CNST) for Szymanski-PT-b10-CTLFireability-02
lola: result : true
lola: FINISHED task # 70 (type CNST) for Szymanski-PT-b10-CTLFireability-15
lola: result : false
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b10-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b10-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-02: DISJ 0 0 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
Szymanski-PT-b10-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
Szymanski-PT-b10-CTLFireability-07: EU 0 0 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-10: CONJ 0 0 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
Szymanski-PT-b10-CTLFireability-12: EFAG 0 0 0 0 0 0 0 0
Szymanski-PT-b10-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
Szymanski-PT-b10-CTLFireability-14: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 1 (type EXCL) for 0 Szymanski-PT-b10-CTLFireability-00
lola: time limit : 128 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for Szymanski-PT-b10-CTLFireability-00
lola: result : true
lola: markings : 33
lola: fired transitions : 34
lola: time used : 1.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b10-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b10-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-02: DISJ 0 0 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
Szymanski-PT-b10-CTLFireability-07: EU 0 0 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-10: CONJ 0 0 0 0 3 0 0 0
Szymanski-PT-b10-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
Szymanski-PT-b10-CTLFireability-12: EFAG 0 0 0 0 0 0 0 0
Szymanski-PT-b10-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
Szymanski-PT-b10-CTLFireability-14: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 15 secs. Pages in use: 1
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lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 18 (type EXCL) for 17 Szymanski-PT-b10-CTLFireability-03
lola: time limit : 155 sec
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lola: FINISHED task # 18 (type EXCL) for Szymanski-PT-b10-CTLFireability-03
lola: result : false
lola: markings : 33
lola: fired transitions : 99
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 27 (type EXCL) for 26 Szymanski-PT-b10-CTLFireability-06
lola: time limit : 170 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 27 (type EXCL) for Szymanski-PT-b10-CTLFireability-06
lola: result : true
lola: markings : 33
lola: fired transitions : 33
lola: time used : 0.000000
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lola: LAUNCH task # 21 (type EXCL) for 20 Szymanski-PT-b10-CTLFireability-04
lola: time limit : 179 sec
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lola: FINISHED task # 21 (type EXCL) for Szymanski-PT-b10-CTLFireability-04
lola: result : true
lola: markings : 33
lola: fired transitions : 33
lola: time used : 0.000000
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lola: LAUNCH task # 9 (type EXCL) for 6 Szymanski-PT-b10-CTLFireability-02
lola: time limit : 188 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:738
lola: rewrite Frontend/Parser/formula_rewrite.k:694
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 78 (type FNDP) for 38 Szymanski-PT-b10-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 79 (type EQUN) for 38 Szymanski-PT-b10-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type SRCH) for 38 Szymanski-PT-b10-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 78 (type FNDP) for Szymanski-PT-b10-CTLFireability-10
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 79 (type EQUN) for Szymanski-PT-b10-CTLFireability-10 (obsolete)
lola: CANCELED task # 81 (type SRCH) for Szymanski-PT-b10-CTLFireability-10 (obsolete)
lola: LAUNCH task # 73 (type FNDP) for 38 Szymanski-PT-b10-CTLFireability-10
lola: time limit : 32000000 sec
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lola: LAUNCH task # 74 (type EQUN) for 38 Szymanski-PT-b10-CTLFireability-10
lola: time limit : 32000000 sec
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lola: LAUNCH task # 82 (type FNDP) for 38 Szymanski-PT-b10-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 81 (type SRCH) for Szymanski-PT-b10-CTLFireability-10
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 82 (type FNDP) for Szymanski-PT-b10-CTLFireability-10
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 86 (type SRCH) for 38 Szymanski-PT-b10-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/CTLFireability-74.sara.
sara: try reading problem file /home/mcc/execution/CTLFireability-79.sara.
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b10-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b10-CTLFireability-04: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Szymanski-PT-b10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-02: DISJ 0 1 1 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-07: EU 0 1 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-10: CONJ 0 3 3 0 7 0 0 5
Szymanski-PT-b10-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-12: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 3/223 1/32 Szymanski-PT-b10-CTLFireability-02 97384 m, 19476 m/sec, 285686 t fired, .
73 EF FNDP 2/3582 0/5 Szymanski-PT-b10-CTLFireability-10 740 t fired, 3 attempts, .
74 EF STEQ 2/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
86 EF SRCH 2/3582 1/5 Szymanski-PT-b10-CTLFireability-10 696 m, 139 m/sec, 1223 t fired, .

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lola: FINISHED task # 86 (type SRCH) for Szymanski-PT-b10-CTLFireability-10
lola: result : unknown
lola: markings : 721
lola: fired transitions : 1263
lola: time used : 2.000000
lola: memory pages used : 1
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 79 (type EQUN) for Szymanski-PT-b10-CTLFireability-10
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Szymanski-PT-b10-CTLFireability-00: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-03: CTL false CTL model checker
Szymanski-PT-b10-CTLFireability-04: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-15: INITIAL false preprocessing

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Szymanski-PT-b10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-07: EU 0 1 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-10: CONJ 0 3 2 0 10 0 0 4
Szymanski-PT-b10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-12: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 8/255 3/32 Szymanski-PT-b10-CTLFireability-02 391136 m, 58750 m/sec, 1282285 t fired, .
73 EF FNDP 7/3582 0/5 Szymanski-PT-b10-CTLFireability-10 6324 t fired, 16 attempts, .
74 EF STEQ 7/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.

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Szymanski-PT-b10-CTLFireability-12: EFAG 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 13/255 5/32 Szymanski-PT-b10-CTLFireability-02 658715 m, 53515 m/sec, 2554670 t fired, .
73 EF FNDP 12/3582 0/5 Szymanski-PT-b10-CTLFireability-10 12082 t fired, 33 attempts, .
74 EF STEQ 12/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.

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Szymanski-PT-b10-CTLFireability-04: CTL true CTL model checker
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 18/255 7/32 Szymanski-PT-b10-CTLFireability-02 957157 m, 59688 m/sec, 3709949 t fired, .
73 EF FNDP 17/3582 0/5 Szymanski-PT-b10-CTLFireability-10 17949 t fired, 47 attempts, .
74 EF STEQ 17/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 23/255 9/32 Szymanski-PT-b10-CTLFireability-02 1268876 m, 62343 m/sec, 4811450 t fired, .
73 EF FNDP 22/3582 0/5 Szymanski-PT-b10-CTLFireability-10 24065 t fired, 57 attempts, .
74 EF STEQ 22/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 28/255 10/32 Szymanski-PT-b10-CTLFireability-02 1523577 m, 50940 m/sec, 6102054 t fired, .
73 EF FNDP 27/3582 0/5 Szymanski-PT-b10-CTLFireability-10 30050 t fired, 68 attempts, .
74 EF STEQ 27/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.

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Szymanski-PT-b10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-10: CONJ 0 3 2 0 10 0 0 4
Szymanski-PT-b10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-12: EFAG 0 1 0 0 1 0 0 0
Szymanski-PT-b10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 33/255 11/32 Szymanski-PT-b10-CTLFireability-02 1719375 m, 39159 m/sec, 7568729 t fired, .
73 EF FNDP 32/3582 0/5 Szymanski-PT-b10-CTLFireability-10 36244 t fired, 76 attempts, .
74 EF STEQ 32/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.

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Szymanski-PT-b10-CTLFireability-06: CTL true CTL model checker
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 38/255 12/32 Szymanski-PT-b10-CTLFireability-02 1912418 m, 38608 m/sec, 9052730 t fired, .
73 EF FNDP 37/3582 0/5 Szymanski-PT-b10-CTLFireability-10 42236 t fired, 89 attempts, .
74 EF STEQ 37/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.

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9 CTL EXCL 43/255 13/32 Szymanski-PT-b10-CTLFireability-02 2103100 m, 38136 m/sec, 10529756 t fired, .
73 EF FNDP 42/3582 0/5 Szymanski-PT-b10-CTLFireability-10 48249 t fired, 99 attempts, .
74 EF STEQ 42/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.

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9 CTL EXCL 48/255 15/32 Szymanski-PT-b10-CTLFireability-02 2401980 m, 59776 m/sec, 11686121 t fired, .
73 EF FNDP 47/3582 0/5 Szymanski-PT-b10-CTLFireability-10 54148 t fired, 112 attempts, .
74 EF STEQ 47/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 CTL EXCL 53/255 17/32 Szymanski-PT-b10-CTLFireability-02 2666538 m, 52911 m/sec, 12935045 t fired, .
73 EF FNDP 52/3582 0/5 Szymanski-PT-b10-CTLFireability-10 60152 t fired, 123 attempts, .
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9 CTL EXCL 58/255 18/32 Szymanski-PT-b10-CTLFireability-02 2844985 m, 35689 m/sec, 14454127 t fired, .
73 EF FNDP 57/3582 0/5 Szymanski-PT-b10-CTLFireability-10 66355 t fired, 130 attempts, .
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9 CTL EXCL 63/255 19/32 Szymanski-PT-b10-CTLFireability-02 3086890 m, 48381 m/sec, 15753381 t fired, .
73 EF FNDP 62/3582 0/5 Szymanski-PT-b10-CTLFireability-10 72189 t fired, 145 attempts, .
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9 CTL EXCL 68/255 21/32 Szymanski-PT-b10-CTLFireability-02 3265616 m, 35745 m/sec, 17265566 t fired, .
73 EF FNDP 67/3582 0/5 Szymanski-PT-b10-CTLFireability-10 78322 t fired, 153 attempts, .
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9 CTL EXCL 73/255 22/32 Szymanski-PT-b10-CTLFireability-02 3541946 m, 55266 m/sec, 18487101 t fired, .
73 EF FNDP 72/3582 0/5 Szymanski-PT-b10-CTLFireability-10 84345 t fired, 163 attempts, .
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9 CTL EXCL 78/255 24/32 Szymanski-PT-b10-CTLFireability-02 3818200 m, 55250 m/sec, 19687281 t fired, .
73 EF FNDP 77/3582 0/5 Szymanski-PT-b10-CTLFireability-10 90382 t fired, 174 attempts, .
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9 CTL EXCL 83/255 26/32 Szymanski-PT-b10-CTLFireability-02 4079771 m, 52314 m/sec, 20937451 t fired, .
73 EF FNDP 82/3582 0/5 Szymanski-PT-b10-CTLFireability-10 96337 t fired, 187 attempts, .
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9 CTL EXCL 88/255 27/32 Szymanski-PT-b10-CTLFireability-02 4286273 m, 41300 m/sec, 22374310 t fired, .
73 EF FNDP 87/3582 0/5 Szymanski-PT-b10-CTLFireability-10 102711 t fired, 190 attempts, .
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9 CTL EXCL 93/255 28/32 Szymanski-PT-b10-CTLFireability-02 4548010 m, 52347 m/sec, 23638949 t fired, .
73 EF FNDP 92/3582 0/5 Szymanski-PT-b10-CTLFireability-10 108760 t fired, 200 attempts, .
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9 CTL EXCL 98/255 30/32 Szymanski-PT-b10-CTLFireability-02 4801613 m, 50720 m/sec, 24915012 t fired, .
73 EF FNDP 97/3582 0/5 Szymanski-PT-b10-CTLFireability-10 114854 t fired, 209 attempts, .
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9 CTL EXCL 103/255 32/32 Szymanski-PT-b10-CTLFireability-02 5136398 m, 66957 m/sec, 25946211 t fired, .
73 EF FNDP 102/3582 0/5 Szymanski-PT-b10-CTLFireability-10 121007 t fired, 216 attempts, .
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73 EF FNDP 107/3582 0/5 Szymanski-PT-b10-CTLFireability-10 126990 t fired, 227 attempts, .
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58 CTL EXCL 5/289 2/32 Szymanski-PT-b10-CTLFireability-11 251942 m, 50388 m/sec, 1286137 t fired, .
73 EF FNDP 112/3582 0/5 Szymanski-PT-b10-CTLFireability-10 132841 t fired, 236 attempts, .
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58 CTL EXCL 10/289 3/32 Szymanski-PT-b10-CTLFireability-11 466922 m, 42996 m/sec, 2696237 t fired, .
73 EF FNDP 117/3582 0/5 Szymanski-PT-b10-CTLFireability-10 138834 t fired, 242 attempts, .
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58 CTL EXCL 15/289 5/32 Szymanski-PT-b10-CTLFireability-11 684430 m, 43501 m/sec, 4121345 t fired, .
73 EF FNDP 122/3582 0/5 Szymanski-PT-b10-CTLFireability-10 144653 t fired, 252 attempts, .
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58 CTL EXCL 20/289 6/32 Szymanski-PT-b10-CTLFireability-11 927562 m, 48626 m/sec, 5447669 t fired, .
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58 CTL EXCL 25/289 8/32 Szymanski-PT-b10-CTLFireability-11 1168850 m, 48257 m/sec, 6844302 t fired, .
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58 CTL EXCL 35/289 10/32 Szymanski-PT-b10-CTLFireability-11 1591050 m, 34375 m/sec, 9800960 t fired, .
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58 CTL EXCL 90/289 23/32 Szymanski-PT-b10-CTLFireability-11 3716342 m, 43273 m/sec, 26592050 t fired, .
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73 EF FNDP 317/3582 0/5 Szymanski-PT-b10-CTLFireability-10 379237 t fired, 565 attempts, .
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24 CTL EXCL 90/371 18/32 Szymanski-PT-b10-CTLFireability-05 2756294 m, 21972 m/sec, 19208222 t fired, .
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24 CTL EXCL 135/371 26/32 Szymanski-PT-b10-CTLFireability-05 4116061 m, 35333 m/sec, 29254721 t fired, .
73 EF FNDP 372/3582 0/5 Szymanski-PT-b10-CTLFireability-10 445355 t fired, 641 attempts, .
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24 CTL EXCL 140/371 26/32 Szymanski-PT-b10-CTLFireability-05 4232693 m, 23326 m/sec, 30423042 t fired, .
73 EF FNDP 377/3582 0/5 Szymanski-PT-b10-CTLFireability-10 451455 t fired, 647 attempts, .
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24 CTL EXCL 145/371 27/32 Szymanski-PT-b10-CTLFireability-05 4370134 m, 27488 m/sec, 31489806 t fired, .
73 EF FNDP 382/3582 0/5 Szymanski-PT-b10-CTLFireability-10 457604 t fired, 651 attempts, .
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73 EF FNDP 387/3582 0/5 Szymanski-PT-b10-CTLFireability-10 463695 t fired, 657 attempts, .
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24 CTL EXCL 155/371 29/32 Szymanski-PT-b10-CTLFireability-05 4689262 m, 30759 m/sec, 33805939 t fired, .
73 EF FNDP 392/3582 0/5 Szymanski-PT-b10-CTLFireability-10 469693 t fired, 665 attempts, .
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73 EF FNDP 402/3582 0/5 Szymanski-PT-b10-CTLFireability-10 481766 t fired, 680 attempts, .
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4 CTL EXCL 10/453 2/32 Szymanski-PT-b10-CTLFireability-01 237638 m, 20221 m/sec, 1032998 t fired, .
73 EF FNDP 417/3582 0/5 Szymanski-PT-b10-CTLFireability-10 500019 t fired, 700 attempts, .
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73 EF FNDP 427/3582 0/5 Szymanski-PT-b10-CTLFireability-10 512263 t fired, 711 attempts, .
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4 CTL EXCL 90/453 12/32 Szymanski-PT-b10-CTLFireability-01 1766767 m, 21546 m/sec, 10255733 t fired, .
73 EF FNDP 497/3582 0/5 Szymanski-PT-b10-CTLFireability-10 597187 t fired, 804 attempts, .
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73 EF FNDP 682/3582 0/5 Szymanski-PT-b10-CTLFireability-10 820229 t fired, 1052 attempts, .
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73 EF FNDP 692/3582 0/5 Szymanski-PT-b10-CTLFireability-10 832075 t fired, 1064 attempts, .
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73 EF FNDP 697/3582 0/5 Szymanski-PT-b10-CTLFireability-10 838099 t fired, 1067 attempts, .
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73 EF FNDP 742/3582 0/5 Szymanski-PT-b10-CTLFireability-10 892612 t fired, 1112 attempts, .
74 EF STEQ 742/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 10/475 1/32 Szymanski-PT-b10-CTLFireability-10 10627 m, 1030 m/sec, 38166 t fired, .

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73 EF FNDP 747/3582 0/5 Szymanski-PT-b10-CTLFireability-10 898680 t fired, 1117 attempts, .
74 EF STEQ 747/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 15/475 1/32 Szymanski-PT-b10-CTLFireability-10 16377 m, 1150 m/sec, 55709 t fired, .

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73 EF FNDP 752/3582 0/5 Szymanski-PT-b10-CTLFireability-10 904743 t fired, 1122 attempts, .
74 EF STEQ 752/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 20/475 1/32 Szymanski-PT-b10-CTLFireability-10 21964 m, 1117 m/sec, 72715 t fired, .

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73 EF FNDP 757/3582 0/5 Szymanski-PT-b10-CTLFireability-10 910802 t fired, 1129 attempts, .
74 EF STEQ 757/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 25/475 1/32 Szymanski-PT-b10-CTLFireability-10 27517 m, 1110 m/sec, 93266 t fired, .

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73 EF FNDP 762/3582 0/5 Szymanski-PT-b10-CTLFireability-10 916871 t fired, 1134 attempts, .
74 EF STEQ 762/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 30/475 1/32 Szymanski-PT-b10-CTLFireability-10 32785 m, 1053 m/sec, 115690 t fired, .

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74 EF STEQ 767/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 35/475 1/32 Szymanski-PT-b10-CTLFireability-10 37732 m, 989 m/sec, 149918 t fired, .

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74 EF STEQ 772/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 40/475 1/32 Szymanski-PT-b10-CTLFireability-10 43510 m, 1155 m/sec, 166756 t fired, .

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74 EF STEQ 777/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 45/475 1/32 Szymanski-PT-b10-CTLFireability-10 49289 m, 1155 m/sec, 187339 t fired, .

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76 EF EXCL 50/475 1/32 Szymanski-PT-b10-CTLFireability-10 55065 m, 1155 m/sec, 207157 t fired, .

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76 EF EXCL 55/475 1/32 Szymanski-PT-b10-CTLFireability-10 60706 m, 1128 m/sec, 224547 t fired, .

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73 EF FNDP 807/3582 0/5 Szymanski-PT-b10-CTLFireability-10 971221 t fired, 1180 attempts, .
74 EF STEQ 807/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 75/475 1/32 Szymanski-PT-b10-CTLFireability-10 82218 m, 978 m/sec, 320937 t fired, .

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73 EF FNDP 812/3582 0/5 Szymanski-PT-b10-CTLFireability-10 977192 t fired, 1185 attempts, .
74 EF STEQ 812/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 80/475 1/32 Szymanski-PT-b10-CTLFireability-10 87152 m, 986 m/sec, 357201 t fired, .

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73 EF FNDP 817/3582 0/5 Szymanski-PT-b10-CTLFireability-10 983283 t fired, 1190 attempts, .
74 EF STEQ 817/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 85/475 1/32 Szymanski-PT-b10-CTLFireability-10 92940 m, 1157 m/sec, 374842 t fired, .

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73 EF FNDP 822/3582 0/5 Szymanski-PT-b10-CTLFireability-10 989241 t fired, 1194 attempts, .
74 EF STEQ 822/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 90/475 1/32 Szymanski-PT-b10-CTLFireability-10 98721 m, 1156 m/sec, 395142 t fired, .

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73 EF FNDP 827/3582 0/5 Szymanski-PT-b10-CTLFireability-10 995322 t fired, 1198 attempts, .
74 EF STEQ 827/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 95/475 1/32 Szymanski-PT-b10-CTLFireability-10 104506 m, 1157 m/sec, 415576 t fired, .

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73 EF FNDP 832/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1001431 t fired, 1202 attempts, .
74 EF STEQ 832/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 100/475 1/32 Szymanski-PT-b10-CTLFireability-10 110292 m, 1157 m/sec, 436331 t fired, .

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73 EF FNDP 837/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1007598 t fired, 1205 attempts, .
74 EF STEQ 837/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 105/475 1/32 Szymanski-PT-b10-CTLFireability-10 116091 m, 1159 m/sec, 456033 t fired, .

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73 EF FNDP 842/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1013657 t fired, 1211 attempts, .
74 EF STEQ 842/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 110/475 1/32 Szymanski-PT-b10-CTLFireability-10 121686 m, 1119 m/sec, 474651 t fired, .

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73 EF FNDP 847/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1019750 t fired, 1217 attempts, .
74 EF STEQ 847/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 115/475 1/32 Szymanski-PT-b10-CTLFireability-10 127276 m, 1118 m/sec, 495055 t fired, .

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73 EF FNDP 852/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1025782 t fired, 1223 attempts, .
74 EF STEQ 852/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 120/475 1/32 Szymanski-PT-b10-CTLFireability-10 132862 m, 1117 m/sec, 517471 t fired, .

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73 EF FNDP 857/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1031777 t fired, 1230 attempts, .
74 EF STEQ 857/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 125/475 1/32 Szymanski-PT-b10-CTLFireability-10 138447 m, 1117 m/sec, 539191 t fired, .

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73 EF FNDP 862/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1037798 t fired, 1238 attempts, .
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76 EF EXCL 130/475 1/32 Szymanski-PT-b10-CTLFireability-10 143604 m, 1031 m/sec, 566846 t fired, .

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73 EF FNDP 867/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1044026 t fired, 1240 attempts, .
74 EF STEQ 867/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 135/475 1/32 Szymanski-PT-b10-CTLFireability-10 148519 m, 983 m/sec, 605183 t fired, .

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73 EF FNDP 872/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1050107 t fired, 1244 attempts, .
74 EF STEQ 872/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 140/475 1/32 Szymanski-PT-b10-CTLFireability-10 153591 m, 1014 m/sec, 637246 t fired, .

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73 EF FNDP 877/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1056337 t fired, 1245 attempts, .
74 EF STEQ 877/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 145/475 1/32 Szymanski-PT-b10-CTLFireability-10 159394 m, 1160 m/sec, 656053 t fired, .

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73 EF FNDP 882/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1062487 t fired, 1249 attempts, .
74 EF STEQ 882/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 150/475 1/32 Szymanski-PT-b10-CTLFireability-10 165199 m, 1161 m/sec, 675780 t fired, .

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73 EF FNDP 887/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1068708 t fired, 1252 attempts, .
74 EF STEQ 887/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 155/475 1/32 Szymanski-PT-b10-CTLFireability-10 171004 m, 1161 m/sec, 698214 t fired, .

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73 EF FNDP 892/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1074869 t fired, 1256 attempts, .
74 EF STEQ 892/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 160/475 1/32 Szymanski-PT-b10-CTLFireability-10 176808 m, 1160 m/sec, 718568 t fired, .

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73 EF FNDP 897/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1081020 t fired, 1259 attempts, .
74 EF STEQ 897/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 165/475 1/32 Szymanski-PT-b10-CTLFireability-10 182611 m, 1160 m/sec, 739785 t fired, .

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73 EF FNDP 902/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1087064 t fired, 1264 attempts, .
74 EF STEQ 902/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 170/475 1/32 Szymanski-PT-b10-CTLFireability-10 188425 m, 1162 m/sec, 759591 t fired, .

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73 EF FNDP 907/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1093143 t fired, 1268 attempts, .
74 EF STEQ 907/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 175/475 2/32 Szymanski-PT-b10-CTLFireability-10 194006 m, 1116 m/sec, 778450 t fired, .

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73 EF FNDP 912/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1099177 t fired, 1272 attempts, .
74 EF STEQ 912/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 180/475 2/32 Szymanski-PT-b10-CTLFireability-10 199578 m, 1114 m/sec, 798381 t fired, .

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73 EF FNDP 917/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1105295 t fired, 1276 attempts, .
74 EF STEQ 917/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 185/475 2/32 Szymanski-PT-b10-CTLFireability-10 205163 m, 1117 m/sec, 820875 t fired, .

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73 EF FNDP 922/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1111486 t fired, 1281 attempts, .
74 EF STEQ 922/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 190/475 2/32 Szymanski-PT-b10-CTLFireability-10 210754 m, 1118 m/sec, 843333 t fired, .

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73 EF FNDP 927/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1117577 t fired, 1285 attempts, .
74 EF STEQ 927/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 195/475 2/32 Szymanski-PT-b10-CTLFireability-10 216016 m, 1052 m/sec, 868284 t fired, .

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73 EF FNDP 932/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1123696 t fired, 1289 attempts, .
74 EF STEQ 932/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 200/475 2/32 Szymanski-PT-b10-CTLFireability-10 220932 m, 983 m/sec, 906856 t fired, .

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73 EF FNDP 937/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1129696 t fired, 1295 attempts, .
74 EF STEQ 937/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 205/475 2/32 Szymanski-PT-b10-CTLFireability-10 225840 m, 981 m/sec, 944578 t fired, .

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73 EF FNDP 942/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1135771 t fired, 1301 attempts, .
74 EF STEQ 942/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 210/475 2/32 Szymanski-PT-b10-CTLFireability-10 231537 m, 1139 m/sec, 963650 t fired, .

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73 EF FNDP 947/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1141839 t fired, 1306 attempts, .
74 EF STEQ 947/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 215/475 2/32 Szymanski-PT-b10-CTLFireability-10 237347 m, 1162 m/sec, 984057 t fired, .

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73 EF FNDP 952/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1147920 t fired, 1310 attempts, .
74 EF STEQ 952/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 220/475 2/32 Szymanski-PT-b10-CTLFireability-10 243164 m, 1163 m/sec, 1003591 t fired, .

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73 EF FNDP 957/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1153994 t fired, 1314 attempts, .
74 EF STEQ 957/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 225/475 2/32 Szymanski-PT-b10-CTLFireability-10 248975 m, 1162 m/sec, 1026048 t fired, .

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73 EF FNDP 962/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1160107 t fired, 1319 attempts, .
74 EF STEQ 962/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 230/475 2/32 Szymanski-PT-b10-CTLFireability-10 254788 m, 1162 m/sec, 1047356 t fired, .

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73 EF FNDP 967/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1166261 t fired, 1322 attempts, .
74 EF STEQ 967/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 235/475 2/32 Szymanski-PT-b10-CTLFireability-10 260595 m, 1161 m/sec, 1066944 t fired, .

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73 EF FNDP 972/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1172378 t fired, 1326 attempts, .
74 EF STEQ 972/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 240/475 2/32 Szymanski-PT-b10-CTLFireability-10 266281 m, 1137 m/sec, 1085561 t fired, .

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73 EF FNDP 977/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1178351 t fired, 1333 attempts, .
74 EF STEQ 977/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 245/475 2/32 Szymanski-PT-b10-CTLFireability-10 271852 m, 1114 m/sec, 1107090 t fired, .

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73 EF FNDP 982/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1184316 t fired, 1340 attempts, .
74 EF STEQ 982/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 250/475 2/32 Szymanski-PT-b10-CTLFireability-10 277433 m, 1116 m/sec, 1128048 t fired, .

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73 EF FNDP 987/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1190152 t fired, 1345 attempts, .
74 EF STEQ 987/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 255/475 2/32 Szymanski-PT-b10-CTLFireability-10 282842 m, 1081 m/sec, 1149531 t fired, .

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73 EF FNDP 992/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1196039 t fired, 1349 attempts, .
74 EF STEQ 992/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 260/475 2/32 Szymanski-PT-b10-CTLFireability-10 288157 m, 1063 m/sec, 1168910 t fired, .

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73 EF FNDP 997/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1201887 t fired, 1353 attempts, .
74 EF STEQ 997/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 265/475 2/32 Szymanski-PT-b10-CTLFireability-10 292892 m, 947 m/sec, 1202390 t fired, .

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73 EF FNDP 1002/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1207695 t fired, 1358 attempts, .
74 EF STEQ 1002/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 270/475 2/32 Szymanski-PT-b10-CTLFireability-10 297626 m, 946 m/sec, 1240979 t fired, .

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73 EF FNDP 1007/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1213584 t fired, 1361 attempts, .
74 EF STEQ 1007/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 275/475 2/32 Szymanski-PT-b10-CTLFireability-10 302897 m, 1054 m/sec, 1264292 t fired, .

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73 EF FNDP 1012/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1219335 t fired, 1366 attempts, .
74 EF STEQ 1012/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 280/475 2/32 Szymanski-PT-b10-CTLFireability-10 308515 m, 1123 m/sec, 1284545 t fired, .

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73 EF FNDP 1017/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1225260 t fired, 1369 attempts, .
74 EF STEQ 1017/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 285/475 2/32 Szymanski-PT-b10-CTLFireability-10 314141 m, 1125 m/sec, 1302491 t fired, .

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73 EF FNDP 1022/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1231100 t fired, 1373 attempts, .
74 EF STEQ 1022/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 290/475 2/32 Szymanski-PT-b10-CTLFireability-10 319747 m, 1121 m/sec, 1325092 t fired, .

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73 EF FNDP 1027/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1236905 t fired, 1376 attempts, .
74 EF STEQ 1027/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 295/475 2/32 Szymanski-PT-b10-CTLFireability-10 325375 m, 1125 m/sec, 1344169 t fired, .

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73 EF FNDP 1032/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1242819 t fired, 1381 attempts, .
74 EF STEQ 1032/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 300/475 2/32 Szymanski-PT-b10-CTLFireability-10 330999 m, 1124 m/sec, 1364756 t fired, .

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73 EF FNDP 1037/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1248694 t fired, 1384 attempts, .
74 EF STEQ 1037/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 305/475 2/32 Szymanski-PT-b10-CTLFireability-10 336544 m, 1109 m/sec, 1381673 t fired, .

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73 EF FNDP 1042/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1254509 t fired, 1391 attempts, .
74 EF STEQ 1042/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 310/475 2/32 Szymanski-PT-b10-CTLFireability-10 341934 m, 1078 m/sec, 1402396 t fired, .

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73 EF FNDP 1047/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1260339 t fired, 1396 attempts, .
74 EF STEQ 1047/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 315/475 2/32 Szymanski-PT-b10-CTLFireability-10 347322 m, 1077 m/sec, 1422700 t fired, .

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73 EF FNDP 1052/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1266139 t fired, 1402 attempts, .
74 EF STEQ 1052/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 320/475 2/32 Szymanski-PT-b10-CTLFireability-10 352702 m, 1076 m/sec, 1444005 t fired, .

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73 EF FNDP 1057/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1272053 t fired, 1406 attempts, .
74 EF STEQ 1057/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 325/475 2/32 Szymanski-PT-b10-CTLFireability-10 357619 m, 983 m/sec, 1471455 t fired, .

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73 EF FNDP 1062/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1277926 t fired, 1411 attempts, .
74 EF STEQ 1062/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 330/475 2/32 Szymanski-PT-b10-CTLFireability-10 362362 m, 948 m/sec, 1508020 t fired, .

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73 EF FNDP 1067/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1283822 t fired, 1416 attempts, .
74 EF STEQ 1067/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 335/475 2/32 Szymanski-PT-b10-CTLFireability-10 367638 m, 1055 m/sec, 1532519 t fired, .

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73 EF FNDP 1072/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1289649 t fired, 1421 attempts, .
74 EF STEQ 1072/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 340/475 2/32 Szymanski-PT-b10-CTLFireability-10 373264 m, 1125 m/sec, 1551014 t fired, .

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73 EF FNDP 1077/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1295542 t fired, 1425 attempts, .
74 EF STEQ 1077/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 345/475 2/32 Szymanski-PT-b10-CTLFireability-10 378862 m, 1119 m/sec, 1569309 t fired, .

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73 EF FNDP 1082/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1301467 t fired, 1428 attempts, .
74 EF STEQ 1082/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 350/475 2/32 Szymanski-PT-b10-CTLFireability-10 384452 m, 1118 m/sec, 1591793 t fired, .

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73 EF FNDP 1087/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1307338 t fired, 1432 attempts, .
74 EF STEQ 1087/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 355/475 3/32 Szymanski-PT-b10-CTLFireability-10 390087 m, 1127 m/sec, 1611520 t fired, .

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74 EF STEQ 1092/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 360/475 3/32 Szymanski-PT-b10-CTLFireability-10 395630 m, 1108 m/sec, 1628927 t fired, .

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74 EF STEQ 1097/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 365/475 3/32 Szymanski-PT-b10-CTLFireability-10 401026 m, 1079 m/sec, 1648545 t fired, .

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76 EF EXCL 370/475 3/32 Szymanski-PT-b10-CTLFireability-10 406420 m, 1078 m/sec, 1668430 t fired, .

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76 EF EXCL 375/475 3/32 Szymanski-PT-b10-CTLFireability-10 411349 m, 985 m/sec, 1697864 t fired, .

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76 EF EXCL 380/475 3/32 Szymanski-PT-b10-CTLFireability-10 416231 m, 976 m/sec, 1727917 t fired, .

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73 EF FNDP 1117/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1342458 t fired, 1460 attempts, .
74 EF STEQ 1117/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 385/475 3/32 Szymanski-PT-b10-CTLFireability-10 421791 m, 1112 m/sec, 1747412 t fired, .

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73 EF FNDP 1122/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1348504 t fired, 1465 attempts, .
74 EF STEQ 1122/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 390/475 3/32 Szymanski-PT-b10-CTLFireability-10 427610 m, 1163 m/sec, 1765816 t fired, .

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73 EF FNDP 1127/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1354502 t fired, 1470 attempts, .
74 EF STEQ 1127/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 395/475 3/32 Szymanski-PT-b10-CTLFireability-10 433344 m, 1146 m/sec, 1786369 t fired, .

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73 EF FNDP 1132/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1360436 t fired, 1475 attempts, .
74 EF STEQ 1132/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 400/475 3/32 Szymanski-PT-b10-CTLFireability-10 438968 m, 1124 m/sec, 1804718 t fired, .

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73 EF FNDP 1137/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1366494 t fired, 1480 attempts, .
74 EF STEQ 1137/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 405/475 3/32 Szymanski-PT-b10-CTLFireability-10 444538 m, 1114 m/sec, 1825020 t fired, .

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73 EF FNDP 1142/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1372553 t fired, 1482 attempts, .
74 EF STEQ 1142/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 410/475 3/32 Szymanski-PT-b10-CTLFireability-10 449465 m, 985 m/sec, 1853484 t fired, .

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73 EF FNDP 1147/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1378477 t fired, 1487 attempts, .
74 EF STEQ 1147/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 415/475 3/32 Szymanski-PT-b10-CTLFireability-10 454936 m, 1094 m/sec, 1874703 t fired, .

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73 EF FNDP 1152/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1384521 t fired, 1493 attempts, .
74 EF STEQ 1152/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 420/475 3/32 Szymanski-PT-b10-CTLFireability-10 460762 m, 1165 m/sec, 1893071 t fired, .

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73 EF FNDP 1157/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1390665 t fired, 1495 attempts, .
74 EF STEQ 1157/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 425/475 3/32 Szymanski-PT-b10-CTLFireability-10 466449 m, 1137 m/sec, 1912192 t fired, .

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73 EF FNDP 1162/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1396873 t fired, 1498 attempts, .
74 EF STEQ 1162/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 430/475 3/32 Szymanski-PT-b10-CTLFireability-10 471730 m, 1056 m/sec, 1935189 t fired, .

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73 EF FNDP 1167/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1402934 t fired, 1503 attempts, .
74 EF STEQ 1167/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 435/475 3/32 Szymanski-PT-b10-CTLFireability-10 477506 m, 1155 m/sec, 1953082 t fired, .

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73 EF FNDP 1172/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1408976 t fired, 1510 attempts, .
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76 EF EXCL 440/475 3/32 Szymanski-PT-b10-CTLFireability-10 483020 m, 1102 m/sec, 1972130 t fired, .

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73 EF FNDP 1237/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1487619 t fired, 1567 attempts, .
74 EF STEQ 1237/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 25/474 1/5 Szymanski-PT-b10-CTLFireability-10 27577 m, 1117 m/sec, 93347 t fired, .

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73 EF FNDP 1242/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1493692 t fired, 1573 attempts, .
74 EF STEQ 1242/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 30/474 1/5 Szymanski-PT-b10-CTLFireability-10 32866 m, 1057 m/sec, 116617 t fired, .

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73 EF FNDP 1247/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1499823 t fired, 1578 attempts, .
74 EF STEQ 1247/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 35/474 1/5 Szymanski-PT-b10-CTLFireability-10 37863 m, 999 m/sec, 150163 t fired, .

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73 EF FNDP 1252/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1505920 t fired, 1582 attempts, .
74 EF STEQ 1252/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 40/474 1/5 Szymanski-PT-b10-CTLFireability-10 43666 m, 1160 m/sec, 167759 t fired, .

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73 EF FNDP 1257/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1512026 t fired, 1586 attempts, .
74 EF STEQ 1257/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 45/474 1/5 Szymanski-PT-b10-CTLFireability-10 49468 m, 1160 m/sec, 188293 t fired, .

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73 EF FNDP 1262/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1518157 t fired, 1589 attempts, .
74 EF STEQ 1262/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 50/474 1/5 Szymanski-PT-b10-CTLFireability-10 55279 m, 1162 m/sec, 207749 t fired, .

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73 EF FNDP 1267/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1524308 t fired, 1591 attempts, .
74 EF STEQ 1267/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 55/474 1/5 Szymanski-PT-b10-CTLFireability-10 60932 m, 1130 m/sec, 224848 t fired, .

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73 EF FNDP 1272/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1530401 t fired, 1596 attempts, .
74 EF STEQ 1272/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 60/474 1/5 Szymanski-PT-b10-CTLFireability-10 66521 m, 1117 m/sec, 246394 t fired, .

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73 EF FNDP 1277/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1536589 t fired, 1598 attempts, .
74 EF STEQ 1277/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 65/474 1/5 Szymanski-PT-b10-CTLFireability-10 72113 m, 1118 m/sec, 267155 t fired, .

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73 EF FNDP 1282/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1542623 t fired, 1600 attempts, .
74 EF STEQ 1282/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 70/474 1/5 Szymanski-PT-b10-CTLFireability-10 77601 m, 1097 m/sec, 287850 t fired, .

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73 EF FNDP 1287/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1548675 t fired, 1605 attempts, .
74 EF STEQ 1287/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 75/474 1/5 Szymanski-PT-b10-CTLFireability-10 82527 m, 985 m/sec, 323569 t fired, .

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73 EF FNDP 1292/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1554740 t fired, 1608 attempts, .
74 EF STEQ 1292/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 80/474 1/5 Szymanski-PT-b10-CTLFireability-10 87541 m, 1002 m/sec, 357920 t fired, .

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73 EF FNDP 1297/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1560807 t fired, 1614 attempts, .
74 EF STEQ 1297/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 85/474 1/5 Szymanski-PT-b10-CTLFireability-10 93346 m, 1161 m/sec, 376865 t fired, .

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73 EF FNDP 1302/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1567003 t fired, 1616 attempts, .
74 EF STEQ 1302/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 90/474 1/5 Szymanski-PT-b10-CTLFireability-10 99129 m, 1156 m/sec, 395922 t fired, .

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73 EF FNDP 1307/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1573003 t fired, 1620 attempts, .
74 EF STEQ 1307/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 95/474 1/5 Szymanski-PT-b10-CTLFireability-10 104771 m, 1128 m/sec, 416086 t fired, .

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73 EF FNDP 1312/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1578696 t fired, 1624 attempts, .
74 EF STEQ 1312/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 100/474 1/5 Szymanski-PT-b10-CTLFireability-10 110114 m, 1068 m/sec, 435756 t fired, .

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73 EF FNDP 1317/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1584515 t fired, 1627 attempts, .
74 EF STEQ 1317/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 105/474 1/5 Szymanski-PT-b10-CTLFireability-10 115650 m, 1107 m/sec, 454434 t fired, .

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73 EF FNDP 1322/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1590358 t fired, 1631 attempts, .
74 EF STEQ 1322/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 110/474 1/5 Szymanski-PT-b10-CTLFireability-10 120975 m, 1065 m/sec, 471420 t fired, .

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73 EF FNDP 1327/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1596310 t fired, 1632 attempts, .
74 EF STEQ 1327/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 115/474 1/5 Szymanski-PT-b10-CTLFireability-10 126324 m, 1069 m/sec, 491582 t fired, .

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73 EF FNDP 1332/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1602120 t fired, 1635 attempts, .
74 EF STEQ 1332/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 120/474 1/5 Szymanski-PT-b10-CTLFireability-10 131600 m, 1055 m/sec, 511685 t fired, .

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73 EF FNDP 1337/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1608031 t fired, 1640 attempts, .
74 EF STEQ 1337/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 125/474 1/5 Szymanski-PT-b10-CTLFireability-10 137095 m, 1099 m/sec, 533044 t fired, .

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73 EF FNDP 1342/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1613976 t fired, 1643 attempts, .
74 EF STEQ 1342/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 130/474 1/5 Szymanski-PT-b10-CTLFireability-10 142311 m, 1043 m/sec, 556907 t fired, .

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73 EF FNDP 1347/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1620059 t fired, 1649 attempts, .
74 EF STEQ 1347/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 135/474 1/5 Szymanski-PT-b10-CTLFireability-10 147228 m, 983 m/sec, 594187 t fired, .

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73 EF FNDP 1352/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1626232 t fired, 1652 attempts, .
74 EF STEQ 1352/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 140/474 1/5 Szymanski-PT-b10-CTLFireability-10 152147 m, 983 m/sec, 632553 t fired, .

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73 EF FNDP 1357/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1632385 t fired, 1654 attempts, .
74 EF STEQ 1357/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 145/474 1/5 Szymanski-PT-b10-CTLFireability-10 157864 m, 1143 m/sec, 651059 t fired, .

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73 EF FNDP 1362/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1638523 t fired, 1657 attempts, .
74 EF STEQ 1362/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 150/474 1/5 Szymanski-PT-b10-CTLFireability-10 163662 m, 1159 m/sec, 671660 t fired, .

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73 EF FNDP 1367/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1644520 t fired, 1660 attempts, .
74 EF STEQ 1367/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 155/474 1/5 Szymanski-PT-b10-CTLFireability-10 169374 m, 1142 m/sec, 691752 t fired, .

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73 EF FNDP 1372/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1650300 t fired, 1663 attempts, .
74 EF STEQ 1372/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 160/474 1/5 Szymanski-PT-b10-CTLFireability-10 174876 m, 1100 m/sec, 711381 t fired, .

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73 EF FNDP 1377/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1656008 t fired, 1669 attempts, .
74 EF STEQ 1377/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 165/474 1/5 Szymanski-PT-b10-CTLFireability-10 180378 m, 1100 m/sec, 731203 t fired, .

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73 EF FNDP 1382/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1662023 t fired, 1672 attempts, .
74 EF STEQ 1382/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 170/474 1/5 Szymanski-PT-b10-CTLFireability-10 186044 m, 1133 m/sec, 751248 t fired, .

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73 EF FNDP 1387/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1668024 t fired, 1676 attempts, .
74 EF STEQ 1387/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 175/474 1/5 Szymanski-PT-b10-CTLFireability-10 191671 m, 1125 m/sec, 769863 t fired, .

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73 EF FNDP 1392/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1674078 t fired, 1678 attempts, .
74 EF STEQ 1392/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 180/474 2/5 Szymanski-PT-b10-CTLFireability-10 197204 m, 1106 m/sec, 790081 t fired, .

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73 EF FNDP 1397/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1680099 t fired, 1681 attempts, .
74 EF STEQ 1397/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 185/474 2/5 Szymanski-PT-b10-CTLFireability-10 202744 m, 1108 m/sec, 812134 t fired, .

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73 EF FNDP 1402/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1686239 t fired, 1682 attempts, .
74 EF STEQ 1402/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 190/474 2/5 Szymanski-PT-b10-CTLFireability-10 208278 m, 1106 m/sec, 833016 t fired, .

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73 EF FNDP 1407/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1692417 t fired, 1684 attempts, .
74 EF STEQ 1407/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 195/474 2/5 Szymanski-PT-b10-CTLFireability-10 213800 m, 1104 m/sec, 854321 t fired, .

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73 EF FNDP 1412/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1698482 t fired, 1687 attempts, .
74 EF STEQ 1412/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 200/474 2/5 Szymanski-PT-b10-CTLFireability-10 218682 m, 976 m/sec, 887057 t fired, .

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73 EF FNDP 1417/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1704616 t fired, 1690 attempts, .
74 EF STEQ 1417/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 205/474 2/5 Szymanski-PT-b10-CTLFireability-10 223555 m, 974 m/sec, 926909 t fired, .

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73 EF FNDP 1422/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1710720 t fired, 1692 attempts, .
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76 EF EXCL 210/474 2/5 Szymanski-PT-b10-CTLFireability-10 228795 m, 1048 m/sec, 954061 t fired, .

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73 EF FNDP 1427/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1716755 t fired, 1693 attempts, .
74 EF STEQ 1427/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 215/474 2/5 Szymanski-PT-b10-CTLFireability-10 234545 m, 1150 m/sec, 974803 t fired, .

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73 EF FNDP 1432/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1722756 t fired, 1696 attempts, .
74 EF STEQ 1432/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 220/474 2/5 Szymanski-PT-b10-CTLFireability-10 240307 m, 1152 m/sec, 993047 t fired, .

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73 EF FNDP 1437/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1728789 t fired, 1701 attempts, .
74 EF STEQ 1437/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 225/474 2/5 Szymanski-PT-b10-CTLFireability-10 246059 m, 1150 m/sec, 1014835 t fired, .

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73 EF FNDP 1442/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1734812 t fired, 1705 attempts, .
74 EF STEQ 1442/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 230/474 2/5 Szymanski-PT-b10-CTLFireability-10 251808 m, 1149 m/sec, 1034976 t fired, .

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73 EF FNDP 1447/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1740862 t fired, 1707 attempts, .
74 EF STEQ 1447/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 235/474 2/5 Szymanski-PT-b10-CTLFireability-10 257555 m, 1149 m/sec, 1056092 t fired, .

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73 EF FNDP 1453/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1746854 t fired, 1710 attempts, .
74 EF STEQ 1453/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 241/474 2/5 Szymanski-PT-b10-CTLFireability-10 263305 m, 1150 m/sec, 1077362 t fired, .

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73 EF FNDP 1458/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1752791 t fired, 1716 attempts, .
74 EF STEQ 1458/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 246/474 2/5 Szymanski-PT-b10-CTLFireability-10 268854 m, 1109 m/sec, 1095124 t fired, .

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73 EF FNDP 1463/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1758896 t fired, 1717 attempts, .
74 EF STEQ 1463/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 251/474 2/5 Szymanski-PT-b10-CTLFireability-10 274380 m, 1105 m/sec, 1114634 t fired, .

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74 EF STEQ 1468/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 256/474 2/5 Szymanski-PT-b10-CTLFireability-10 279903 m, 1104 m/sec, 1137302 t fired, .

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73 EF FNDP 1473/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1771122 t fired, 1721 attempts, .
74 EF STEQ 1473/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 261/474 2/5 Szymanski-PT-b10-CTLFireability-10 285428 m, 1105 m/sec, 1159686 t fired, .

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76 EF EXCL 266/474 2/5 Szymanski-PT-b10-CTLFireability-10 290549 m, 1024 m/sec, 1186450 t fired, .

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76 EF EXCL 271/474 2/5 Szymanski-PT-b10-CTLFireability-10 295418 m, 973 m/sec, 1224427 t fired, .

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73 EF FNDP 1488/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1789374 t fired, 1730 attempts, .
74 EF STEQ 1488/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 276/474 2/5 Szymanski-PT-b10-CTLFireability-10 300418 m, 1000 m/sec, 1257059 t fired, .

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73 EF FNDP 1493/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1795311 t fired, 1734 attempts, .
74 EF STEQ 1493/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 281/474 2/5 Szymanski-PT-b10-CTLFireability-10 306162 m, 1148 m/sec, 1275551 t fired, .

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73 EF FNDP 1498/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1801327 t fired, 1737 attempts, .
74 EF STEQ 1498/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 286/474 2/5 Szymanski-PT-b10-CTLFireability-10 311910 m, 1149 m/sec, 1296731 t fired, .

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73 EF FNDP 1503/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1807330 t fired, 1743 attempts, .
74 EF STEQ 1503/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 291/474 2/5 Szymanski-PT-b10-CTLFireability-10 317666 m, 1151 m/sec, 1316079 t fired, .

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73 EF FNDP 1508/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1813382 t fired, 1746 attempts, .
74 EF STEQ 1508/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 296/474 2/5 Szymanski-PT-b10-CTLFireability-10 323419 m, 1150 m/sec, 1336639 t fired, .

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73 EF FNDP 1513/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1819382 t fired, 1751 attempts, .
74 EF STEQ 1513/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 301/474 2/5 Szymanski-PT-b10-CTLFireability-10 329167 m, 1149 m/sec, 1358160 t fired, .

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73 EF FNDP 1518/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1825353 t fired, 1756 attempts, .
74 EF STEQ 1518/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 306/474 2/5 Szymanski-PT-b10-CTLFireability-10 334900 m, 1146 m/sec, 1378330 t fired, .

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73 EF FNDP 1523/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1831392 t fired, 1758 attempts, .
74 EF STEQ 1523/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 311/474 2/5 Szymanski-PT-b10-CTLFireability-10 340419 m, 1103 m/sec, 1397595 t fired, .

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73 EF FNDP 1528/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1837370 t fired, 1763 attempts, .
74 EF STEQ 1528/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 316/474 2/5 Szymanski-PT-b10-CTLFireability-10 345951 m, 1106 m/sec, 1418087 t fired, .

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74 EF STEQ 1533/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 321/474 2/5 Szymanski-PT-b10-CTLFireability-10 351477 m, 1105 m/sec, 1439266 t fired, .

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74 EF STEQ 1538/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 326/474 2/5 Szymanski-PT-b10-CTLFireability-10 356676 m, 1039 m/sec, 1464537 t fired, .

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73 EF FNDP 1543/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1855424 t fired, 1773 attempts, .
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76 EF EXCL 331/474 2/5 Szymanski-PT-b10-CTLFireability-10 361534 m, 971 m/sec, 1502065 t fired, .

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73 EF FNDP 1548/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1861445 t fired, 1775 attempts, .
74 EF STEQ 1548/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 336/474 2/5 Szymanski-PT-b10-CTLFireability-10 366788 m, 1050 m/sec, 1528035 t fired, .

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73 EF FNDP 1553/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1867429 t fired, 1776 attempts, .
74 EF STEQ 1553/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 341/474 2/5 Szymanski-PT-b10-CTLFireability-10 372526 m, 1147 m/sec, 1549626 t fired, .

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73 EF FNDP 1558/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1873403 t fired, 1778 attempts, .
74 EF STEQ 1558/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 346/474 2/5 Szymanski-PT-b10-CTLFireability-10 378280 m, 1150 m/sec, 1566992 t fired, .

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73 EF FNDP 1563/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1879486 t fired, 1781 attempts, .
74 EF STEQ 1563/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 351/474 2/5 Szymanski-PT-b10-CTLFireability-10 384026 m, 1149 m/sec, 1589419 t fired, .

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73 EF FNDP 1568/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1885620 t fired, 1782 attempts, .
74 EF STEQ 1568/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 356/474 3/5 Szymanski-PT-b10-CTLFireability-10 389785 m, 1151 m/sec, 1610220 t fired, .

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73 EF FNDP 1573/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1891764 t fired, 1785 attempts, .
74 EF STEQ 1573/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 361/474 3/5 Szymanski-PT-b10-CTLFireability-10 395454 m, 1133 m/sec, 1628698 t fired, .

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73 EF FNDP 1578/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1897774 t fired, 1787 attempts, .
74 EF STEQ 1578/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 366/474 3/5 Szymanski-PT-b10-CTLFireability-10 400967 m, 1102 m/sec, 1648469 t fired, .

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73 EF FNDP 1583/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1903856 t fired, 1788 attempts, .
74 EF STEQ 1583/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 371/474 3/5 Szymanski-PT-b10-CTLFireability-10 406490 m, 1104 m/sec, 1668523 t fired, .

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73 EF FNDP 1588/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1909870 t fired, 1793 attempts, .
74 EF STEQ 1588/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 376/474 3/5 Szymanski-PT-b10-CTLFireability-10 411512 m, 1004 m/sec, 1698588 t fired, .

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74 EF STEQ 1593/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 381/474 3/5 Szymanski-PT-b10-CTLFireability-10 416533 m, 1004 m/sec, 1728478 t fired, .

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74 EF STEQ 1598/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 386/474 3/5 Szymanski-PT-b10-CTLFireability-10 422113 m, 1116 m/sec, 1748020 t fired, .

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73 EF FNDP 1603/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1927586 t fired, 1800 attempts, .
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76 EF EXCL 391/474 3/5 Szymanski-PT-b10-CTLFireability-10 427706 m, 1118 m/sec, 1767100 t fired, .

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76 EF EXCL 396/474 3/5 Szymanski-PT-b10-CTLFireability-10 433283 m, 1115 m/sec, 1786253 t fired, .

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73 EF FNDP 1613/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1939359 t fired, 1808 attempts, .
74 EF STEQ 1613/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 401/474 3/5 Szymanski-PT-b10-CTLFireability-10 438776 m, 1098 m/sec, 1803449 t fired, .

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73 EF FNDP 1618/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1945205 t fired, 1811 attempts, .
74 EF STEQ 1618/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 406/474 3/5 Szymanski-PT-b10-CTLFireability-10 444128 m, 1070 m/sec, 1822906 t fired, .

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73 EF FNDP 1623/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1951076 t fired, 1814 attempts, .
74 EF STEQ 1623/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 411/474 3/5 Szymanski-PT-b10-CTLFireability-10 449022 m, 978 m/sec, 1850115 t fired, .

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73 EF FNDP 1628/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1956928 t fired, 1816 attempts, .
74 EF STEQ 1628/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 416/474 3/5 Szymanski-PT-b10-CTLFireability-10 454323 m, 1060 m/sec, 1871710 t fired, .

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73 EF FNDP 1633/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1962805 t fired, 1820 attempts, .
74 EF STEQ 1633/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 421/474 3/5 Szymanski-PT-b10-CTLFireability-10 459914 m, 1118 m/sec, 1890296 t fired, .

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73 EF FNDP 1638/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1968892 t fired, 1823 attempts, .
74 EF STEQ 1638/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 426/474 3/5 Szymanski-PT-b10-CTLFireability-10 465529 m, 1123 m/sec, 1908532 t fired, .

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73 EF FNDP 1643/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1974964 t fired, 1825 attempts, .
74 EF STEQ 1643/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 431/474 3/5 Szymanski-PT-b10-CTLFireability-10 470736 m, 1041 m/sec, 1932429 t fired, .

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73 EF FNDP 1648/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1981031 t fired, 1828 attempts, .
74 EF STEQ 1648/3582 0/5 Szymanski-PT-b10-CTLFireability-10 sara is running.
76 EF EXCL 436/474 3/5 Szymanski-PT-b10-CTLFireability-10 476513 m, 1155 m/sec, 1950232 t fired, .

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73 EF FNDP 1653/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1987073 t fired, 1831 attempts, .
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76 EF EXCL 441/474 3/5 Szymanski-PT-b10-CTLFireability-10 482004 m, 1098 m/sec, 1968055 t fired, .

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73 EF FNDP 1658/3582 0/5 Szymanski-PT-b10-CTLFireability-10 1992961 t fired, 1832 attempts, .
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76 EF EXCL 446/474 3/5 Szymanski-PT-b10-CTLFireability-10 487344 m, 1068 m/sec, 1988627 t fired, .

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Szymanski-PT-b10-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-09: CTL false CTL model checker
Szymanski-PT-b10-CTLFireability-10: CONJ false findpath
Szymanski-PT-b10-CTLFireability-12: EFAG true tscc_search
Szymanski-PT-b10-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-b10-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-15: INITIAL false preprocessing

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30 EU EXCL 10/639 1/5 Szymanski-PT-b10-CTLFireability-07 9769 m, 987 m/sec, 16181 t fired, .

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Szymanski-PT-b10-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-09: CTL false CTL model checker
Szymanski-PT-b10-CTLFireability-10: CONJ false findpath
Szymanski-PT-b10-CTLFireability-12: EFAG true tscc_search
Szymanski-PT-b10-CTLFireability-13: CTL false CTL model checker
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30 EU EXCL 15/639 1/5 Szymanski-PT-b10-CTLFireability-07 14865 m, 1019 m/sec, 24925 t fired, .

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Szymanski-PT-b10-CTLFireability-04: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-09: CTL false CTL model checker
Szymanski-PT-b10-CTLFireability-10: CONJ false findpath
Szymanski-PT-b10-CTLFireability-12: EFAG true tscc_search
Szymanski-PT-b10-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-b10-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-15: INITIAL false preprocessing

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30 EU EXCL 20/639 1/5 Szymanski-PT-b10-CTLFireability-07 21365 m, 1300 m/sec, 51102 t fired, .

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Szymanski-PT-b10-CTLFireability-04: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-09: CTL false CTL model checker
Szymanski-PT-b10-CTLFireability-10: CONJ false findpath
Szymanski-PT-b10-CTLFireability-12: EFAG true tscc_search
Szymanski-PT-b10-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-b10-CTLFireability-14: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-15: INITIAL false preprocessing

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30 EU EXCL 25/639 1/5 Szymanski-PT-b10-CTLFireability-07 28294 m, 1385 m/sec, 89083 t fired, .

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Szymanski-PT-b10-CTLFireability-04: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-09: CTL false CTL model checker
Szymanski-PT-b10-CTLFireability-10: CONJ false findpath
Szymanski-PT-b10-CTLFireability-12: EFAG true tscc_search
Szymanski-PT-b10-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-b10-CTLFireability-14: CTL true CTL model checker
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Szymanski-PT-b10-CTLFireability-04: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-06: CTL true CTL model checker
Szymanski-PT-b10-CTLFireability-09: CTL false CTL model checker
Szymanski-PT-b10-CTLFireability-10: CONJ false findpath
Szymanski-PT-b10-CTLFireability-12: EFAG true tscc_search
Szymanski-PT-b10-CTLFireability-13: CTL false CTL model checker
Szymanski-PT-b10-CTLFireability-14: CTL true CTL model checker
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30 EU EXCL 35/639 1/5 Szymanski-PT-b10-CTLFireability-07 41532 m, 1278 m/sec, 170448 t fired, .

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Szymanski-PT-b10-CTLFireability-09: CTL false CTL model checker
Szymanski-PT-b10-CTLFireability-10: CONJ false findpath
Szymanski-PT-b10-CTLFireability-12: EFAG true tscc_search
Szymanski-PT-b10-CTLFireability-13: CTL false CTL model checker
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Szymanski-PT-b10-CTLFireability-09: CTL false CTL model checker
Szymanski-PT-b10-CTLFireability-10: CONJ false findpath
Szymanski-PT-b10-CTLFireability-12: EFAG true tscc_search

========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Szymanski-PT-b10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is Szymanski-PT-b10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r486-tall-167912701300482"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Szymanski-PT-b10.tgz
mv Szymanski-PT-b10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;