About the Execution of LoLa+red for StigmergyElection-PT-07a
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
558.472 | 15741.00 | 32690.00 | 588.80 | TFTFFTFTTTTFTFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r455-smll-167912647600638.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is StigmergyElection-PT-07a, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912647600638
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.2M
-rw-r--r-- 1 mcc users 5.1K Feb 26 16:40 CTLCardinality.txt
-rw-r--r-- 1 mcc users 50K Feb 26 16:40 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Feb 26 16:37 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 26 16:37 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 17:14 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 17:14 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 17:14 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:14 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 16:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 160K Feb 26 16:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 16:42 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 94K Feb 26 16:42 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 17:14 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 17:14 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 1.8M Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME StigmergyElection-PT-07a-ReachabilityCardinality-00
FORMULA_NAME StigmergyElection-PT-07a-ReachabilityCardinality-01
FORMULA_NAME StigmergyElection-PT-07a-ReachabilityCardinality-02
FORMULA_NAME StigmergyElection-PT-07a-ReachabilityCardinality-03
FORMULA_NAME StigmergyElection-PT-07a-ReachabilityCardinality-04
FORMULA_NAME StigmergyElection-PT-07a-ReachabilityCardinality-05
FORMULA_NAME StigmergyElection-PT-07a-ReachabilityCardinality-06
FORMULA_NAME StigmergyElection-PT-07a-ReachabilityCardinality-07
FORMULA_NAME StigmergyElection-PT-07a-ReachabilityCardinality-08
FORMULA_NAME StigmergyElection-PT-07a-ReachabilityCardinality-09
FORMULA_NAME StigmergyElection-PT-07a-ReachabilityCardinality-10
FORMULA_NAME StigmergyElection-PT-07a-ReachabilityCardinality-11
FORMULA_NAME StigmergyElection-PT-07a-ReachabilityCardinality-12
FORMULA_NAME StigmergyElection-PT-07a-ReachabilityCardinality-13
FORMULA_NAME StigmergyElection-PT-07a-ReachabilityCardinality-14
FORMULA_NAME StigmergyElection-PT-07a-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1679319421406
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=StigmergyElection-PT-07a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-20 13:37:05] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2023-03-20 13:37:05] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-20 13:37:05] [INFO ] Load time of PNML (sax parser for PT used): 596 ms
[2023-03-20 13:37:05] [INFO ] Transformed 100 places.
[2023-03-20 13:37:05] [INFO ] Transformed 2618 transitions.
[2023-03-20 13:37:05] [INFO ] Found NUPN structural information;
[2023-03-20 13:37:05] [INFO ] Parsed PT model containing 100 places and 2618 transitions and 34799 arcs in 794 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 40 ms.
Working with output stream class java.io.PrintStream
Ensure Unique test removed 2229 transitions
Reduce redundant transitions removed 2229 transitions.
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-00 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-04 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-05 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-10 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10000 steps, including 8 resets, run finished after 760 ms. (steps per millisecond=13 ) properties (out of 12) seen :6
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-14 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-11 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-06 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-03 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-02 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-01 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 50 ms. (steps per millisecond=200 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 49 ms. (steps per millisecond=204 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 3 resets, run finished after 73 ms. (steps per millisecond=137 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=322 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 3 resets, run finished after 49 ms. (steps per millisecond=204 ) properties (out of 6) seen :0
Running SMT prover for 6 properties.
[2023-03-20 13:37:07] [INFO ] Flow matrix only has 368 transitions (discarded 21 similar events)
// Phase 1: matrix 368 rows 100 cols
[2023-03-20 13:37:07] [INFO ] Computed 8 place invariants in 34 ms
[2023-03-20 13:37:07] [INFO ] After 377ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:6
[2023-03-20 13:37:07] [INFO ] [Nat]Absence check using 8 positive place invariants in 17 ms returned sat
[2023-03-20 13:37:08] [INFO ] After 543ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :6
[2023-03-20 13:37:08] [INFO ] State equation strengthened by 288 read => feed constraints.
[2023-03-20 13:37:08] [INFO ] After 326ms SMT Verify possible using 288 Read/Feed constraints in natural domain returned unsat :0 sat :6
[2023-03-20 13:37:09] [INFO ] Deduced a trap composed of 13 places in 181 ms of which 10 ms to minimize.
[2023-03-20 13:37:09] [INFO ] Deduced a trap composed of 12 places in 171 ms of which 1 ms to minimize.
[2023-03-20 13:37:09] [INFO ] Deduced a trap composed of 12 places in 144 ms of which 1 ms to minimize.
[2023-03-20 13:37:09] [INFO ] Deduced a trap composed of 12 places in 107 ms of which 1 ms to minimize.
[2023-03-20 13:37:09] [INFO ] Deduced a trap composed of 12 places in 143 ms of which 2 ms to minimize.
[2023-03-20 13:37:09] [INFO ] Deduced a trap composed of 12 places in 131 ms of which 1 ms to minimize.
[2023-03-20 13:37:10] [INFO ] Deduced a trap composed of 12 places in 107 ms of which 1 ms to minimize.
[2023-03-20 13:37:10] [INFO ] Deduced a trap composed of 12 places in 103 ms of which 0 ms to minimize.
[2023-03-20 13:37:10] [INFO ] Deduced a trap composed of 12 places in 78 ms of which 0 ms to minimize.
[2023-03-20 13:37:10] [INFO ] Deduced a trap composed of 12 places in 68 ms of which 1 ms to minimize.
[2023-03-20 13:37:10] [INFO ] Trap strengthening (SAT) tested/added 11/10 trap constraints in 1469 ms
[2023-03-20 13:37:10] [INFO ] Deduced a trap composed of 13 places in 160 ms of which 1 ms to minimize.
[2023-03-20 13:37:10] [INFO ] Deduced a trap composed of 13 places in 140 ms of which 1 ms to minimize.
[2023-03-20 13:37:10] [INFO ] Deduced a trap composed of 13 places in 141 ms of which 1 ms to minimize.
[2023-03-20 13:37:11] [INFO ] Deduced a trap composed of 12 places in 111 ms of which 1 ms to minimize.
[2023-03-20 13:37:11] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 4 trap constraints in 643 ms
[2023-03-20 13:37:11] [INFO ] Deduced a trap composed of 12 places in 132 ms of which 1 ms to minimize.
[2023-03-20 13:37:11] [INFO ] Deduced a trap composed of 13 places in 132 ms of which 1 ms to minimize.
[2023-03-20 13:37:11] [INFO ] Deduced a trap composed of 12 places in 125 ms of which 1 ms to minimize.
[2023-03-20 13:37:11] [INFO ] Deduced a trap composed of 12 places in 109 ms of which 2 ms to minimize.
[2023-03-20 13:37:11] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 4 trap constraints in 600 ms
[2023-03-20 13:37:11] [INFO ] After 3318ms SMT Verify possible using trap constraints in natural domain returned unsat :5 sat :1
Attempting to minimize the solution found.
Minimization took 70 ms.
[2023-03-20 13:37:11] [INFO ] After 4185ms SMT Verify possible using all constraints in natural domain returned unsat :5 sat :1
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-15 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-13 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-12 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-09 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-08 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 6 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 14 ms.
Support contains 8 out of 100 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 100/100 places, 389/389 transitions.
Graph (complete) has 288 edges and 100 vertex of which 93 are kept as prefixes of interest. Removing 7 places using SCC suffix rule.19 ms
Discarding 7 places :
Also discarding 7 output transitions
Drop transitions removed 7 transitions
Drop transitions removed 22 transitions
Reduce isomorphic transitions removed 22 transitions.
Drop transitions removed 10 transitions
Trivial Post-agglo rules discarded 10 transitions
Performed 10 trivial Post agglomeration. Transition count delta: 10
Iterating post reduction 0 with 32 rules applied. Total rules applied 33 place count 93 transition count 350
Reduce places removed 10 places and 0 transitions.
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded 6 transitions
Performed 6 trivial Post agglomeration. Transition count delta: 6
Iterating post reduction 1 with 26 rules applied. Total rules applied 59 place count 83 transition count 334
Reduce places removed 6 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 2 with 7 rules applied. Total rules applied 66 place count 77 transition count 333
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 68 place count 76 transition count 332
Performed 11 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 11 Pre rules applied. Total rules applied 68 place count 76 transition count 321
Deduced a syphon composed of 11 places in 1 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 4 with 22 rules applied. Total rules applied 90 place count 65 transition count 321
Discarding 12 places :
Symmetric choice reduction at 4 with 12 rule applications. Total rules 102 place count 53 transition count 309
Iterating global reduction 4 with 12 rules applied. Total rules applied 114 place count 53 transition count 309
Discarding 10 places :
Symmetric choice reduction at 4 with 10 rule applications. Total rules 124 place count 43 transition count 298
Iterating global reduction 4 with 10 rules applied. Total rules applied 134 place count 43 transition count 298
Ensure Unique test removed 20 transitions
Reduce isomorphic transitions removed 20 transitions.
Iterating post reduction 4 with 20 rules applied. Total rules applied 154 place count 43 transition count 278
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 1 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 5 with 12 rules applied. Total rules applied 166 place count 37 transition count 272
Discarding 6 places :
Symmetric choice reduction at 5 with 6 rule applications. Total rules 172 place count 31 transition count 266
Iterating global reduction 5 with 6 rules applied. Total rules applied 178 place count 31 transition count 266
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 5 with 2 rules applied. Total rules applied 180 place count 31 transition count 264
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 182 place count 30 transition count 263
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules 183 place count 29 transition count 262
Iterating global reduction 5 with 1 rules applied. Total rules applied 184 place count 29 transition count 262
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 185 place count 29 transition count 261
Applied a total of 185 rules in 257 ms. Remains 29 /100 variables (removed 71) and now considering 261/389 (removed 128) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 258 ms. Remains : 29/100 places, 261/389 transitions.
Finished random walk after 2018 steps, including 0 resets, run visited all 1 properties in 85 ms. (steps per millisecond=23 )
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-07 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
All properties solved without resorting to model-checking.
Total runtime 7296 ms.
starting LoLA
BK_INPUT StigmergyElection-PT-07a
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-07a-ReachabilityCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679319437147
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 53 (type EXCL) for 15 StigmergyElection-PT-07a-ReachabilityCardinality-05
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 49 (type FNDP) for 15 StigmergyElection-PT-07a-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type EQUN) for 15 StigmergyElection-PT-07a-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type SRCH) for 15 StigmergyElection-PT-07a-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 52 (type SRCH) for StigmergyElection-PT-07a-ReachabilityCardinality-05
lola: result : false
lola: markings : 557
lola: fired transitions : 852
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 49 (type FNDP) for StigmergyElection-PT-07a-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 50 (type EQUN) for StigmergyElection-PT-07a-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 53 (type EXCL) for StigmergyElection-PT-07a-ReachabilityCardinality-05 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 61 (type EXCL) for 9 StigmergyElection-PT-07a-ReachabilityCardinality-03
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 63 (type FNDP) for 30 StigmergyElection-PT-07a-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 64 (type EQUN) for 30 StigmergyElection-PT-07a-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 66 (type SRCH) for 30 StigmergyElection-PT-07a-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 66 (type SRCH) for StigmergyElection-PT-07a-ReachabilityCardinality-10
lola: result : false
lola: markings : 2
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: fired transitions : 2
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 63 (type FNDP) for StigmergyElection-PT-07a-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 64 (type EQUN) for StigmergyElection-PT-07a-ReachabilityCardinality-10 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 74 (type FNDP) for 27 StigmergyElection-PT-07a-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type EQUN) for 27 StigmergyElection-PT-07a-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type SRCH) for 27 StigmergyElection-PT-07a-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 63 (type FNDP) for StigmergyElection-PT-07a-ReachabilityCardinality-10
lola: result : unknown
lola: fired transitions : 22085
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 61 (type EXCL) for StigmergyElection-PT-07a-ReachabilityCardinality-03
lola: result : true
lola: markings : 32
lola: fired transitions : 38
lola: time used : 1.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 92 (type EXCL) for 21 StigmergyElection-PT-07a-ReachabilityCardinality-07
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-50.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-64.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 75 (type EQUN) for StigmergyElection-PT-07a-ReachabilityCardinality-09
lola: result : unknown
lola: LAUNCH task # 108 (type FNDP) for 33 StigmergyElection-PT-07a-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 92 (type EXCL) for StigmergyElection-PT-07a-ReachabilityCardinality-07
lola: result : true
lola: markings : 248
lola: fired transitions : 437
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 84 (type EXCL) for 39 StigmergyElection-PT-07a-ReachabilityCardinality-13
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 64 (type EQUN) for StigmergyElection-PT-07a-ReachabilityCardinality-10
lola: result : false
lola: FINISHED task # 77 (type SRCH) for StigmergyElection-PT-07a-ReachabilityCardinality-09
lola: result : false
lola: markings : 3480
lola: fired transitions : 6618
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 74 (type FNDP) for StigmergyElection-PT-07a-ReachabilityCardinality-09 (obsolete)
lola: LAUNCH task # 120 (type FNDP) for 24 StigmergyElection-PT-07a-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 137 (type EQUN) for 24 StigmergyElection-PT-07a-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 74 (type FNDP) for StigmergyElection-PT-07a-ReachabilityCardinality-09
lola: result : unknown
lola: fired transitions : 3050
lola: tried executions : 2
lola: time used : 1.000000
lola: memory pages used : 0
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-137.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 84 (type EXCL) for StigmergyElection-PT-07a-ReachabilityCardinality-13
lola: result : false
lola: markings : 645
lola: fired transitions : 1090
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 143 (type EXCL) for 42 StigmergyElection-PT-07a-ReachabilityCardinality-14
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 143 (type EXCL) for StigmergyElection-PT-07a-ReachabilityCardinality-14
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 140 (type EXCL) for 18 StigmergyElection-PT-07a-ReachabilityCardinality-06
lola: time limit : 399 sec
lola: memory limit: 32 pages
lola: FINISHED task # 140 (type EXCL) for StigmergyElection-PT-07a-ReachabilityCardinality-06
lola: result : true
lola: markings : 5
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 153 (type EXCL) for 0 StigmergyElection-PT-07a-ReachabilityCardinality-00
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: FINISHED task # 153 (type EXCL) for StigmergyElection-PT-07a-ReachabilityCardinality-00
lola: result : false
lola: markings : 721
lola: fired transitions : 1045
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 90 (type EXCL) for 3 StigmergyElection-PT-07a-ReachabilityCardinality-01
lola: time limit : 513 sec
lola: memory limit: 32 pages
lola: FINISHED task # 90 (type EXCL) for StigmergyElection-PT-07a-ReachabilityCardinality-01
lola: result : true
lola: markings : 124
lola: fired transitions : 206
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 126 (type EXCL) for 6 StigmergyElection-PT-07a-ReachabilityCardinality-02
lola: time limit : 599 sec
lola: memory limit: 32 pages
lola: FINISHED task # 126 (type EXCL) for StigmergyElection-PT-07a-ReachabilityCardinality-02
lola: result : true
lola: markings : 116
lola: fired transitions : 172
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 132 (type EXCL) for 45 StigmergyElection-PT-07a-ReachabilityCardinality-15
lola: time limit : 719 sec
lola: memory limit: 32 pages
lola: FINISHED task # 132 (type EXCL) for StigmergyElection-PT-07a-ReachabilityCardinality-15
lola: result : false
lola: markings : 702
lola: fired transitions : 1057
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 98 (type EXCL) for 36 StigmergyElection-PT-07a-ReachabilityCardinality-12
lola: time limit : 899 sec
lola: memory limit: 32 pages
lola: FINISHED task # 108 (type FNDP) for StigmergyElection-PT-07a-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 13841
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 101 (type FNDP) for 12 StigmergyElection-PT-07a-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: warning, failure of lp_solve (at job 255)
lola: FINISHED task # 98 (type EXCL) for StigmergyElection-PT-07a-ReachabilityCardinality-12
lola: result : false
lola: markings : 578
lola: fired transitions : 926
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 105 (type EXCL) for 12 StigmergyElection-PT-07a-ReachabilityCardinality-04
lola: time limit : 1798 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EQUN) for StigmergyElection-PT-07a-ReachabilityCardinality-05
lola: result : false
lola: FINISHED task # 105 (type EXCL) for StigmergyElection-PT-07a-ReachabilityCardinality-04
lola: result : false
lola: markings : 1155
lola: fired transitions : 1739
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 101 (type FNDP) for StigmergyElection-PT-07a-ReachabilityCardinality-04 (obsolete)
lola: LAUNCH task # 147 (type EXCL) for 24 StigmergyElection-PT-07a-ReachabilityCardinality-08
lola: time limit : 3596 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 146 (type SRCH) for 24 StigmergyElection-PT-07a-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 101 (type FNDP) for StigmergyElection-PT-07a-ReachabilityCardinality-04
lola: result : unknown
lola: fired transitions : 16990
lola: tried executions : 24
lola: time used : 1.000000
lola: memory pages used : 0
lola: FINISHED task # 147 (type EXCL) for StigmergyElection-PT-07a-ReachabilityCardinality-08
lola: result : false
lola: markings : 165
lola: fired transitions : 245
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 120 (type FNDP) for StigmergyElection-PT-07a-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 137 (type EQUN) for StigmergyElection-PT-07a-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 146 (type SRCH) for StigmergyElection-PT-07a-ReachabilityCardinality-08 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyElection-PT-07a-ReachabilityCardinality-00: AG true tandem / relaxed
StigmergyElection-PT-07a-ReachabilityCardinality-01: AG false tandem / relaxed
StigmergyElection-PT-07a-ReachabilityCardinality-02: EF true tandem / relaxed
StigmergyElection-PT-07a-ReachabilityCardinality-03: AG false tandem / relaxed
StigmergyElection-PT-07a-ReachabilityCardinality-04: EF false tandem / relaxed
StigmergyElection-PT-07a-ReachabilityCardinality-05: AG true tandem / insertion
StigmergyElection-PT-07a-ReachabilityCardinality-06: AG false tandem / relaxed
StigmergyElection-PT-07a-ReachabilityCardinality-07: EF true tandem / relaxed
StigmergyElection-PT-07a-ReachabilityCardinality-08: AG true tandem / relaxed
StigmergyElection-PT-07a-ReachabilityCardinality-09: AG true tandem / insertion
StigmergyElection-PT-07a-ReachabilityCardinality-10: AG true tandem / insertion
StigmergyElection-PT-07a-ReachabilityCardinality-11: AG false findpath
StigmergyElection-PT-07a-ReachabilityCardinality-12: AG true tandem / relaxed
StigmergyElection-PT-07a-ReachabilityCardinality-13: EF false tandem / relaxed
StigmergyElection-PT-07a-ReachabilityCardinality-14: AG false tandem / relaxed
StigmergyElection-PT-07a-ReachabilityCardinality-15: EF false tandem / relaxed
Time elapsed: 4 secs. Pages in use: 2
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="StigmergyElection-PT-07a"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is StigmergyElection-PT-07a, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912647600638"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/StigmergyElection-PT-07a.tgz
mv StigmergyElection-PT-07a execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;