Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r455-smll-167912647100218.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmartHome-PT-09, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912647100218
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 444K
-rw-r--r-- 1 mcc users 6.9K Feb 26 05:39 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Feb 26 05:39 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Feb 26 05:38 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 26 05:38 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 17:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 17:09 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 17:09 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 25 17:09 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.5K Feb 26 05:40 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 75K Feb 26 05:40 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.6K Feb 26 05:40 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 05:40 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 17:09 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 17:09 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 64K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmartHome-PT-09-CTLFireability-00
FORMULA_NAME SmartHome-PT-09-CTLFireability-01
FORMULA_NAME SmartHome-PT-09-CTLFireability-02
FORMULA_NAME SmartHome-PT-09-CTLFireability-03
FORMULA_NAME SmartHome-PT-09-CTLFireability-04
FORMULA_NAME SmartHome-PT-09-CTLFireability-05
FORMULA_NAME SmartHome-PT-09-CTLFireability-06
FORMULA_NAME SmartHome-PT-09-CTLFireability-07
FORMULA_NAME SmartHome-PT-09-CTLFireability-08
FORMULA_NAME SmartHome-PT-09-CTLFireability-09
FORMULA_NAME SmartHome-PT-09-CTLFireability-10
FORMULA_NAME SmartHome-PT-09-CTLFireability-11
FORMULA_NAME SmartHome-PT-09-CTLFireability-12
FORMULA_NAME SmartHome-PT-09-CTLFireability-13
FORMULA_NAME SmartHome-PT-09-CTLFireability-14
FORMULA_NAME SmartHome-PT-09-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679202962833

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmartHome-PT-09
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 05:16:06] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 05:16:06] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 05:16:06] [INFO ] Load time of PNML (sax parser for PT used): 85 ms
[2023-03-19 05:16:06] [INFO ] Transformed 253 places.
[2023-03-19 05:16:06] [INFO ] Transformed 293 transitions.
[2023-03-19 05:16:06] [INFO ] Found NUPN structural information;
[2023-03-19 05:16:06] [INFO ] Parsed PT model containing 253 places and 293 transitions and 664 arcs in 195 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 18 ms.
Deduced a syphon composed of 29 places in 4 ms
Reduce places removed 29 places and 30 transitions.
Initial state reduction rules removed 1 formulas.
FORMULA SmartHome-PT-09-CTLFireability-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 73 out of 224 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 224/224 places, 263/263 transitions.
Reduce places removed 7 places and 0 transitions.
Iterating post reduction 0 with 7 rules applied. Total rules applied 7 place count 217 transition count 263
Discarding 44 places :
Symmetric choice reduction at 1 with 44 rule applications. Total rules 51 place count 173 transition count 219
Iterating global reduction 1 with 44 rules applied. Total rules applied 95 place count 173 transition count 219
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 98 place count 173 transition count 216
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 102 place count 169 transition count 212
Iterating global reduction 2 with 4 rules applied. Total rules applied 106 place count 169 transition count 212
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 108 place count 167 transition count 210
Iterating global reduction 2 with 2 rules applied. Total rules applied 110 place count 167 transition count 210
Applied a total of 110 rules in 61 ms. Remains 167 /224 variables (removed 57) and now considering 210/263 (removed 53) transitions.
// Phase 1: matrix 210 rows 167 cols
[2023-03-19 05:16:06] [INFO ] Computed 3 place invariants in 29 ms
[2023-03-19 05:16:07] [INFO ] Implicit Places using invariants in 363 ms returned []
[2023-03-19 05:16:07] [INFO ] Invariant cache hit.
[2023-03-19 05:16:07] [INFO ] Implicit Places using invariants and state equation in 266 ms returned []
Implicit Place search using SMT with State Equation took 674 ms to find 0 implicit places.
[2023-03-19 05:16:07] [INFO ] Invariant cache hit.
[2023-03-19 05:16:07] [INFO ] Dead Transitions using invariants and state equation in 366 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 167/224 places, 210/263 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1102 ms. Remains : 167/224 places, 210/263 transitions.
Support contains 73 out of 167 places after structural reductions.
[2023-03-19 05:16:08] [INFO ] Flatten gal took : 92 ms
[2023-03-19 05:16:08] [INFO ] Flatten gal took : 33 ms
[2023-03-19 05:16:08] [INFO ] Input system was already deterministic with 210 transitions.
Support contains 71 out of 167 places (down from 73) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 63 resets, run finished after 869 ms. (steps per millisecond=11 ) properties (out of 61) seen :56
Incomplete Best-First random walk after 10001 steps, including 10 resets, run finished after 70 ms. (steps per millisecond=142 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 11 resets, run finished after 53 ms. (steps per millisecond=188 ) properties (out of 5) seen :1
Incomplete Best-First random walk after 10001 steps, including 9 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 6 resets, run finished after 35 ms. (steps per millisecond=285 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 7 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 4) seen :0
Running SMT prover for 4 properties.
[2023-03-19 05:16:09] [INFO ] Invariant cache hit.
[2023-03-19 05:16:09] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 05:16:09] [INFO ] [Real]Absence check using 2 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-19 05:16:09] [INFO ] After 120ms SMT Verify possible using state equation in real domain returned unsat :2 sat :1 real:1
[2023-03-19 05:16:09] [INFO ] After 148ms SMT Verify possible using trap constraints in real domain returned unsat :2 sat :0 real:2
[2023-03-19 05:16:09] [INFO ] After 269ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0 real:2
[2023-03-19 05:16:09] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 05:16:09] [INFO ] [Nat]Absence check using 2 positive and 1 generalized place invariants in 2 ms returned sat
[2023-03-19 05:16:10] [INFO ] After 141ms SMT Verify possible using state equation in natural domain returned unsat :2 sat :2
[2023-03-19 05:16:10] [INFO ] After 196ms SMT Verify possible using trap constraints in natural domain returned unsat :2 sat :2
Attempting to minimize the solution found.
Minimization took 36 ms.
[2023-03-19 05:16:10] [INFO ] After 322ms SMT Verify possible using all constraints in natural domain returned unsat :2 sat :2
Fused 4 Parikh solutions to 2 different solutions.
Parikh walk visited 0 properties in 10 ms.
Support contains 3 out of 167 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 167/167 places, 210/210 transitions.
Graph (trivial) has 161 edges and 167 vertex of which 67 / 167 are part of one of the 5 SCC in 9 ms
Free SCC test removed 62 places
Drop transitions removed 89 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 90 transitions.
Drop transitions removed 39 transitions
Trivial Post-agglo rules discarded 39 transitions
Performed 39 trivial Post agglomeration. Transition count delta: 39
Iterating post reduction 0 with 39 rules applied. Total rules applied 40 place count 105 transition count 81
Reduce places removed 39 places and 0 transitions.
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded 6 transitions
Performed 6 trivial Post agglomeration. Transition count delta: 6
Iterating post reduction 1 with 51 rules applied. Total rules applied 91 place count 66 transition count 69
Reduce places removed 6 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 2 with 8 rules applied. Total rules applied 99 place count 60 transition count 67
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 100 place count 59 transition count 67
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 3 Pre rules applied. Total rules applied 100 place count 59 transition count 64
Deduced a syphon composed of 3 places in 8 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 4 with 6 rules applied. Total rules applied 106 place count 56 transition count 64
Discarding 12 places :
Symmetric choice reduction at 4 with 12 rule applications. Total rules 118 place count 44 transition count 52
Iterating global reduction 4 with 12 rules applied. Total rules applied 130 place count 44 transition count 52
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 4 with 4 rules applied. Total rules applied 134 place count 44 transition count 48
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 1 Pre rules applied. Total rules applied 134 place count 44 transition count 47
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 136 place count 43 transition count 47
Performed 17 Post agglomeration using F-continuation condition.Transition count delta: 17
Deduced a syphon composed of 17 places in 0 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 5 with 34 rules applied. Total rules applied 170 place count 26 transition count 30
Drop transitions removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 5 with 8 rules applied. Total rules applied 178 place count 26 transition count 22
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 6 with 2 rules applied. Total rules applied 180 place count 26 transition count 20
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 6 with 2 rules applied. Total rules applied 182 place count 24 transition count 20
Partial Free-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 7 with 1 rules applied. Total rules applied 183 place count 24 transition count 20
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 7 with 1 rules applied. Total rules applied 184 place count 23 transition count 19
Reduce places removed 4 places and 0 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 7 with 7 rules applied. Total rules applied 191 place count 19 transition count 16
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 8 with 3 rules applied. Total rules applied 194 place count 16 transition count 16
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 9 with 3 Pre rules applied. Total rules applied 194 place count 16 transition count 13
Deduced a syphon composed of 3 places in 0 ms
Ensure Unique test removed 1 places
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 9 with 7 rules applied. Total rules applied 201 place count 12 transition count 13
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 9 with 1 rules applied. Total rules applied 202 place count 12 transition count 12
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 10 with 1 rules applied. Total rules applied 203 place count 11 transition count 12
Free-agglomeration rule applied 1 times.
Iterating global reduction 11 with 1 rules applied. Total rules applied 204 place count 11 transition count 11
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 11 with 1 rules applied. Total rules applied 205 place count 10 transition count 11
Partial Free-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 12 with 1 rules applied. Total rules applied 206 place count 10 transition count 11
Applied a total of 206 rules in 78 ms. Remains 10 /167 variables (removed 157) and now considering 11/210 (removed 199) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 78 ms. Remains : 10/167 places, 11/210 transitions.
Finished random walk after 22 steps, including 2 resets, run visited all 2 properties in 1 ms. (steps per millisecond=22 )
Successfully simplified 2 atomic propositions for a total of 15 simplifications.
FORMULA SmartHome-PT-09-CTLFireability-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 05:16:10] [INFO ] Flatten gal took : 21 ms
[2023-03-19 05:16:10] [INFO ] Flatten gal took : 20 ms
[2023-03-19 05:16:10] [INFO ] Input system was already deterministic with 210 transitions.
Support contains 66 out of 167 places (down from 68) after GAL structural reductions.
Computed a total of 48 stabilizing places and 48 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 167/167 places, 210/210 transitions.
Graph (trivial) has 163 edges and 167 vertex of which 63 / 167 are part of one of the 6 SCC in 0 ms
Free SCC test removed 57 places
Ensure Unique test removed 74 transitions
Reduce isomorphic transitions removed 74 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 42 transitions
Trivial Post-agglo rules discarded 42 transitions
Performed 42 trivial Post agglomeration. Transition count delta: 42
Iterating post reduction 0 with 42 rules applied. Total rules applied 43 place count 109 transition count 93
Reduce places removed 42 places and 0 transitions.
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 1 with 51 rules applied. Total rules applied 94 place count 67 transition count 84
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 2 with 4 rules applied. Total rules applied 98 place count 63 transition count 84
Performed 5 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 5 Pre rules applied. Total rules applied 98 place count 63 transition count 79
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 3 with 10 rules applied. Total rules applied 108 place count 58 transition count 79
Discarding 12 places :
Symmetric choice reduction at 3 with 12 rule applications. Total rules 120 place count 46 transition count 67
Iterating global reduction 3 with 12 rules applied. Total rules applied 132 place count 46 transition count 67
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 3 with 3 rules applied. Total rules applied 135 place count 46 transition count 64
Performed 15 Post agglomeration using F-continuation condition.Transition count delta: 15
Deduced a syphon composed of 15 places in 0 ms
Reduce places removed 15 places and 0 transitions.
Iterating global reduction 4 with 30 rules applied. Total rules applied 165 place count 31 transition count 49
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 166 place count 31 transition count 48
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 168 place count 30 transition count 47
Drop transitions removed 10 transitions
Redundant transition composition rules discarded 10 transitions
Iterating global reduction 5 with 10 rules applied. Total rules applied 178 place count 30 transition count 37
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 5 with 2 rules applied. Total rules applied 180 place count 28 transition count 37
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 1 Pre rules applied. Total rules applied 180 place count 28 transition count 36
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 6 with 2 rules applied. Total rules applied 182 place count 27 transition count 36
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 6 with 1 rules applied. Total rules applied 183 place count 27 transition count 36
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 6 with 1 rules applied. Total rules applied 184 place count 26 transition count 35
Applied a total of 184 rules in 40 ms. Remains 26 /167 variables (removed 141) and now considering 35/210 (removed 175) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 41 ms. Remains : 26/167 places, 35/210 transitions.
[2023-03-19 05:16:10] [INFO ] Flatten gal took : 4 ms
[2023-03-19 05:16:10] [INFO ] Flatten gal took : 4 ms
[2023-03-19 05:16:10] [INFO ] Input system was already deterministic with 35 transitions.
Starting structural reductions in LTL mode, iteration 0 : 167/167 places, 210/210 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 143 transition count 186
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 143 transition count 186
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 51 place count 143 transition count 183
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 61 place count 133 transition count 173
Iterating global reduction 1 with 10 rules applied. Total rules applied 71 place count 133 transition count 173
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 75 place count 129 transition count 169
Iterating global reduction 1 with 4 rules applied. Total rules applied 79 place count 129 transition count 169
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 80 place count 129 transition count 168
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 82 place count 127 transition count 166
Iterating global reduction 2 with 2 rules applied. Total rules applied 84 place count 127 transition count 166
Applied a total of 84 rules in 27 ms. Remains 127 /167 variables (removed 40) and now considering 166/210 (removed 44) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 27 ms. Remains : 127/167 places, 166/210 transitions.
[2023-03-19 05:16:10] [INFO ] Flatten gal took : 16 ms
[2023-03-19 05:16:10] [INFO ] Flatten gal took : 16 ms
[2023-03-19 05:16:10] [INFO ] Input system was already deterministic with 166 transitions.
Starting structural reductions in LTL mode, iteration 0 : 167/167 places, 210/210 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 143 transition count 186
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 143 transition count 186
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 51 place count 143 transition count 183
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 61 place count 133 transition count 173
Iterating global reduction 1 with 10 rules applied. Total rules applied 71 place count 133 transition count 173
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 76 place count 128 transition count 168
Iterating global reduction 1 with 5 rules applied. Total rules applied 81 place count 128 transition count 168
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 82 place count 128 transition count 167
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 84 place count 126 transition count 165
Iterating global reduction 2 with 2 rules applied. Total rules applied 86 place count 126 transition count 165
Applied a total of 86 rules in 22 ms. Remains 126 /167 variables (removed 41) and now considering 165/210 (removed 45) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 22 ms. Remains : 126/167 places, 165/210 transitions.
[2023-03-19 05:16:10] [INFO ] Flatten gal took : 17 ms
[2023-03-19 05:16:10] [INFO ] Flatten gal took : 17 ms
[2023-03-19 05:16:10] [INFO ] Input system was already deterministic with 165 transitions.
Starting structural reductions in LTL mode, iteration 0 : 167/167 places, 210/210 transitions.
Discarding 25 places :
Symmetric choice reduction at 0 with 25 rule applications. Total rules 25 place count 142 transition count 185
Iterating global reduction 0 with 25 rules applied. Total rules applied 50 place count 142 transition count 185
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 53 place count 142 transition count 182
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 62 place count 133 transition count 173
Iterating global reduction 1 with 9 rules applied. Total rules applied 71 place count 133 transition count 173
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 76 place count 128 transition count 168
Iterating global reduction 1 with 5 rules applied. Total rules applied 81 place count 128 transition count 168
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 82 place count 128 transition count 167
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 83 place count 127 transition count 166
Iterating global reduction 2 with 1 rules applied. Total rules applied 84 place count 127 transition count 166
Applied a total of 84 rules in 19 ms. Remains 127 /167 variables (removed 40) and now considering 166/210 (removed 44) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 19 ms. Remains : 127/167 places, 166/210 transitions.
[2023-03-19 05:16:10] [INFO ] Flatten gal took : 15 ms
[2023-03-19 05:16:10] [INFO ] Flatten gal took : 19 ms
[2023-03-19 05:16:10] [INFO ] Input system was already deterministic with 166 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 167/167 places, 210/210 transitions.
Graph (trivial) has 157 edges and 167 vertex of which 50 / 167 are part of one of the 6 SCC in 1 ms
Free SCC test removed 44 places
Ensure Unique test removed 57 transitions
Reduce isomorphic transitions removed 57 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 43 transitions
Trivial Post-agglo rules discarded 43 transitions
Performed 43 trivial Post agglomeration. Transition count delta: 43
Iterating post reduction 0 with 43 rules applied. Total rules applied 44 place count 122 transition count 109
Reduce places removed 43 places and 0 transitions.
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 1 with 56 rules applied. Total rules applied 100 place count 79 transition count 96
Reduce places removed 7 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 9 rules applied. Total rules applied 109 place count 72 transition count 94
Reduce places removed 1 places and 0 transitions.
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Iterating post reduction 3 with 4 rules applied. Total rules applied 113 place count 71 transition count 91
Reduce places removed 3 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 4 with 5 rules applied. Total rules applied 118 place count 68 transition count 89
Performed 7 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 7 Pre rules applied. Total rules applied 118 place count 68 transition count 82
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 5 with 14 rules applied. Total rules applied 132 place count 61 transition count 82
Discarding 9 places :
Symmetric choice reduction at 5 with 9 rule applications. Total rules 141 place count 52 transition count 73
Iterating global reduction 5 with 9 rules applied. Total rules applied 150 place count 52 transition count 73
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 5 with 3 rules applied. Total rules applied 153 place count 52 transition count 70
Performed 17 Post agglomeration using F-continuation condition.Transition count delta: 17
Deduced a syphon composed of 17 places in 0 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 6 with 34 rules applied. Total rules applied 187 place count 35 transition count 53
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 6 with 3 rules applied. Total rules applied 190 place count 35 transition count 50
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 191 place count 34 transition count 50
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 8 with 2 rules applied. Total rules applied 193 place count 33 transition count 49
Drop transitions removed 8 transitions
Redundant transition composition rules discarded 8 transitions
Iterating global reduction 8 with 8 rules applied. Total rules applied 201 place count 33 transition count 41
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 8 with 1 rules applied. Total rules applied 202 place count 32 transition count 41
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 9 with 1 Pre rules applied. Total rules applied 202 place count 32 transition count 40
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 9 with 2 rules applied. Total rules applied 204 place count 31 transition count 40
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 9 with 1 rules applied. Total rules applied 205 place count 30 transition count 39
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 9 with 1 rules applied. Total rules applied 206 place count 29 transition count 39
Applied a total of 206 rules in 39 ms. Remains 29 /167 variables (removed 138) and now considering 39/210 (removed 171) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 41 ms. Remains : 29/167 places, 39/210 transitions.
[2023-03-19 05:16:10] [INFO ] Flatten gal took : 3 ms
[2023-03-19 05:16:10] [INFO ] Flatten gal took : 4 ms
[2023-03-19 05:16:10] [INFO ] Input system was already deterministic with 39 transitions.
Starting structural reductions in LTL mode, iteration 0 : 167/167 places, 210/210 transitions.
Discarding 20 places :
Symmetric choice reduction at 0 with 20 rule applications. Total rules 20 place count 147 transition count 190
Iterating global reduction 0 with 20 rules applied. Total rules applied 40 place count 147 transition count 190
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 42 place count 147 transition count 188
Discarding 7 places :
Symmetric choice reduction at 1 with 7 rule applications. Total rules 49 place count 140 transition count 181
Iterating global reduction 1 with 7 rules applied. Total rules applied 56 place count 140 transition count 181
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 59 place count 137 transition count 178
Iterating global reduction 1 with 3 rules applied. Total rules applied 62 place count 137 transition count 178
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 63 place count 137 transition count 177
Applied a total of 63 rules in 16 ms. Remains 137 /167 variables (removed 30) and now considering 177/210 (removed 33) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16 ms. Remains : 137/167 places, 177/210 transitions.
[2023-03-19 05:16:10] [INFO ] Flatten gal took : 16 ms
[2023-03-19 05:16:10] [INFO ] Flatten gal took : 15 ms
[2023-03-19 05:16:10] [INFO ] Input system was already deterministic with 177 transitions.
Starting structural reductions in LTL mode, iteration 0 : 167/167 places, 210/210 transitions.
Discarding 24 places :
Symmetric choice reduction at 0 with 24 rule applications. Total rules 24 place count 143 transition count 186
Iterating global reduction 0 with 24 rules applied. Total rules applied 48 place count 143 transition count 186
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 51 place count 143 transition count 183
Discarding 11 places :
Symmetric choice reduction at 1 with 11 rule applications. Total rules 62 place count 132 transition count 172
Iterating global reduction 1 with 11 rules applied. Total rules applied 73 place count 132 transition count 172
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 79 place count 126 transition count 166
Iterating global reduction 1 with 6 rules applied. Total rules applied 85 place count 126 transition count 166
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 86 place count 126 transition count 165
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 88 place count 124 transition count 163
Iterating global reduction 2 with 2 rules applied. Total rules applied 90 place count 124 transition count 163
Applied a total of 90 rules in 19 ms. Remains 124 /167 variables (removed 43) and now considering 163/210 (removed 47) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 19 ms. Remains : 124/167 places, 163/210 transitions.
[2023-03-19 05:16:10] [INFO ] Flatten gal took : 13 ms
[2023-03-19 05:16:11] [INFO ] Flatten gal took : 13 ms
[2023-03-19 05:16:11] [INFO ] Input system was already deterministic with 163 transitions.
Starting structural reductions in LTL mode, iteration 0 : 167/167 places, 210/210 transitions.
Discarding 25 places :
Symmetric choice reduction at 0 with 25 rule applications. Total rules 25 place count 142 transition count 185
Iterating global reduction 0 with 25 rules applied. Total rules applied 50 place count 142 transition count 185
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 53 place count 142 transition count 182
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 63 place count 132 transition count 172
Iterating global reduction 1 with 10 rules applied. Total rules applied 73 place count 132 transition count 172
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 79 place count 126 transition count 166
Iterating global reduction 1 with 6 rules applied. Total rules applied 85 place count 126 transition count 166
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 86 place count 126 transition count 165
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 88 place count 124 transition count 163
Iterating global reduction 2 with 2 rules applied. Total rules applied 90 place count 124 transition count 163
Applied a total of 90 rules in 12 ms. Remains 124 /167 variables (removed 43) and now considering 163/210 (removed 47) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 124/167 places, 163/210 transitions.
[2023-03-19 05:16:11] [INFO ] Flatten gal took : 8 ms
[2023-03-19 05:16:11] [INFO ] Flatten gal took : 8 ms
[2023-03-19 05:16:11] [INFO ] Input system was already deterministic with 163 transitions.
Starting structural reductions in LTL mode, iteration 0 : 167/167 places, 210/210 transitions.
Discarding 25 places :
Symmetric choice reduction at 0 with 25 rule applications. Total rules 25 place count 142 transition count 185
Iterating global reduction 0 with 25 rules applied. Total rules applied 50 place count 142 transition count 185
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 52 place count 142 transition count 183
Discarding 11 places :
Symmetric choice reduction at 1 with 11 rule applications. Total rules 63 place count 131 transition count 172
Iterating global reduction 1 with 11 rules applied. Total rules applied 74 place count 131 transition count 172
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 80 place count 125 transition count 166
Iterating global reduction 1 with 6 rules applied. Total rules applied 86 place count 125 transition count 166
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 87 place count 125 transition count 165
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 89 place count 123 transition count 163
Iterating global reduction 2 with 2 rules applied. Total rules applied 91 place count 123 transition count 163
Applied a total of 91 rules in 11 ms. Remains 123 /167 variables (removed 44) and now considering 163/210 (removed 47) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 123/167 places, 163/210 transitions.
[2023-03-19 05:16:11] [INFO ] Flatten gal took : 7 ms
[2023-03-19 05:16:11] [INFO ] Flatten gal took : 8 ms
[2023-03-19 05:16:11] [INFO ] Input system was already deterministic with 163 transitions.
Starting structural reductions in LTL mode, iteration 0 : 167/167 places, 210/210 transitions.
Discarding 23 places :
Symmetric choice reduction at 0 with 23 rule applications. Total rules 23 place count 144 transition count 187
Iterating global reduction 0 with 23 rules applied. Total rules applied 46 place count 144 transition count 187
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 48 place count 144 transition count 185
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 57 place count 135 transition count 176
Iterating global reduction 1 with 9 rules applied. Total rules applied 66 place count 135 transition count 176
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 70 place count 131 transition count 172
Iterating global reduction 1 with 4 rules applied. Total rules applied 74 place count 131 transition count 172
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 75 place count 131 transition count 171
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 77 place count 129 transition count 169
Iterating global reduction 2 with 2 rules applied. Total rules applied 79 place count 129 transition count 169
Applied a total of 79 rules in 12 ms. Remains 129 /167 variables (removed 38) and now considering 169/210 (removed 41) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 129/167 places, 169/210 transitions.
[2023-03-19 05:16:11] [INFO ] Flatten gal took : 8 ms
[2023-03-19 05:16:11] [INFO ] Flatten gal took : 9 ms
[2023-03-19 05:16:11] [INFO ] Input system was already deterministic with 169 transitions.
Starting structural reductions in LTL mode, iteration 0 : 167/167 places, 210/210 transitions.
Discarding 25 places :
Symmetric choice reduction at 0 with 25 rule applications. Total rules 25 place count 142 transition count 185
Iterating global reduction 0 with 25 rules applied. Total rules applied 50 place count 142 transition count 185
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 53 place count 142 transition count 182
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 63 place count 132 transition count 172
Iterating global reduction 1 with 10 rules applied. Total rules applied 73 place count 132 transition count 172
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 77 place count 128 transition count 168
Iterating global reduction 1 with 4 rules applied. Total rules applied 81 place count 128 transition count 168
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 82 place count 128 transition count 167
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 83 place count 127 transition count 166
Iterating global reduction 2 with 1 rules applied. Total rules applied 84 place count 127 transition count 166
Applied a total of 84 rules in 11 ms. Remains 127 /167 variables (removed 40) and now considering 166/210 (removed 44) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 127/167 places, 166/210 transitions.
[2023-03-19 05:16:11] [INFO ] Flatten gal took : 9 ms
[2023-03-19 05:16:11] [INFO ] Flatten gal took : 16 ms
[2023-03-19 05:16:11] [INFO ] Input system was already deterministic with 166 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 167/167 places, 210/210 transitions.
Graph (trivial) has 149 edges and 167 vertex of which 51 / 167 are part of one of the 4 SCC in 1 ms
Free SCC test removed 47 places
Ensure Unique test removed 60 transitions
Reduce isomorphic transitions removed 60 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 44 transitions
Trivial Post-agglo rules discarded 44 transitions
Performed 44 trivial Post agglomeration. Transition count delta: 44
Iterating post reduction 0 with 44 rules applied. Total rules applied 45 place count 119 transition count 105
Reduce places removed 44 places and 0 transitions.
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 1 with 54 rules applied. Total rules applied 99 place count 75 transition count 95
Reduce places removed 5 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 2 with 8 rules applied. Total rules applied 107 place count 70 transition count 92
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 3 with 3 rules applied. Total rules applied 110 place count 68 transition count 91
Performed 6 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 6 Pre rules applied. Total rules applied 110 place count 68 transition count 85
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 4 with 12 rules applied. Total rules applied 122 place count 62 transition count 85
Discarding 13 places :
Symmetric choice reduction at 4 with 13 rule applications. Total rules 135 place count 49 transition count 72
Iterating global reduction 4 with 13 rules applied. Total rules applied 148 place count 49 transition count 72
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 151 place count 49 transition count 69
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules 152 place count 48 transition count 67
Iterating global reduction 5 with 1 rules applied. Total rules applied 153 place count 48 transition count 67
Performed 14 Post agglomeration using F-continuation condition.Transition count delta: 14
Deduced a syphon composed of 14 places in 0 ms
Reduce places removed 14 places and 0 transitions.
Iterating global reduction 5 with 28 rules applied. Total rules applied 181 place count 34 transition count 53
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 182 place count 34 transition count 52
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 6 with 2 rules applied. Total rules applied 184 place count 33 transition count 51
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 185 place count 33 transition count 50
Drop transitions removed 5 transitions
Redundant transition composition rules discarded 5 transitions
Iterating global reduction 7 with 5 rules applied. Total rules applied 190 place count 33 transition count 45
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 191 place count 32 transition count 45
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 8 with 1 Pre rules applied. Total rules applied 191 place count 32 transition count 44
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 8 with 2 rules applied. Total rules applied 193 place count 31 transition count 44
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 8 with 1 rules applied. Total rules applied 194 place count 31 transition count 44
Applied a total of 194 rules in 24 ms. Remains 31 /167 variables (removed 136) and now considering 44/210 (removed 166) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 24 ms. Remains : 31/167 places, 44/210 transitions.
[2023-03-19 05:16:11] [INFO ] Flatten gal took : 2 ms
[2023-03-19 05:16:11] [INFO ] Flatten gal took : 3 ms
[2023-03-19 05:16:11] [INFO ] Input system was already deterministic with 44 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 167/167 places, 210/210 transitions.
Graph (trivial) has 147 edges and 167 vertex of which 33 / 167 are part of one of the 3 SCC in 0 ms
Free SCC test removed 30 places
Ensure Unique test removed 38 transitions
Reduce isomorphic transitions removed 38 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 53 transitions
Trivial Post-agglo rules discarded 53 transitions
Performed 53 trivial Post agglomeration. Transition count delta: 53
Iterating post reduction 0 with 53 rules applied. Total rules applied 54 place count 136 transition count 118
Reduce places removed 53 places and 0 transitions.
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Drop transitions removed 10 transitions
Trivial Post-agglo rules discarded 10 transitions
Performed 10 trivial Post agglomeration. Transition count delta: 10
Iterating post reduction 1 with 70 rules applied. Total rules applied 124 place count 83 transition count 101
Reduce places removed 10 places and 0 transitions.
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 2 with 15 rules applied. Total rules applied 139 place count 73 transition count 96
Reduce places removed 2 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 3 with 4 rules applied. Total rules applied 143 place count 71 transition count 94
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 4 with 2 rules applied. Total rules applied 145 place count 69 transition count 94
Performed 6 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 6 Pre rules applied. Total rules applied 145 place count 69 transition count 88
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 5 with 12 rules applied. Total rules applied 157 place count 63 transition count 88
Discarding 14 places :
Symmetric choice reduction at 5 with 14 rule applications. Total rules 171 place count 49 transition count 73
Iterating global reduction 5 with 14 rules applied. Total rules applied 185 place count 49 transition count 73
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 5 with 5 rules applied. Total rules applied 190 place count 49 transition count 68
Performed 14 Post agglomeration using F-continuation condition.Transition count delta: 14
Deduced a syphon composed of 14 places in 0 ms
Reduce places removed 14 places and 0 transitions.
Iterating global reduction 6 with 28 rules applied. Total rules applied 218 place count 35 transition count 54
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 219 place count 35 transition count 53
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 7 with 2 rules applied. Total rules applied 221 place count 34 transition count 52
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 222 place count 34 transition count 51
Drop transitions removed 5 transitions
Redundant transition composition rules discarded 5 transitions
Iterating global reduction 8 with 5 rules applied. Total rules applied 227 place count 34 transition count 46
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 8 with 1 rules applied. Total rules applied 228 place count 33 transition count 46
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 9 with 1 Pre rules applied. Total rules applied 228 place count 33 transition count 45
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 9 with 2 rules applied. Total rules applied 230 place count 32 transition count 45
Applied a total of 230 rules in 20 ms. Remains 32 /167 variables (removed 135) and now considering 45/210 (removed 165) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 20 ms. Remains : 32/167 places, 45/210 transitions.
[2023-03-19 05:16:11] [INFO ] Flatten gal took : 3 ms
[2023-03-19 05:16:11] [INFO ] Flatten gal took : 4 ms
[2023-03-19 05:16:11] [INFO ] Input system was already deterministic with 45 transitions.
Starting structural reductions in LTL mode, iteration 0 : 167/167 places, 210/210 transitions.
Discarding 25 places :
Symmetric choice reduction at 0 with 25 rule applications. Total rules 25 place count 142 transition count 185
Iterating global reduction 0 with 25 rules applied. Total rules applied 50 place count 142 transition count 185
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 53 place count 142 transition count 182
Discarding 11 places :
Symmetric choice reduction at 1 with 11 rule applications. Total rules 64 place count 131 transition count 171
Iterating global reduction 1 with 11 rules applied. Total rules applied 75 place count 131 transition count 171
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 81 place count 125 transition count 165
Iterating global reduction 1 with 6 rules applied. Total rules applied 87 place count 125 transition count 165
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 88 place count 125 transition count 164
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 90 place count 123 transition count 162
Iterating global reduction 2 with 2 rules applied. Total rules applied 92 place count 123 transition count 162
Applied a total of 92 rules in 12 ms. Remains 123 /167 variables (removed 44) and now considering 162/210 (removed 48) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 123/167 places, 162/210 transitions.
[2023-03-19 05:16:11] [INFO ] Flatten gal took : 8 ms
[2023-03-19 05:16:11] [INFO ] Flatten gal took : 9 ms
[2023-03-19 05:16:11] [INFO ] Input system was already deterministic with 162 transitions.
[2023-03-19 05:16:11] [INFO ] Flatten gal took : 10 ms
[2023-03-19 05:16:11] [INFO ] Flatten gal took : 9 ms
[2023-03-19 05:16:11] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-19 05:16:11] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 167 places, 210 transitions and 473 arcs took 2 ms.
Total runtime 4948 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmartHome-PT-09
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA SmartHome-PT-09-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-09-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-09-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-09-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-09-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-09-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-09-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-09-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-09-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-09-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-09-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-09-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679203213418

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
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lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 30 (type EXCL) for 29 SmartHome-PT-09-CTLFireability-08
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:809
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 50 (type FNDP) for 3 SmartHome-PT-09-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type EQUN) for 3 SmartHome-PT-09-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 53 (type SRCH) for 3 SmartHome-PT-09-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 50 (type FNDP) for SmartHome-PT-09-CTLFireability-01
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 51 (type EQUN) for SmartHome-PT-09-CTLFireability-01 (obsolete)
lola: CANCELED task # 53 (type SRCH) for SmartHome-PT-09-CTLFireability-01 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
sara: try reading problem file /home/mcc/execution/375/CTLFireability-51.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
sara: place or transition ordering is non-deterministic

lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 51 (type EQUN) for SmartHome-PT-09-CTLFireability-01
lola: result : true
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30 CTL EXCL 5/257 4/32 SmartHome-PT-09-CTLFireability-08 697626 m, 139525 m/sec, 2633556 t fired, .

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30 CTL EXCL 10/257 7/32 SmartHome-PT-09-CTLFireability-08 1389458 m, 138366 m/sec, 5513760 t fired, .

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30 CTL EXCL 15/257 10/32 SmartHome-PT-09-CTLFireability-08 2168190 m, 155746 m/sec, 8159310 t fired, .

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SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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SmartHome-PT-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-09-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
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SmartHome-PT-09-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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30 CTL EXCL 20/257 13/32 SmartHome-PT-09-CTLFireability-08 2713106 m, 108983 m/sec, 10750321 t fired, .

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SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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30 CTL EXCL 30/257 17/32 SmartHome-PT-09-CTLFireability-08 3725911 m, 111877 m/sec, 16127034 t fired, .

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30 CTL EXCL 35/257 20/32 SmartHome-PT-09-CTLFireability-08 4280139 m, 110845 m/sec, 18838768 t fired, .

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30 CTL EXCL 40/257 22/32 SmartHome-PT-09-CTLFireability-08 4799881 m, 103948 m/sec, 21577519 t fired, .

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SmartHome-PT-09-CTLFireability-01: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-09-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-09-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 55/257 28/32 SmartHome-PT-09-CTLFireability-08 6315174 m, 107418 m/sec, 29518263 t fired, .

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SmartHome-PT-09-CTLFireability-01: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-09-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-09-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 60/257 30/32 SmartHome-PT-09-CTLFireability-08 6701899 m, 77345 m/sec, 32131985 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-09-CTLFireability-01: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-09-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-09-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 66 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 48 (type EXCL) for 47 SmartHome-PT-09-CTLFireability-15
lola: time limit : 271 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for SmartHome-PT-09-CTLFireability-15
lola: result : false
lola: markings : 64
lola: fired transitions : 64
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 SmartHome-PT-09-CTLFireability-11
lola: time limit : 294 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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SmartHome-PT-09-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-09-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-09-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 5/294 2/32 SmartHome-PT-09-CTLFireability-11 240491 m, 48098 m/sec, 2353028 t fired, .

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SmartHome-PT-09-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-09-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-09-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 10/294 3/32 SmartHome-PT-09-CTLFireability-11 462641 m, 44430 m/sec, 4831433 t fired, .

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SmartHome-PT-09-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-09-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-09-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 15/294 4/32 SmartHome-PT-09-CTLFireability-11 673148 m, 42101 m/sec, 7279621 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-09-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-09-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 20/294 4/32 SmartHome-PT-09-CTLFireability-11 880515 m, 41473 m/sec, 9798754 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-09-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-09-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 25/294 6/32 SmartHome-PT-09-CTLFireability-11 1127550 m, 49407 m/sec, 12542666 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-09-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-09-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 30/294 6/32 SmartHome-PT-09-CTLFireability-11 1347893 m, 44068 m/sec, 15247357 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-09-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-09-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

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39 CTL EXCL 35/294 8/32 SmartHome-PT-09-CTLFireability-11 1604750 m, 51371 m/sec, 17878240 t fired, .

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SmartHome-PT-09-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-09-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

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39 CTL EXCL 40/294 9/32 SmartHome-PT-09-CTLFireability-11 1833286 m, 45707 m/sec, 20375053 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-09-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-09-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 45/294 10/32 SmartHome-PT-09-CTLFireability-11 2042252 m, 41793 m/sec, 22869124 t fired, .

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SmartHome-PT-09-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-09-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 50/294 11/32 SmartHome-PT-09-CTLFireability-11 2240839 m, 39717 m/sec, 25374789 t fired, .

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SmartHome-PT-09-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-09-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

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39 CTL EXCL 55/294 12/32 SmartHome-PT-09-CTLFireability-11 2463011 m, 44434 m/sec, 27865838 t fired, .

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SmartHome-PT-09-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-09-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

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39 CTL EXCL 60/294 13/32 SmartHome-PT-09-CTLFireability-11 2734916 m, 54381 m/sec, 30346408 t fired, .

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SmartHome-PT-09-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-09-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

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39 CTL EXCL 65/294 15/32 SmartHome-PT-09-CTLFireability-11 3100013 m, 73019 m/sec, 32747369 t fired, .

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SmartHome-PT-09-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmartHome-PT-09-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-09-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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39 CTL EXCL 70/294 16/32 SmartHome-PT-09-CTLFireability-11 3386917 m, 57380 m/sec, 35024740 t fired, .

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39 CTL EXCL 105/294 21/32 SmartHome-PT-09-CTLFireability-11 4589037 m, 16826 m/sec, 52209162 t fired, .

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39 CTL EXCL 110/294 22/32 SmartHome-PT-09-CTLFireability-11 4714850 m, 25162 m/sec, 54724132 t fired, .

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39 CTL EXCL 115/294 23/32 SmartHome-PT-09-CTLFireability-11 5076221 m, 72274 m/sec, 57125405 t fired, .

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39 CTL EXCL 125/294 25/32 SmartHome-PT-09-CTLFireability-11 5575550 m, 44389 m/sec, 61666309 t fired, .

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39 CTL EXCL 150/294 29/32 SmartHome-PT-09-CTLFireability-11 6439753 m, 21645 m/sec, 74008669 t fired, .

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39 CTL EXCL 155/294 29/32 SmartHome-PT-09-CTLFireability-11 6524500 m, 16949 m/sec, 76461906 t fired, .

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lola: LAUNCH task # 36 (type EXCL) for 35 SmartHome-PT-09-CTLFireability-10
lola: time limit : 305 sec
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lola: result : true
lola: markings : 8618
lola: fired transitions : 37776
lola: time used : 0.000000
lola: memory pages used : 1
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lola: result : false
lola: markings : 6886
lola: fired transitions : 10673
lola: time used : 0.000000
lola: memory pages used : 1
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lola: result : true
lola: markings : 187
lola: fired transitions : 237
lola: time used : 0.000000
lola: memory pages used : 1
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lola: result : false
lola: markings : 18
lola: fired transitions : 37
lola: time used : 0.000000
lola: memory pages used : 1
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lola: time limit : 479 sec
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lola: result : true
lola: markings : 664
lola: fired transitions : 794
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 15 (type EXCL) for 10 SmartHome-PT-09-CTLFireability-02
lola: time limit : 559 sec
lola: memory limit: 32 pages
lola: FINISHED task # 15 (type EXCL) for SmartHome-PT-09-CTLFireability-02
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
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lola: time limit : 671 sec
lola: memory limit: 32 pages
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lola: result : false
lola: markings : 60
lola: fired transitions : 113
lola: time used : 0.000000
lola: memory pages used : 1
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lola: result : true
lola: markings : 45
lola: fired transitions : 97
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 SmartHome-PT-09-CTLFireability-00
lola: time limit : 1119 sec
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lola: FINISHED task # 1 (type EXCL) for SmartHome-PT-09-CTLFireability-00
lola: result : false
lola: markings : 6144
lola: fired transitions : 37096
lola: time used : 0.000000
lola: memory pages used : 1
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lola: time limit : 1679 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for SmartHome-PT-09-CTLFireability-12
lola: result : true
lola: markings : 62
lola: fired transitions : 180
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 44 SmartHome-PT-09-CTLFireability-13
lola: time limit : 3359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for SmartHome-PT-09-CTLFireability-13
lola: result : true
lola: markings : 178
lola: fired transitions : 547
lola: time used : 0.000000
lola: memory pages used : 1
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SmartHome-PT-09-CTLFireability-00: CTL false CTL model checker
SmartHome-PT-09-CTLFireability-01: DISJ true findpath
SmartHome-PT-09-CTLFireability-02: DISJ false DISJ
SmartHome-PT-09-CTLFireability-03: CTL true CTL model checker
SmartHome-PT-09-CTLFireability-04: CTL true CTL model checker
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SmartHome-PT-09-CTLFireability-08: CTL unknown AGGR
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SmartHome-PT-09-CTLFireability-11: CTL unknown AGGR
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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmartHome-PT-09"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmartHome-PT-09, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912647100218"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmartHome-PT-09.tgz
mv SmartHome-PT-09 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;