Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r455-smll-167912647000178.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmartHome-PT-04, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912647000178
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 476K
-rw-r--r-- 1 mcc users 6.2K Feb 26 05:42 CTLCardinality.txt
-rw-r--r-- 1 mcc users 67K Feb 26 05:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Feb 26 05:41 CTLFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 26 05:41 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 17:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 17:09 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 17:09 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:09 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.8K Feb 26 05:43 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 92K Feb 26 05:43 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 05:43 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 94K Feb 26 05:43 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 17:09 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 17:09 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 35K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmartHome-PT-04-CTLFireability-00
FORMULA_NAME SmartHome-PT-04-CTLFireability-01
FORMULA_NAME SmartHome-PT-04-CTLFireability-02
FORMULA_NAME SmartHome-PT-04-CTLFireability-03
FORMULA_NAME SmartHome-PT-04-CTLFireability-04
FORMULA_NAME SmartHome-PT-04-CTLFireability-05
FORMULA_NAME SmartHome-PT-04-CTLFireability-06
FORMULA_NAME SmartHome-PT-04-CTLFireability-07
FORMULA_NAME SmartHome-PT-04-CTLFireability-08
FORMULA_NAME SmartHome-PT-04-CTLFireability-09
FORMULA_NAME SmartHome-PT-04-CTLFireability-10
FORMULA_NAME SmartHome-PT-04-CTLFireability-11
FORMULA_NAME SmartHome-PT-04-CTLFireability-12
FORMULA_NAME SmartHome-PT-04-CTLFireability-13
FORMULA_NAME SmartHome-PT-04-CTLFireability-14
FORMULA_NAME SmartHome-PT-04-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679201786174

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmartHome-PT-04
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 04:56:28] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 04:56:28] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 04:56:29] [INFO ] Load time of PNML (sax parser for PT used): 78 ms
[2023-03-19 04:56:29] [INFO ] Transformed 139 places.
[2023-03-19 04:56:29] [INFO ] Transformed 159 transitions.
[2023-03-19 04:56:29] [INFO ] Found NUPN structural information;
[2023-03-19 04:56:29] [INFO ] Parsed PT model containing 139 places and 159 transitions and 361 arcs in 225 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 14 ms.
Initial state reduction rules removed 1 formulas.
Deduced a syphon composed of 17 places in 4 ms
Reduce places removed 17 places and 19 transitions.
FORMULA SmartHome-PT-04-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 58 out of 122 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 140/140 transitions.
Discarding 17 places :
Symmetric choice reduction at 0 with 17 rule applications. Total rules 17 place count 105 transition count 123
Iterating global reduction 0 with 17 rules applied. Total rules applied 34 place count 105 transition count 123
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 35 place count 105 transition count 122
Applied a total of 35 rules in 33 ms. Remains 105 /122 variables (removed 17) and now considering 122/140 (removed 18) transitions.
// Phase 1: matrix 122 rows 105 cols
[2023-03-19 04:56:29] [INFO ] Computed 7 place invariants in 14 ms
[2023-03-19 04:56:29] [INFO ] Implicit Places using invariants in 415 ms returned []
[2023-03-19 04:56:29] [INFO ] Invariant cache hit.
[2023-03-19 04:56:29] [INFO ] Implicit Places using invariants and state equation in 148 ms returned []
Implicit Place search using SMT with State Equation took 605 ms to find 0 implicit places.
[2023-03-19 04:56:29] [INFO ] Invariant cache hit.
[2023-03-19 04:56:30] [INFO ] Dead Transitions using invariants and state equation in 137 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 105/122 places, 122/140 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 778 ms. Remains : 105/122 places, 122/140 transitions.
Support contains 58 out of 105 places after structural reductions.
[2023-03-19 04:56:30] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-19 04:56:30] [INFO ] Flatten gal took : 48 ms
FORMULA SmartHome-PT-04-CTLFireability-03 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 04:56:30] [INFO ] Flatten gal took : 29 ms
[2023-03-19 04:56:30] [INFO ] Input system was already deterministic with 122 transitions.
Support contains 52 out of 105 places (down from 58) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 114 resets, run finished after 703 ms. (steps per millisecond=14 ) properties (out of 49) seen :43
Incomplete Best-First random walk after 10001 steps, including 30 resets, run finished after 112 ms. (steps per millisecond=89 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10000 steps, including 32 resets, run finished after 77 ms. (steps per millisecond=129 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10000 steps, including 30 resets, run finished after 93 ms. (steps per millisecond=107 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 31 resets, run finished after 68 ms. (steps per millisecond=147 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 26 resets, run finished after 42 ms. (steps per millisecond=238 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 52 ms. (steps per millisecond=192 ) properties (out of 6) seen :0
Running SMT prover for 6 properties.
[2023-03-19 04:56:31] [INFO ] Invariant cache hit.
[2023-03-19 04:56:31] [INFO ] After 101ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:6
[2023-03-19 04:56:31] [INFO ] [Nat]Absence check using 7 positive place invariants in 3 ms returned sat
[2023-03-19 04:56:31] [INFO ] After 80ms SMT Verify possible using state equation in natural domain returned unsat :4 sat :2
[2023-03-19 04:56:32] [INFO ] Deduced a trap composed of 23 places in 60 ms of which 8 ms to minimize.
[2023-03-19 04:56:32] [INFO ] Deduced a trap composed of 27 places in 36 ms of which 1 ms to minimize.
[2023-03-19 04:56:32] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 132 ms
[2023-03-19 04:56:32] [INFO ] After 246ms SMT Verify possible using trap constraints in natural domain returned unsat :4 sat :2
Attempting to minimize the solution found.
Minimization took 23 ms.
[2023-03-19 04:56:32] [INFO ] After 362ms SMT Verify possible using all constraints in natural domain returned unsat :4 sat :2
Fused 6 Parikh solutions to 2 different solutions.
Parikh walk visited 1 properties in 9 ms.
Support contains 1 out of 105 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 105/105 places, 122/122 transitions.
Graph (trivial) has 99 edges and 105 vertex of which 45 / 105 are part of one of the 3 SCC in 7 ms
Free SCC test removed 42 places
Drop transitions removed 56 transitions
Reduce isomorphic transitions removed 56 transitions.
Drop transitions removed 20 transitions
Trivial Post-agglo rules discarded 20 transitions
Performed 20 trivial Post agglomeration. Transition count delta: 20
Iterating post reduction 0 with 20 rules applied. Total rules applied 21 place count 63 transition count 46
Reduce places removed 20 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 24 rules applied. Total rules applied 45 place count 43 transition count 42
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 47 place count 41 transition count 42
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 3 Pre rules applied. Total rules applied 47 place count 41 transition count 39
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 3 with 6 rules applied. Total rules applied 53 place count 38 transition count 39
Discarding 8 places :
Symmetric choice reduction at 3 with 8 rule applications. Total rules 61 place count 30 transition count 31
Iterating global reduction 3 with 8 rules applied. Total rules applied 69 place count 30 transition count 31
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 71 place count 30 transition count 29
Performed 11 Post agglomeration using F-continuation condition.Transition count delta: 11
Deduced a syphon composed of 11 places in 0 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 4 with 22 rules applied. Total rules applied 93 place count 19 transition count 18
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Graph (complete) has 43 edges and 19 vertex of which 17 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.1 ms
Discarding 2 places :
Also discarding 0 output transitions
Iterating post reduction 4 with 6 rules applied. Total rules applied 99 place count 17 transition count 13
Free-agglomeration rule applied 3 times.
Iterating global reduction 5 with 3 rules applied. Total rules applied 102 place count 17 transition count 10
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 5 with 3 rules applied. Total rules applied 105 place count 14 transition count 10
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 6 with 1 rules applied. Total rules applied 106 place count 13 transition count 9
Reduce places removed 2 places and 0 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 6 with 4 rules applied. Total rules applied 110 place count 11 transition count 7
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 7 with 2 rules applied. Total rules applied 112 place count 9 transition count 7
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 8 with 3 Pre rules applied. Total rules applied 112 place count 9 transition count 4
Deduced a syphon composed of 3 places in 0 ms
Ensure Unique test removed 1 places
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 8 with 7 rules applied. Total rules applied 119 place count 5 transition count 4
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 8 with 1 Pre rules applied. Total rules applied 119 place count 5 transition count 3
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 8 with 2 rules applied. Total rules applied 121 place count 4 transition count 3
Applied a total of 121 rules in 42 ms. Remains 4 /105 variables (removed 101) and now considering 3/122 (removed 119) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 42 ms. Remains : 4/105 places, 3/122 transitions.
Finished random walk after 2 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=2 )
Successfully simplified 4 atomic propositions for a total of 13 simplifications.
FORMULA SmartHome-PT-04-CTLFireability-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 17 ms
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 15 ms
[2023-03-19 04:56:32] [INFO ] Input system was already deterministic with 122 transitions.
Computed a total of 16 stabilizing places and 16 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 122/122 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 91 transition count 108
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 91 transition count 108
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 30 place count 91 transition count 106
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 36 place count 85 transition count 100
Iterating global reduction 1 with 6 rules applied. Total rules applied 42 place count 85 transition count 100
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 46 place count 81 transition count 96
Iterating global reduction 1 with 4 rules applied. Total rules applied 50 place count 81 transition count 96
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 52 place count 79 transition count 94
Iterating global reduction 1 with 2 rules applied. Total rules applied 54 place count 79 transition count 94
Applied a total of 54 rules in 42 ms. Remains 79 /105 variables (removed 26) and now considering 94/122 (removed 28) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 42 ms. Remains : 79/105 places, 94/122 transitions.
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 10 ms
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 11 ms
[2023-03-19 04:56:32] [INFO ] Input system was already deterministic with 94 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 105/105 places, 122/122 transitions.
Graph (trivial) has 95 edges and 105 vertex of which 37 / 105 are part of one of the 3 SCC in 1 ms
Free SCC test removed 34 places
Ensure Unique test removed 43 transitions
Reduce isomorphic transitions removed 43 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 22 transitions
Trivial Post-agglo rules discarded 22 transitions
Performed 22 trivial Post agglomeration. Transition count delta: 22
Iterating post reduction 0 with 22 rules applied. Total rules applied 23 place count 70 transition count 56
Reduce places removed 22 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 1 with 25 rules applied. Total rules applied 48 place count 48 transition count 53
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 2 with 2 rules applied. Total rules applied 50 place count 47 transition count 52
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 51 place count 46 transition count 52
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 4 Pre rules applied. Total rules applied 51 place count 46 transition count 48
Deduced a syphon composed of 4 places in 1 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 4 with 8 rules applied. Total rules applied 59 place count 42 transition count 48
Discarding 9 places :
Symmetric choice reduction at 4 with 9 rule applications. Total rules 68 place count 33 transition count 39
Iterating global reduction 4 with 9 rules applied. Total rules applied 77 place count 33 transition count 39
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 4 with 4 rules applied. Total rules applied 81 place count 33 transition count 35
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 82 place count 32 transition count 35
Performed 9 Post agglomeration using F-continuation condition.Transition count delta: 9
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 6 with 18 rules applied. Total rules applied 100 place count 23 transition count 26
Drop transitions removed 4 transitions
Redundant transition composition rules discarded 4 transitions
Iterating global reduction 6 with 4 rules applied. Total rules applied 104 place count 23 transition count 22
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 105 place count 22 transition count 22
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 7 with 2 rules applied. Total rules applied 107 place count 20 transition count 20
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 108 place count 19 transition count 20
Applied a total of 108 rules in 30 ms. Remains 19 /105 variables (removed 86) and now considering 20/122 (removed 102) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 31 ms. Remains : 19/105 places, 20/122 transitions.
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:56:32] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 122/122 transitions.
Discarding 17 places :
Symmetric choice reduction at 0 with 17 rule applications. Total rules 17 place count 88 transition count 105
Iterating global reduction 0 with 17 rules applied. Total rules applied 34 place count 88 transition count 105
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 36 place count 88 transition count 103
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 42 place count 82 transition count 97
Iterating global reduction 1 with 6 rules applied. Total rules applied 48 place count 82 transition count 97
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 53 place count 77 transition count 92
Iterating global reduction 1 with 5 rules applied. Total rules applied 58 place count 77 transition count 92
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 60 place count 75 transition count 90
Iterating global reduction 1 with 2 rules applied. Total rules applied 62 place count 75 transition count 90
Applied a total of 62 rules in 30 ms. Remains 75 /105 variables (removed 30) and now considering 90/122 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 30 ms. Remains : 75/105 places, 90/122 transitions.
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 10 ms
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 9 ms
[2023-03-19 04:56:32] [INFO ] Input system was already deterministic with 90 transitions.
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 122/122 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 91 transition count 108
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 91 transition count 108
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 29 place count 91 transition count 107
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 34 place count 86 transition count 102
Iterating global reduction 1 with 5 rules applied. Total rules applied 39 place count 86 transition count 102
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 42 place count 83 transition count 99
Iterating global reduction 1 with 3 rules applied. Total rules applied 45 place count 83 transition count 99
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 46 place count 82 transition count 98
Iterating global reduction 1 with 1 rules applied. Total rules applied 47 place count 82 transition count 98
Applied a total of 47 rules in 9 ms. Remains 82 /105 variables (removed 23) and now considering 98/122 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 82/105 places, 98/122 transitions.
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 7 ms
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 7 ms
[2023-03-19 04:56:32] [INFO ] Input system was already deterministic with 98 transitions.
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 122/122 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 89 transition count 106
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 89 transition count 106
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 34 place count 89 transition count 104
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 39 place count 84 transition count 99
Iterating global reduction 1 with 5 rules applied. Total rules applied 44 place count 84 transition count 99
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 48 place count 80 transition count 95
Iterating global reduction 1 with 4 rules applied. Total rules applied 52 place count 80 transition count 95
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 54 place count 78 transition count 93
Iterating global reduction 1 with 2 rules applied. Total rules applied 56 place count 78 transition count 93
Applied a total of 56 rules in 9 ms. Remains 78 /105 variables (removed 27) and now considering 93/122 (removed 29) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 78/105 places, 93/122 transitions.
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 6 ms
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 6 ms
[2023-03-19 04:56:32] [INFO ] Input system was already deterministic with 93 transitions.
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 122/122 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 91 transition count 108
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 91 transition count 108
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 29 place count 91 transition count 107
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 33 place count 87 transition count 103
Iterating global reduction 1 with 4 rules applied. Total rules applied 37 place count 87 transition count 103
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 40 place count 84 transition count 100
Iterating global reduction 1 with 3 rules applied. Total rules applied 43 place count 84 transition count 100
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 44 place count 83 transition count 99
Iterating global reduction 1 with 1 rules applied. Total rules applied 45 place count 83 transition count 99
Applied a total of 45 rules in 7 ms. Remains 83 /105 variables (removed 22) and now considering 99/122 (removed 23) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 83/105 places, 99/122 transitions.
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 5 ms
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 6 ms
[2023-03-19 04:56:32] [INFO ] Input system was already deterministic with 99 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 105/105 places, 122/122 transitions.
Graph (trivial) has 97 edges and 105 vertex of which 42 / 105 are part of one of the 3 SCC in 1 ms
Free SCC test removed 39 places
Ensure Unique test removed 49 transitions
Reduce isomorphic transitions removed 49 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 21 transitions
Trivial Post-agglo rules discarded 21 transitions
Performed 21 trivial Post agglomeration. Transition count delta: 21
Iterating post reduction 0 with 21 rules applied. Total rules applied 22 place count 65 transition count 51
Reduce places removed 21 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 25 rules applied. Total rules applied 47 place count 44 transition count 47
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 49 place count 42 transition count 47
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 3 Pre rules applied. Total rules applied 49 place count 42 transition count 44
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 3 with 6 rules applied. Total rules applied 55 place count 39 transition count 44
Discarding 8 places :
Symmetric choice reduction at 3 with 8 rule applications. Total rules 63 place count 31 transition count 36
Iterating global reduction 3 with 8 rules applied. Total rules applied 71 place count 31 transition count 36
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 73 place count 31 transition count 34
Performed 9 Post agglomeration using F-continuation condition.Transition count delta: 9
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 4 with 18 rules applied. Total rules applied 91 place count 22 transition count 25
Drop transitions removed 5 transitions
Redundant transition composition rules discarded 5 transitions
Iterating global reduction 4 with 5 rules applied. Total rules applied 96 place count 22 transition count 20
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 4 with 2 rules applied. Total rules applied 98 place count 20 transition count 20
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 100 place count 18 transition count 18
Applied a total of 100 rules in 19 ms. Remains 18 /105 variables (removed 87) and now considering 18/122 (removed 104) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 18/105 places, 18/122 transitions.
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:56:32] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 122/122 transitions.
Discarding 17 places :
Symmetric choice reduction at 0 with 17 rule applications. Total rules 17 place count 88 transition count 105
Iterating global reduction 0 with 17 rules applied. Total rules applied 34 place count 88 transition count 105
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 36 place count 88 transition count 103
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 41 place count 83 transition count 98
Iterating global reduction 1 with 5 rules applied. Total rules applied 46 place count 83 transition count 98
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 50 place count 79 transition count 94
Iterating global reduction 1 with 4 rules applied. Total rules applied 54 place count 79 transition count 94
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 56 place count 77 transition count 92
Iterating global reduction 1 with 2 rules applied. Total rules applied 58 place count 77 transition count 92
Applied a total of 58 rules in 6 ms. Remains 77 /105 variables (removed 28) and now considering 92/122 (removed 30) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 77/105 places, 92/122 transitions.
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 5 ms
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 6 ms
[2023-03-19 04:56:32] [INFO ] Input system was already deterministic with 92 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 105/105 places, 122/122 transitions.
Graph (trivial) has 79 edges and 105 vertex of which 17 / 105 are part of one of the 2 SCC in 0 ms
Free SCC test removed 15 places
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 28 transitions
Trivial Post-agglo rules discarded 28 transitions
Performed 28 trivial Post agglomeration. Transition count delta: 28
Iterating post reduction 0 with 28 rules applied. Total rules applied 29 place count 89 transition count 75
Reduce places removed 28 places and 0 transitions.
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 1 with 36 rules applied. Total rules applied 65 place count 61 transition count 67
Reduce places removed 5 places and 0 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Iterating post reduction 2 with 9 rules applied. Total rules applied 74 place count 56 transition count 63
Reduce places removed 4 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 3 with 7 rules applied. Total rules applied 81 place count 52 transition count 60
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 82 place count 51 transition count 60
Performed 6 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 6 Pre rules applied. Total rules applied 82 place count 51 transition count 54
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 5 with 12 rules applied. Total rules applied 94 place count 45 transition count 54
Discarding 9 places :
Symmetric choice reduction at 5 with 9 rule applications. Total rules 103 place count 36 transition count 45
Iterating global reduction 5 with 9 rules applied. Total rules applied 112 place count 36 transition count 45
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 5 with 3 rules applied. Total rules applied 115 place count 36 transition count 42
Performed 8 Post agglomeration using F-continuation condition.Transition count delta: 8
Deduced a syphon composed of 8 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 6 with 16 rules applied. Total rules applied 131 place count 28 transition count 34
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 6 with 3 rules applied. Total rules applied 134 place count 28 transition count 31
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 6 with 1 rules applied. Total rules applied 135 place count 27 transition count 30
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 136 place count 26 transition count 30
Applied a total of 136 rules in 16 ms. Remains 26 /105 variables (removed 79) and now considering 30/122 (removed 92) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 16 ms. Remains : 26/105 places, 30/122 transitions.
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:56:32] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 122/122 transitions.
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 15 place count 90 transition count 107
Iterating global reduction 0 with 15 rules applied. Total rules applied 30 place count 90 transition count 107
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 32 place count 90 transition count 105
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 36 place count 86 transition count 101
Iterating global reduction 1 with 4 rules applied. Total rules applied 40 place count 86 transition count 101
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 43 place count 83 transition count 98
Iterating global reduction 1 with 3 rules applied. Total rules applied 46 place count 83 transition count 98
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 47 place count 82 transition count 97
Iterating global reduction 1 with 1 rules applied. Total rules applied 48 place count 82 transition count 97
Applied a total of 48 rules in 6 ms. Remains 82 /105 variables (removed 23) and now considering 97/122 (removed 25) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 82/105 places, 97/122 transitions.
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 5 ms
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 6 ms
[2023-03-19 04:56:32] [INFO ] Input system was already deterministic with 97 transitions.
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 122/122 transitions.
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 15 place count 90 transition count 107
Iterating global reduction 0 with 15 rules applied. Total rules applied 30 place count 90 transition count 107
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 32 place count 90 transition count 105
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 38 place count 84 transition count 99
Iterating global reduction 1 with 6 rules applied. Total rules applied 44 place count 84 transition count 99
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 47 place count 81 transition count 96
Iterating global reduction 1 with 3 rules applied. Total rules applied 50 place count 81 transition count 96
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 51 place count 80 transition count 95
Iterating global reduction 1 with 1 rules applied. Total rules applied 52 place count 80 transition count 95
Applied a total of 52 rules in 6 ms. Remains 80 /105 variables (removed 25) and now considering 95/122 (removed 27) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 80/105 places, 95/122 transitions.
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 5 ms
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 6 ms
[2023-03-19 04:56:32] [INFO ] Input system was already deterministic with 95 transitions.
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 122/122 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 89 transition count 106
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 89 transition count 106
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 34 place count 89 transition count 104
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 39 place count 84 transition count 99
Iterating global reduction 1 with 5 rules applied. Total rules applied 44 place count 84 transition count 99
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 48 place count 80 transition count 95
Iterating global reduction 1 with 4 rules applied. Total rules applied 52 place count 80 transition count 95
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 54 place count 78 transition count 93
Iterating global reduction 1 with 2 rules applied. Total rules applied 56 place count 78 transition count 93
Applied a total of 56 rules in 6 ms. Remains 78 /105 variables (removed 27) and now considering 93/122 (removed 29) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 78/105 places, 93/122 transitions.
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 5 ms
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 4 ms
[2023-03-19 04:56:32] [INFO ] Input system was already deterministic with 93 transitions.
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 122/122 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 89 transition count 106
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 89 transition count 106
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 34 place count 89 transition count 104
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 39 place count 84 transition count 99
Iterating global reduction 1 with 5 rules applied. Total rules applied 44 place count 84 transition count 99
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 49 place count 79 transition count 94
Iterating global reduction 1 with 5 rules applied. Total rules applied 54 place count 79 transition count 94
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 56 place count 77 transition count 92
Iterating global reduction 1 with 2 rules applied. Total rules applied 58 place count 77 transition count 92
Applied a total of 58 rules in 6 ms. Remains 77 /105 variables (removed 28) and now considering 92/122 (removed 30) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 77/105 places, 92/122 transitions.
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 5 ms
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 5 ms
[2023-03-19 04:56:32] [INFO ] Input system was already deterministic with 92 transitions.
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 7 ms
[2023-03-19 04:56:32] [INFO ] Flatten gal took : 7 ms
[2023-03-19 04:56:32] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-19 04:56:32] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 105 places, 122 transitions and 285 arcs took 1 ms.
Total runtime 3997 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmartHome-PT-04
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA SmartHome-PT-04-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmartHome-PT-04-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679201817276

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:196
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:207
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: LAUNCH INITIAL
lola: LAUNCH task # 7 (type CNST) for 6 SmartHome-PT-04-CTLFireability-04
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 58 (type CNST) for 53 SmartHome-PT-04-CTLFireability-14
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 7 (type CNST) for SmartHome-PT-04-CTLFireability-04
lola: result : false
lola: FINISHED task # 58 (type CNST) for SmartHome-PT-04-CTLFireability-14
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: planning for (null) stopped (result already fixed).
lola: LAUNCH task # 27 (type EXCL) for 24 SmartHome-PT-04-CTLFireability-06
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: FINISHED task # 27 (type EXCL) for SmartHome-PT-04-CTLFireability-06
lola: result : true
lola: markings : 31
lola: fired transitions : 32
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 32 (type EXCL) for 31 SmartHome-PT-04-CTLFireability-07
lola: time limit : 200 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:738
lola: rewrite Frontend/Parser/formula_rewrite.k:694
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 75 (type FNDP) for 46 SmartHome-PT-04-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 76 (type EQUN) for 46 SmartHome-PT-04-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 78 (type SRCH) for 46 SmartHome-PT-04-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 78 (type SRCH) for SmartHome-PT-04-CTLFireability-12
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 75 (type FNDP) for SmartHome-PT-04-CTLFireability-12
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 76 (type EQUN) for SmartHome-PT-04-CTLFireability-12 (obsolete)
sara: try reading problem file /home/mcc/execution/373/CTLFireability-76.sara.

lola: FINISHED task # 76 (type EQUN) for SmartHome-PT-04-CTLFireability-12
lola: result : true
lola: FINISHED task # 32 (type EXCL) for SmartHome-PT-04-CTLFireability-07
lola: result : false
lola: markings : 60018
lola: fired transitions : 307491
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 73 (type EXCL) for 60 SmartHome-PT-04-CTLFireability-15
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: FINISHED task # 73 (type EXCL) for SmartHome-PT-04-CTLFireability-15
lola: result : true
lola: markings : 32
lola: fired transitions : 64
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 SmartHome-PT-04-CTLFireability-11
lola: time limit : 327 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-04-CTLFireability-04: INITIAL false preprocessing
SmartHome-PT-04-CTLFireability-07: CTL false CTL model checker
SmartHome-PT-04-CTLFireability-12: DISJ true findpath
SmartHome-PT-04-CTLFireability-14: DISJ true preprocessing
SmartHome-PT-04-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-05: DISJ 0 4 0 0 4 0 0 0
SmartHome-PT-04-CTLFireability-06: CONJ 0 1 0 0 3 0 0 0
SmartHome-PT-04-CTLFireability-08: EU 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 4/327 3/32 SmartHome-PT-04-CTLFireability-11 601829 m, 120365 m/sec, 3054092 t fired, .

Time elapsed: 5 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-04-CTLFireability-04: INITIAL false preprocessing
SmartHome-PT-04-CTLFireability-07: CTL false CTL model checker
SmartHome-PT-04-CTLFireability-12: DISJ true findpath
SmartHome-PT-04-CTLFireability-14: DISJ true preprocessing
SmartHome-PT-04-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-05: DISJ 0 4 0 0 4 0 0 0
SmartHome-PT-04-CTLFireability-06: CONJ 0 1 0 0 3 0 0 0
SmartHome-PT-04-CTLFireability-08: EU 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 9/327 6/32 SmartHome-PT-04-CTLFireability-11 1261217 m, 131877 m/sec, 6576846 t fired, .

Time elapsed: 10 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-04-CTLFireability-04: INITIAL false preprocessing
SmartHome-PT-04-CTLFireability-07: CTL false CTL model checker
SmartHome-PT-04-CTLFireability-12: DISJ true findpath
SmartHome-PT-04-CTLFireability-14: DISJ true preprocessing
SmartHome-PT-04-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-05: DISJ 0 4 0 0 4 0 0 0
SmartHome-PT-04-CTLFireability-06: CONJ 0 1 0 0 3 0 0 0
SmartHome-PT-04-CTLFireability-08: EU 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 14/327 6/32 SmartHome-PT-04-CTLFireability-11 1402178 m, 28192 m/sec, 10042351 t fired, .

Time elapsed: 15 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-04-CTLFireability-04: INITIAL false preprocessing
SmartHome-PT-04-CTLFireability-07: CTL false CTL model checker
SmartHome-PT-04-CTLFireability-12: DISJ true findpath
SmartHome-PT-04-CTLFireability-14: DISJ true preprocessing
SmartHome-PT-04-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-04-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-05: DISJ 0 4 0 0 4 0 0 0
SmartHome-PT-04-CTLFireability-06: CONJ 0 1 0 0 3 0 0 0
SmartHome-PT-04-CTLFireability-08: EU 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-04-CTLFireability-11: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 19/327 6/32 SmartHome-PT-04-CTLFireability-11 1402178 m, 0 m/sec, 13618285 t fired, .

Time elapsed: 20 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 13
lola: FINISHED task # 44 (type EXCL) for SmartHome-PT-04-CTLFireability-11
lola: result : false
lola: markings : 1465229
lola: fired transitions : 15554177
lola: time used : 22.000000
lola: memory pages used : 7
lola: LAUNCH task # 38 (type EXCL) for 37 SmartHome-PT-04-CTLFireability-09
lola: time limit : 357 sec
lola: memory limit: 32 pages
lola: FINISHED task # 38 (type EXCL) for SmartHome-PT-04-CTLFireability-09
lola: result : true
lola: markings : 137
lola: fired transitions : 299
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 24 SmartHome-PT-04-CTLFireability-06
lola: time limit : 397 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for SmartHome-PT-04-CTLFireability-06
lola: result : true
lola: markings : 364
lola: fired transitions : 548
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 9 SmartHome-PT-04-CTLFireability-05
lola: time limit : 447 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for SmartHome-PT-04-CTLFireability-05
lola: result : false
lola: markings : 365
lola: fired transitions : 547
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 9 SmartHome-PT-04-CTLFireability-05
lola: time limit : 511 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for SmartHome-PT-04-CTLFireability-05
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 12 (type EXCL) for 9 SmartHome-PT-04-CTLFireability-05
lola: time limit : 715 sec
lola: memory limit: 32 pages
lola: FINISHED task # 12 (type EXCL) for SmartHome-PT-04-CTLFireability-05
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 SmartHome-PT-04-CTLFireability-00
lola: time limit : 894 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for SmartHome-PT-04-CTLFireability-00
lola: result : false
lola: markings : 111
lola: fired transitions : 286
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 SmartHome-PT-04-CTLFireability-02
lola: time limit : 1192 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for SmartHome-PT-04-CTLFireability-02
lola: result : false
lola: markings : 12
lola: fired transitions : 14
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 35 (type EXCL) for 34 SmartHome-PT-04-CTLFireability-08
lola: time limit : 1788 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for SmartHome-PT-04-CTLFireability-08
lola: result : true
lola: markings : 13
lola: fired transitions : 40
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 SmartHome-PT-04-CTLFireability-10
lola: time limit : 3577 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for SmartHome-PT-04-CTLFireability-10
lola: result : true
lola: markings : 49
lola: fired transitions : 282
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-04-CTLFireability-00: CTL false CTL model checker
SmartHome-PT-04-CTLFireability-02: AGEF false tscc_search
SmartHome-PT-04-CTLFireability-04: INITIAL false preprocessing
SmartHome-PT-04-CTLFireability-05: DISJ true CTL model checker
SmartHome-PT-04-CTLFireability-06: CONJ true CONJ
SmartHome-PT-04-CTLFireability-07: CTL false CTL model checker
SmartHome-PT-04-CTLFireability-08: EU true state space /EU
SmartHome-PT-04-CTLFireability-09: CTL true CTL model checker
SmartHome-PT-04-CTLFireability-10: CTL true CTL model checker
SmartHome-PT-04-CTLFireability-11: CTL false CTL model checker
SmartHome-PT-04-CTLFireability-12: DISJ true findpath
SmartHome-PT-04-CTLFireability-14: DISJ true preprocessing
SmartHome-PT-04-CTLFireability-15: DISJ true CTL model checker


Time elapsed: 23 secs. Pages in use: 7

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmartHome-PT-04"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmartHome-PT-04, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912647000178"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmartHome-PT-04.tgz
mv SmartHome-PT-04 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;