About the Execution of LoLa+red for SmartHome-PT-03
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 316.403 | 33898.00 | 40396.00 | 689.20 | FFFFTFTTFFFFFTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r455-smll-167912647000170.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmartHome-PT-03, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912647000170
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 540K
-rw-r--r-- 1 mcc users 7.7K Feb 26 05:47 CTLCardinality.txt
-rw-r--r-- 1 mcc users 92K Feb 26 05:47 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Feb 26 05:44 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 26 05:44 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 17:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:09 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 17:09 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:09 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 05:50 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 141K Feb 26 05:50 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.9K Feb 26 05:48 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Feb 26 05:48 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 17:09 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 17:09 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 31K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SmartHome-PT-03-CTLFireability-00
FORMULA_NAME SmartHome-PT-03-CTLFireability-01
FORMULA_NAME SmartHome-PT-03-CTLFireability-02
FORMULA_NAME SmartHome-PT-03-CTLFireability-03
FORMULA_NAME SmartHome-PT-03-CTLFireability-04
FORMULA_NAME SmartHome-PT-03-CTLFireability-05
FORMULA_NAME SmartHome-PT-03-CTLFireability-06
FORMULA_NAME SmartHome-PT-03-CTLFireability-07
FORMULA_NAME SmartHome-PT-03-CTLFireability-08
FORMULA_NAME SmartHome-PT-03-CTLFireability-09
FORMULA_NAME SmartHome-PT-03-CTLFireability-10
FORMULA_NAME SmartHome-PT-03-CTLFireability-11
FORMULA_NAME SmartHome-PT-03-CTLFireability-12
FORMULA_NAME SmartHome-PT-03-CTLFireability-13
FORMULA_NAME SmartHome-PT-03-CTLFireability-14
FORMULA_NAME SmartHome-PT-03-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679201683327
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmartHome-PT-03
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 04:54:47] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 04:54:47] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 04:54:47] [INFO ] Load time of PNML (sax parser for PT used): 90 ms
[2023-03-19 04:54:47] [INFO ] Transformed 45 places.
[2023-03-19 04:54:47] [INFO ] Transformed 145 transitions.
[2023-03-19 04:54:47] [INFO ] Found NUPN structural information;
[2023-03-19 04:54:47] [INFO ] Parsed PT model containing 45 places and 145 transitions and 405 arcs in 234 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 23 ms.
Initial state reduction rules removed 2 formulas.
Ensure Unique test removed 77 transitions
Reduce redundant transitions removed 77 transitions.
FORMULA SmartHome-PT-03-CTLFireability-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmartHome-PT-03-CTLFireability-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 34 out of 45 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 45/45 places, 68/68 transitions.
Drop transitions removed 13 transitions
Redundant transition composition rules discarded 13 transitions
Iterating global reduction 0 with 13 rules applied. Total rules applied 13 place count 45 transition count 55
Applied a total of 13 rules in 26 ms. Remains 45 /45 variables (removed 0) and now considering 55/68 (removed 13) transitions.
[2023-03-19 04:54:47] [INFO ] Flow matrix only has 40 transitions (discarded 15 similar events)
// Phase 1: matrix 40 rows 45 cols
[2023-03-19 04:54:47] [INFO ] Computed 19 place invariants in 9 ms
[2023-03-19 04:54:47] [INFO ] Implicit Places using invariants in 312 ms returned []
[2023-03-19 04:54:47] [INFO ] Flow matrix only has 40 transitions (discarded 15 similar events)
[2023-03-19 04:54:47] [INFO ] Invariant cache hit.
[2023-03-19 04:54:48] [INFO ] State equation strengthened by 23 read => feed constraints.
[2023-03-19 04:54:48] [INFO ] Implicit Places using invariants and state equation in 201 ms returned []
Implicit Place search using SMT with State Equation took 576 ms to find 0 implicit places.
[2023-03-19 04:54:48] [INFO ] Flow matrix only has 40 transitions (discarded 15 similar events)
[2023-03-19 04:54:48] [INFO ] Invariant cache hit.
[2023-03-19 04:54:48] [INFO ] Dead Transitions using invariants and state equation in 185 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 45/45 places, 55/68 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 792 ms. Remains : 45/45 places, 55/68 transitions.
Support contains 34 out of 45 places after structural reductions.
[2023-03-19 04:54:48] [INFO ] Flatten gal took : 44 ms
[2023-03-19 04:54:48] [INFO ] Flatten gal took : 17 ms
[2023-03-19 04:54:48] [INFO ] Input system was already deterministic with 55 transitions.
Finished random walk after 138 steps, including 0 resets, run visited all 59 properties in 76 ms. (steps per millisecond=1 )
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 8 ms
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 12 ms
[2023-03-19 04:54:49] [INFO ] Input system was already deterministic with 55 transitions.
Computed a total of 22 stabilizing places and 13 stable transitions
Graph (complete) has 120 edges and 45 vertex of which 44 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.3 ms
Starting structural reductions in LTL mode, iteration 0 : 45/45 places, 55/55 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 37 transition count 47
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 37 transition count 47
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 0 with 3 rules applied. Total rules applied 19 place count 37 transition count 44
Applied a total of 19 rules in 11 ms. Remains 37 /45 variables (removed 8) and now considering 44/55 (removed 11) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 37/45 places, 44/55 transitions.
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 6 ms
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 6 ms
[2023-03-19 04:54:49] [INFO ] Input system was already deterministic with 44 transitions.
Starting structural reductions in LTL mode, iteration 0 : 45/45 places, 55/55 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 41 transition count 51
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 41 transition count 51
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 9 place count 41 transition count 50
Applied a total of 9 rules in 7 ms. Remains 41 /45 variables (removed 4) and now considering 50/55 (removed 5) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 41/45 places, 50/55 transitions.
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 6 ms
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 6 ms
[2023-03-19 04:54:49] [INFO ] Input system was already deterministic with 50 transitions.
Starting structural reductions in LTL mode, iteration 0 : 45/45 places, 55/55 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 44 transition count 55
Discarding 7 places :
Symmetric choice reduction at 1 with 7 rule applications. Total rules 8 place count 37 transition count 48
Iterating global reduction 1 with 7 rules applied. Total rules applied 15 place count 37 transition count 48
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 1 with 3 rules applied. Total rules applied 18 place count 37 transition count 45
Applied a total of 18 rules in 7 ms. Remains 37 /45 variables (removed 8) and now considering 45/55 (removed 10) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 37/45 places, 45/55 transitions.
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 4 ms
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 4 ms
[2023-03-19 04:54:49] [INFO ] Input system was already deterministic with 45 transitions.
Starting structural reductions in LTL mode, iteration 0 : 45/45 places, 55/55 transitions.
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 3 place count 42 transition count 52
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 42 transition count 52
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 7 place count 42 transition count 51
Applied a total of 7 rules in 6 ms. Remains 42 /45 variables (removed 3) and now considering 51/55 (removed 4) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 42/45 places, 51/55 transitions.
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 4 ms
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 5 ms
[2023-03-19 04:54:49] [INFO ] Input system was already deterministic with 51 transitions.
Starting structural reductions in LTL mode, iteration 0 : 45/45 places, 55/55 transitions.
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 7 place count 38 transition count 48
Iterating global reduction 0 with 7 rules applied. Total rules applied 14 place count 38 transition count 48
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 0 with 2 rules applied. Total rules applied 16 place count 38 transition count 46
Applied a total of 16 rules in 6 ms. Remains 38 /45 variables (removed 7) and now considering 46/55 (removed 9) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 38/45 places, 46/55 transitions.
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 4 ms
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 5 ms
[2023-03-19 04:54:49] [INFO ] Input system was already deterministic with 46 transitions.
Starting structural reductions in LTL mode, iteration 0 : 45/45 places, 55/55 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 44 transition count 55
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 7 place count 38 transition count 49
Iterating global reduction 1 with 6 rules applied. Total rules applied 13 place count 38 transition count 49
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 1 with 2 rules applied. Total rules applied 15 place count 38 transition count 47
Applied a total of 15 rules in 5 ms. Remains 38 /45 variables (removed 7) and now considering 47/55 (removed 8) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 38/45 places, 47/55 transitions.
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 14 ms
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 4 ms
[2023-03-19 04:54:49] [INFO ] Input system was already deterministic with 47 transitions.
Starting structural reductions in LTL mode, iteration 0 : 45/45 places, 55/55 transitions.
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 7 place count 38 transition count 48
Iterating global reduction 0 with 7 rules applied. Total rules applied 14 place count 38 transition count 48
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 0 with 3 rules applied. Total rules applied 17 place count 38 transition count 45
Applied a total of 17 rules in 4 ms. Remains 38 /45 variables (removed 7) and now considering 45/55 (removed 10) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 38/45 places, 45/55 transitions.
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 4 ms
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 4 ms
[2023-03-19 04:54:49] [INFO ] Input system was already deterministic with 45 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 45/45 places, 55/55 transitions.
Graph (trivial) has 25 edges and 45 vertex of which 4 / 45 are part of one of the 2 SCC in 5 ms
Free SCC test removed 2 places
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 7 place count 37 transition count 45
Iterating global reduction 0 with 6 rules applied. Total rules applied 13 place count 37 transition count 45
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 0 with 14 rules applied. Total rules applied 27 place count 30 transition count 38
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 30 place count 27 transition count 32
Iterating global reduction 0 with 3 rules applied. Total rules applied 33 place count 27 transition count 32
Drop transitions removed 5 transitions
Redundant transition composition rules discarded 5 transitions
Iterating global reduction 0 with 5 rules applied. Total rules applied 38 place count 27 transition count 27
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 39 place count 26 transition count 26
Iterating global reduction 0 with 1 rules applied. Total rules applied 40 place count 26 transition count 26
Applied a total of 40 rules in 31 ms. Remains 26 /45 variables (removed 19) and now considering 26/55 (removed 29) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 31 ms. Remains : 26/45 places, 26/55 transitions.
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:54:49] [INFO ] Input system was already deterministic with 26 transitions.
Starting structural reductions in LTL mode, iteration 0 : 45/45 places, 55/55 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 37 transition count 47
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 37 transition count 47
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 0 with 3 rules applied. Total rules applied 19 place count 37 transition count 44
Applied a total of 19 rules in 4 ms. Remains 37 /45 variables (removed 8) and now considering 44/55 (removed 11) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 37/45 places, 44/55 transitions.
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 4 ms
[2023-03-19 04:54:49] [INFO ] Input system was already deterministic with 44 transitions.
Starting structural reductions in LTL mode, iteration 0 : 45/45 places, 55/55 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 44 transition count 55
Discarding 7 places :
Symmetric choice reduction at 1 with 7 rule applications. Total rules 8 place count 37 transition count 48
Iterating global reduction 1 with 7 rules applied. Total rules applied 15 place count 37 transition count 48
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 1 with 3 rules applied. Total rules applied 18 place count 37 transition count 45
Applied a total of 18 rules in 5 ms. Remains 37 /45 variables (removed 8) and now considering 45/55 (removed 10) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 37/45 places, 45/55 transitions.
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 4 ms
[2023-03-19 04:54:49] [INFO ] Input system was already deterministic with 45 transitions.
Starting structural reductions in LTL mode, iteration 0 : 45/45 places, 55/55 transitions.
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 6 place count 39 transition count 49
Iterating global reduction 0 with 6 rules applied. Total rules applied 12 place count 39 transition count 49
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 0 with 3 rules applied. Total rules applied 15 place count 39 transition count 46
Applied a total of 15 rules in 4 ms. Remains 39 /45 variables (removed 6) and now considering 46/55 (removed 9) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 39/45 places, 46/55 transitions.
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 5 ms
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 4 ms
[2023-03-19 04:54:49] [INFO ] Input system was already deterministic with 46 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 45/45 places, 55/55 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 41 transition count 51
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 41 transition count 51
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 4 rules applied. Total rules applied 12 place count 39 transition count 49
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 13 place count 38 transition count 47
Iterating global reduction 0 with 1 rules applied. Total rules applied 14 place count 38 transition count 47
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 0 with 3 rules applied. Total rules applied 17 place count 38 transition count 44
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 18 place count 37 transition count 43
Iterating global reduction 0 with 1 rules applied. Total rules applied 19 place count 37 transition count 43
Applied a total of 19 rules in 16 ms. Remains 37 /45 variables (removed 8) and now considering 43/55 (removed 12) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 16 ms. Remains : 37/45 places, 43/55 transitions.
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 5 ms
[2023-03-19 04:54:49] [INFO ] Input system was already deterministic with 43 transitions.
Starting structural reductions in LTL mode, iteration 0 : 45/45 places, 55/55 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 44 transition count 55
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 7 place count 38 transition count 49
Iterating global reduction 1 with 6 rules applied. Total rules applied 13 place count 38 transition count 49
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 1 with 3 rules applied. Total rules applied 16 place count 38 transition count 46
Applied a total of 16 rules in 5 ms. Remains 38 /45 variables (removed 7) and now considering 46/55 (removed 9) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 38/45 places, 46/55 transitions.
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 5 ms
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 5 ms
[2023-03-19 04:54:49] [INFO ] Input system was already deterministic with 46 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 45/45 places, 55/55 transitions.
Graph (trivial) has 24 edges and 45 vertex of which 4 / 45 are part of one of the 2 SCC in 0 ms
Free SCC test removed 2 places
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Graph (complete) has 116 edges and 43 vertex of which 42 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.0 ms
Discarding 1 places :
Also discarding 0 output transitions
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 6 place count 38 transition count 47
Iterating global reduction 0 with 4 rules applied. Total rules applied 10 place count 38 transition count 47
Performed 8 Post agglomeration using F-continuation condition.Transition count delta: 8
Deduced a syphon composed of 8 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 0 with 16 rules applied. Total rules applied 26 place count 30 transition count 39
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 30 place count 26 transition count 31
Iterating global reduction 0 with 4 rules applied. Total rules applied 34 place count 26 transition count 31
Drop transitions removed 5 transitions
Redundant transition composition rules discarded 5 transitions
Iterating global reduction 0 with 5 rules applied. Total rules applied 39 place count 26 transition count 26
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 40 place count 25 transition count 25
Iterating global reduction 0 with 1 rules applied. Total rules applied 41 place count 25 transition count 25
Applied a total of 41 rules in 15 ms. Remains 25 /45 variables (removed 20) and now considering 25/55 (removed 30) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 15 ms. Remains : 25/45 places, 25/55 transitions.
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:54:49] [INFO ] Input system was already deterministic with 25 transitions.
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 7 ms
[2023-03-19 04:54:49] [INFO ] Flatten gal took : 6 ms
[2023-03-19 04:54:49] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 6 ms.
[2023-03-19 04:54:49] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 45 places, 55 transitions and 173 arcs took 2 ms.
Total runtime 2422 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmartHome-PT-03
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA SmartHome-PT-03-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmartHome-PT-03-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmartHome-PT-03-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmartHome-PT-03-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmartHome-PT-03-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmartHome-PT-03-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmartHome-PT-03-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmartHome-PT-03-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmartHome-PT-03-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmartHome-PT-03-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmartHome-PT-03-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmartHome-PT-03-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmartHome-PT-03-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmartHome-PT-03-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679201717225
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 7 (type EXCL) for 6 SmartHome-PT-03-CTLFireability-02
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/239 2/32 SmartHome-PT-03-CTLFireability-02 259201 m, 51840 m/sec, 8088402 t fired, .
Time elapsed: 6 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 7 (type EXCL) for SmartHome-PT-03-CTLFireability-02
lola: result : false
lola: markings : 259201
lola: fired transitions : 12166273
lola: time used : 7.000000
lola: memory pages used : 2
lola: LAUNCH task # 41 (type EXCL) for 40 SmartHome-PT-03-CTLFireability-14
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for SmartHome-PT-03-CTLFireability-14
lola: result : false
lola: markings : 97201
lola: fired transitions : 620834
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 35 (type EXCL) for 34 SmartHome-PT-03-CTLFireability-12
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for SmartHome-PT-03-CTLFireability-12
lola: result : false
lola: markings : 2
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 SmartHome-PT-03-CTLFireability-11
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for SmartHome-PT-03-CTLFireability-11
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 SmartHome-PT-03-CTLFireability-10
lola: time limit : 326 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for SmartHome-PT-03-CTLFireability-10
lola: result : false
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 SmartHome-PT-03-CTLFireability-06
lola: time limit : 359 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-03-CTLFireability-02: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-11: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-12: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
SmartHome-PT-03-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 2/359 1/32 SmartHome-PT-03-CTLFireability-06 138098 m, 27619 m/sec, 3144940 t fired, .
Time elapsed: 11 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 23 (type EXCL) for SmartHome-PT-03-CTLFireability-06
lola: result : true
lola: markings : 259201
lola: fired transitions : 6180954
lola: time used : 4.000000
lola: memory pages used : 2
lola: LAUNCH task # 18 (type EXCL) for 15 SmartHome-PT-03-CTLFireability-05
lola: time limit : 398 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-03-CTLFireability-02: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-06: CTL true CTL model checker
SmartHome-PT-03-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-11: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-12: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
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SmartHome-PT-03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 3/398 1/32 SmartHome-PT-03-CTLFireability-05 185366 m, 37073 m/sec, 4131673 t fired, .
Time elapsed: 16 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 18 (type EXCL) for SmartHome-PT-03-CTLFireability-05
lola: result : false
lola: markings : 259201
lola: fired transitions : 5953537
lola: time used : 4.000000
lola: memory pages used : 2
lola: LAUNCH task # 13 (type EXCL) for 12 SmartHome-PT-03-CTLFireability-04
lola: time limit : 447 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for SmartHome-PT-03-CTLFireability-04
lola: result : true
lola: markings : 259201
lola: fired transitions : 5953538
lola: time used : 3.000000
lola: memory pages used : 2
lola: LAUNCH task # 10 (type EXCL) for 9 SmartHome-PT-03-CTLFireability-03
lola: time limit : 511 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-03-CTLFireability-02: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-04: CTL true CTL model checker
SmartHome-PT-03-CTLFireability-06: CTL true CTL model checker
SmartHome-PT-03-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-11: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-12: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
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SmartHome-PT-03-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 1/511 1/32 SmartHome-PT-03-CTLFireability-03 34865 m, 6973 m/sec, 212379 t fired, .
Time elapsed: 21 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 10 (type EXCL) for SmartHome-PT-03-CTLFireability-03
lola: result : false
lola: markings : 97201
lola: fired transitions : 620833
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 SmartHome-PT-03-CTLFireability-01
lola: time limit : 596 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for SmartHome-PT-03-CTLFireability-01
lola: result : false
lola: markings : 183601
lola: fired transitions : 4210845
lola: time used : 2.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 SmartHome-PT-03-CTLFireability-00
lola: time limit : 715 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-03-CTLFireability-01: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-02: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-03: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-04: CTL true CTL model checker
SmartHome-PT-03-CTLFireability-06: CTL true CTL model checker
SmartHome-PT-03-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-11: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-12: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmartHome-PT-03-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
SmartHome-PT-03-CTLFireability-05: DISJ 0 1 0 0 3 0 0 0
SmartHome-PT-03-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmartHome-PT-03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 3/715 1/32 SmartHome-PT-03-CTLFireability-00 179004 m, 35800 m/sec, 3982032 t fired, .
Time elapsed: 26 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 1 (type EXCL) for SmartHome-PT-03-CTLFireability-00
lola: result : false
lola: markings : 259201
lola: fired transitions : 5953537
lola: time used : 4.000000
lola: memory pages used : 2
lola: LAUNCH task # 20 (type EXCL) for 15 SmartHome-PT-03-CTLFireability-05
lola: time limit : 893 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for SmartHome-PT-03-CTLFireability-05
lola: result : false
lola: markings : 451
lola: fired transitions : 9013
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 SmartHome-PT-03-CTLFireability-07
lola: time limit : 1191 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for SmartHome-PT-03-CTLFireability-07
lola: result : true
lola: markings : 901
lola: fired transitions : 25129
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 SmartHome-PT-03-CTLFireability-15
lola: time limit : 1786 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for SmartHome-PT-03-CTLFireability-15
lola: result : false
lola: markings : 2
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 38 (type EXCL) for 37 SmartHome-PT-03-CTLFireability-13
lola: time limit : 3573 sec
lola: memory limit: 32 pages
lola: FINISHED task # 38 (type EXCL) for SmartHome-PT-03-CTLFireability-13
lola: result : true
lola: markings : 2
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmartHome-PT-03-CTLFireability-00: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-01: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-02: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-03: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-04: CTL true CTL model checker
SmartHome-PT-03-CTLFireability-05: DISJ false DISJ
SmartHome-PT-03-CTLFireability-06: CTL true CTL model checker
SmartHome-PT-03-CTLFireability-07: CTL true CTL model checker
SmartHome-PT-03-CTLFireability-10: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-11: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-12: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-13: CTL true CTL model checker
SmartHome-PT-03-CTLFireability-14: CTL false CTL model checker
SmartHome-PT-03-CTLFireability-15: CTL false CTL model checker
Time elapsed: 27 secs. Pages in use: 2
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmartHome-PT-03"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmartHome-PT-03, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912647000170"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SmartHome-PT-03.tgz
mv SmartHome-PT-03 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;