About the Execution of LoLa+red for SmallOperatingSystem-PT-MT8192DC4096
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 2729.088 | 82682.00 | 76620.00 | 873.60 | F??F?TTTT?FFFTFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r455-smll-167912647000146.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmallOperatingSystem-PT-MT8192DC4096, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912647000146
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 492K
-rw-r--r-- 1 mcc users 11K Feb 25 12:49 CTLCardinality.txt
-rw-r--r-- 1 mcc users 97K Feb 25 12:49 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.6K Feb 25 12:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 25 12:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.4K Feb 25 17:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:08 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 17:08 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:08 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 12:49 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 94K Feb 25 12:49 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 25 12:49 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 87K Feb 25 12:49 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 17:08 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 17:08 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 8.1K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679200881010
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT8192DC4096
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 04:41:24] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 04:41:25] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 04:41:25] [INFO ] Load time of PNML (sax parser for PT used): 42 ms
[2023-03-19 04:41:25] [INFO ] Transformed 9 places.
[2023-03-19 04:41:25] [INFO ] Transformed 8 transitions.
[2023-03-19 04:41:25] [INFO ] Parsed PT model containing 9 places and 8 transitions and 27 arcs in 190 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 27 ms.
Initial state reduction rules removed 5 formulas.
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 20 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
// Phase 1: matrix 8 rows 9 cols
[2023-03-19 04:41:25] [INFO ] Computed 4 place invariants in 6 ms
[2023-03-19 04:41:25] [INFO ] Implicit Places using invariants in 222 ms returned []
[2023-03-19 04:41:25] [INFO ] Invariant cache hit.
[2023-03-19 04:41:25] [INFO ] Implicit Places using invariants and state equation in 51 ms returned []
Implicit Place search using SMT with State Equation took 334 ms to find 0 implicit places.
[2023-03-19 04:41:25] [INFO ] Invariant cache hit.
[2023-03-19 04:41:25] [INFO ] Dead Transitions using invariants and state equation in 52 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 409 ms. Remains : 9/9 places, 8/8 transitions.
Support contains 9 out of 9 places after structural reductions.
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 29 ms
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 10 ms
[2023-03-19 04:41:26] [INFO ] Input system was already deterministic with 8 transitions.
Incomplete random walk after 12293 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=315 ) properties (out of 21) seen :5
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 35 ms. (steps per millisecond=28 ) properties (out of 16) seen :15
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-19 04:41:26] [INFO ] Invariant cache hit.
[2023-03-19 04:41:26] [INFO ] [Real]Absence check using 4 positive place invariants in 4 ms returned sat
[2023-03-19 04:41:26] [INFO ] After 66ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 04:41:26] [INFO ] [Nat]Absence check using 4 positive place invariants in 3 ms returned sat
[2023-03-19 04:41:26] [INFO ] After 16ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 04:41:26] [INFO ] After 28ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 10 ms.
[2023-03-19 04:41:26] [INFO ] After 98ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Finished Parikh walk after 16386 steps, including 0 resets, run visited all 1 properties in 204 ms. (steps per millisecond=80 )
Parikh walk visited 1 properties in 220 ms.
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 6 ms
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 6 ms
[2023-03-19 04:41:26] [INFO ] Input system was already deterministic with 8 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 2 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 4 ms
[2023-03-19 04:41:26] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:41:26] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:41:26] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:41:26] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 3 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:41:26] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:41:26] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:41:26] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 1 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:41:26] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 8 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:41:26] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:41:26] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:41:26] [INFO ] Input system was already deterministic with 8 transitions.
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:41:26] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:41:26] [INFO ] Export to MCC of 11 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-19 04:41:26] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9 places, 8 transitions and 27 arcs took 0 ms.
Total runtime 2003 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT8192DC4096
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679200963692
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
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lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 16 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03
lola: result : false
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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lola: FINISHED task # 1 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00
lola: result : false
lola: markings : 8193
lola: fired transitions : 8194
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 33 (type EXCL) for 32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09
lola: time limit : 3550 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 5/3550 8/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09 1924723 m, 384944 m/sec, 8645788 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 10/3550 17/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09 3942433 m, 403542 m/sec, 17721479 t fired, .
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# running tasks: 1 of 4 Visible: 11
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 15/3550 24/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09 5834529 m, 378419 m/sec, 26232315 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 20/3550 32/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09 7667529 m, 366600 m/sec, 34477575 t fired, .
Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 11
lola: CANCELED task # 33 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 11
lola: Portfolio finished: no open tasks 11
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CTL unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: CONJ unknown CONJ
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: CTL unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker
Time elapsed: 75 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT8192DC4096"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmallOperatingSystem-PT-MT8192DC4096, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912647000146"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT8192DC4096.tgz
mv SmallOperatingSystem-PT-MT8192DC4096 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;