About the Execution of LoLa+red for SmallOperatingSystem-PT-MT8192DC4096
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 5621.292 | 237658.00 | 248519.00 | 1243.20 | F?FTF??T??FT??FF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r455-smll-167912647000145.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmallOperatingSystem-PT-MT8192DC4096, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912647000145
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 492K
-rw-r--r-- 1 mcc users 11K Feb 25 12:49 CTLCardinality.txt
-rw-r--r-- 1 mcc users 97K Feb 25 12:49 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.6K Feb 25 12:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 25 12:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.4K Feb 25 17:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:08 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 17:08 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:08 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 12:49 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 94K Feb 25 12:49 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 25 12:49 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 87K Feb 25 12:49 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 17:08 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 17:08 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 8.1K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-02
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-03
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-04
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-07
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-14
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-15
=== Now, execution of the tool begins
BK_START 1679200632339
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT8192DC4096
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 04:37:16] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLCardinality, -timeout, 360, -rebuildPNML]
[2023-03-19 04:37:16] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 04:37:16] [INFO ] Load time of PNML (sax parser for PT used): 41 ms
[2023-03-19 04:37:16] [INFO ] Transformed 9 places.
[2023-03-19 04:37:16] [INFO ] Transformed 8 transitions.
[2023-03-19 04:37:16] [INFO ] Parsed PT model containing 9 places and 8 transitions and 27 arcs in 280 ms.
Parsed 16 properties from file /home/mcc/execution/CTLCardinality.xml in 37 ms.
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 22 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
// Phase 1: matrix 8 rows 9 cols
[2023-03-19 04:37:16] [INFO ] Computed 4 place invariants in 7 ms
[2023-03-19 04:37:16] [INFO ] Implicit Places using invariants in 225 ms returned []
[2023-03-19 04:37:16] [INFO ] Invariant cache hit.
[2023-03-19 04:37:16] [INFO ] Implicit Places using invariants and state equation in 55 ms returned []
Implicit Place search using SMT with State Equation took 339 ms to find 0 implicit places.
[2023-03-19 04:37:16] [INFO ] Invariant cache hit.
[2023-03-19 04:37:16] [INFO ] Dead Transitions using invariants and state equation in 51 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 415 ms. Remains : 9/9 places, 8/8 transitions.
Support contains 9 out of 9 places after structural reductions.
[2023-03-19 04:37:17] [INFO ] Flatten gal took : 30 ms
[2023-03-19 04:37:17] [INFO ] Flatten gal took : 11 ms
[2023-03-19 04:37:17] [INFO ] Input system was already deterministic with 8 transitions.
Incomplete random walk after 12293 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=384 ) properties (out of 98) seen :17
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 126 ms. (steps per millisecond=7 ) properties (out of 81) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 66 ms. (steps per millisecond=15 ) properties (out of 81) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 94 ms. (steps per millisecond=10 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 61 ms. (steps per millisecond=16 ) properties (out of 78) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 55 ms. (steps per millisecond=18 ) properties (out of 78) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 84 ms. (steps per millisecond=11 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=26 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=27 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=23 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 35 ms. (steps per millisecond=28 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 35 ms. (steps per millisecond=28 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 75) seen :0
Running SMT prover for 75 properties.
[2023-03-19 04:37:18] [INFO ] Invariant cache hit.
[2023-03-19 04:37:19] [INFO ] [Real]Absence check using 4 positive place invariants in 7 ms returned sat
[2023-03-19 04:37:19] [INFO ] After 191ms SMT Verify possible using state equation in real domain returned unsat :14 sat :10 real:51
[2023-03-19 04:37:19] [INFO ] After 254ms SMT Verify possible using trap constraints in real domain returned unsat :14 sat :2 real:59
Attempting to minimize the solution found.
Minimization took 18 ms.
[2023-03-19 04:37:19] [INFO ] After 628ms SMT Verify possible using all constraints in real domain returned unsat :14 sat :2 real:59
[2023-03-19 04:37:19] [INFO ] [Nat]Absence check using 4 positive place invariants in 2 ms returned sat
[2023-03-19 04:37:19] [INFO ] After 167ms SMT Verify possible using state equation in natural domain returned unsat :19 sat :56
[2023-03-19 04:37:20] [INFO ] After 372ms SMT Verify possible using trap constraints in natural domain returned unsat :19 sat :56
Attempting to minimize the solution found.
Minimization took 199 ms.
[2023-03-19 04:37:20] [INFO ] After 860ms SMT Verify possible using all constraints in natural domain returned unsat :19 sat :56
Fused 75 Parikh solutions to 55 different solutions.
Finished Parikh walk after 29562 steps, including 0 resets, run visited all 1 properties in 44 ms. (steps per millisecond=671 )
Parikh walk visited 56 properties in 19623 ms.
Successfully simplified 19 atomic propositions for a total of 16 simplifications.
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-02 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 04:37:39] [INFO ] Initial state reduction rules for CTL removed 3 formulas.
[2023-03-19 04:37:39] [INFO ] Flatten gal took : 6 ms
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-04 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 04:37:40] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:37:40] [INFO ] Input system was already deterministic with 8 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 7
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Applied a total of 2 rules in 23 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 23 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 04:37:40] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:37:40] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:37:40] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 04:37:40] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:37:40] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:37:40] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 5 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 04:37:40] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:37:40] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:37:40] [INFO ] Input system was already deterministic with 7 transitions.
Incomplete random walk after 12293 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=647 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2443607 steps, run timeout after 3001 ms. (steps per millisecond=814 ) properties seen :{}
Probabilistic random walk after 2443607 steps, saw 1188718 distinct states, run finished after 3002 ms. (steps per millisecond=813 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 7 rows 7 cols
[2023-03-19 04:37:43] [INFO ] Computed 3 place invariants in 2 ms
[2023-03-19 04:37:43] [INFO ] After 30ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 04:37:43] [INFO ] [Nat]Absence check using 3 positive place invariants in 2 ms returned sat
[2023-03-19 04:37:43] [INFO ] After 9ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 04:37:43] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-19 04:37:43] [INFO ] After 4ms SMT Verify possible using 1 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 04:37:43] [INFO ] After 8ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 5 ms.
[2023-03-19 04:37:43] [INFO ] After 58ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Finished Parikh walk after 4102 steps, including 0 resets, run visited all 1 properties in 8 ms. (steps per millisecond=512 )
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-03 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 1 properties in 7 ms.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 2 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:37:43] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 7
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 5 place count 5 transition count 6
Applied a total of 5 rules in 1 ms. Remains 5 /9 variables (removed 4) and now considering 6/8 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 5/9 places, 6/8 transitions.
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 0 ms
[2023-03-19 04:37:43] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 7
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 5 place count 5 transition count 6
Applied a total of 5 rules in 1 ms. Remains 5 /9 variables (removed 4) and now considering 6/8 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 5/9 places, 6/8 transitions.
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 0 ms
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:37:43] [INFO ] Input system was already deterministic with 6 transitions.
Finished random walk after 8193 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=4096 )
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-07 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:37:43] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:37:43] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 7
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 5 place count 5 transition count 6
Applied a total of 5 rules in 2 ms. Remains 5 /9 variables (removed 4) and now considering 6/8 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 5/9 places, 6/8 transitions.
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 0 ms
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 0 ms
[2023-03-19 04:37:43] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:37:43] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 0 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:37:43] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 1 ms
[2023-03-19 04:37:43] [INFO ] Input system was already deterministic with 8 transitions.
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 3 ms
[2023-03-19 04:37:43] [INFO ] Flatten gal took : 2 ms
[2023-03-19 04:37:43] [INFO ] Export to MCC of 10 properties in file /home/mcc/execution/CTLCardinality.sr.xml took 2 ms.
[2023-03-19 04:37:43] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9 places, 8 transitions and 27 arcs took 0 ms.
Total runtime 27324 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT8192DC4096
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/371
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679200869997
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/371/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/371/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/371/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:207
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 15 (type EXCL) for 12 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: FINISHED task # 15 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08
lola: result : false
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 24 (type EXCL) for 19 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 50 (type FNDP) for 26 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type EQUN) for 26 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 53 (type SRCH) for 26 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 53 (type SRCH) for SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10
lola: result : unknown
lola: markings : 4
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 50 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10
lola: result : true
lola: fired transitions : 1439
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 51 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10 (obsolete)
lola: LAUNCH task # 44 (type FNDP) for 0 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 45 (type EQUN) for 0 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 47 (type SRCH) for 0 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 47 (type SRCH) for SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00
lola: result : unknown
lola: markings : 5
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/371/CTLCardinality-45.sara.
sara: try reading problem file /home/mcc/execution/371/CTLCardinality-51.sara.
lola: FINISHED task # 44 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00
lola: result : true
lola: fired transitions : 16393
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 45 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00 (obsolete)
lola: FINISHED task # 45 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00
lola: result : unknown
lola: FINISHED task # 51 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
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24 CTL EXCL 5/360 7/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09 1502255 m, 300451 m/sec, 5170516 t fired, .
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lola: CANCELED task # 24 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09 (memory limit exceeded)
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 1 0 0 2 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 5/396 16/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12 3768776 m, 753755 m/sec, 8161480 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 1 0 0 2 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 10/396 32/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12 7481367 m, 742518 m/sec, 16203540 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 1 0 0 2 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: FINISHED task # 34 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11
lola: result : true
lola: markings : 2433596
lola: fired transitions : 4864074
lola: time used : 3.000000
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lola: LAUNCH task # 22 (type EXCL) for 19 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 1 0 2 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 2/507 2/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09 371567 m, 74313 m/sec, 1957815 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 1 0 2 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 7/507 7/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09 1500905 m, 225867 m/sec, 8030129 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 1 0 2 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 12/507 11/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09 2572451 m, 214309 m/sec, 13822823 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 1 0 2 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 17/507 15/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09 3645213 m, 214552 m/sec, 19636103 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 1 0 2 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 22/507 19/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09 4687379 m, 208433 m/sec, 25290834 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 1 0 2 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 27/507 23/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09 5713526 m, 205229 m/sec, 30864130 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 1 0 2 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 32/507 28/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09 6783528 m, 214000 m/sec, 36680185 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 1 0 2 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 37/507 32/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09 7843344 m, 211963 m/sec, 42443055 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 7 (type EXCL) for 6 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
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7 CTL EXCL 5/585 14/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05 3254477 m, 650895 m/sec, 8090215 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/585 25/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05 6201239 m, 589352 m/sec, 15432847 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 5/699 10/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06 2613384 m, 522676 m/sec, 9506395 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 10/699 19/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06 4970497 m, 471422 m/sec, 18409442 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 15/699 26/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06 7050622 m, 416025 m/sec, 26365880 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 1 0 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ 0 1 0 0 5 0 0 1
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 42 (type EXCL) for 26 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10
lola: time limit : 868 sec
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lola: FINISHED task # 42 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10
lola: result : true
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 17 (type EXCL) for 12 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08
lola: time limit : 1158 sec
lola: memory limit: 32 pages
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 0 1 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 5/1158 8/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08 1966679 m, 393335 m/sec, 8817125 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 0 1 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 10/1158 16/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08 3841942 m, 375052 m/sec, 17237565 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 0 1 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 15/1158 23/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08 5648600 m, 361331 m/sec, 25352494 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 0 1 0 3 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 20/1158 31/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08 7532060 m, 376692 m/sec, 33813924 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 40 (type EXCL) for 39 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13
lola: time limit : 1725 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/1725 16/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13 3785814 m, 757162 m/sec, 8513503 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 10/1725 30/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13 7270820 m, 697001 m/sec, 16352143 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 4 (type EXCL) for 3 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/3435 5/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01 1169760 m, 233952 m/sec, 8750104 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/3435 10/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01 2281779 m, 222403 m/sec, 17077165 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/3435 14/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01 3368478 m, 217339 m/sec, 25216145 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/3435 18/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01 4414105 m, 209125 m/sec, 33048841 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/3435 22/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01 5434351 m, 204049 m/sec, 40692539 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/3435 27/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01 6506801 m, 214490 m/sec, 48727751 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 35/3435 31/32 SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01 7574841 m, 213608 m/sec, 56730023 t fired, .
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
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FINAL RESULTS
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SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-00: AG false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-01: CTL unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-05: CTL unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-06: EFAG unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-08: DISJ unknown DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-09: DISJ unknown DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-10: DISJ false DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLCardinality-11: CTL true CTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT8192DC4096"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmallOperatingSystem-PT-MT8192DC4096, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912647000145"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT8192DC4096.tgz
mv SmallOperatingSystem-PT-MT8192DC4096 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;