Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r455-smll-167912647000129.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmallOperatingSystem-PT-MT4096DC2048, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912647000129
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 448K
-rw-r--r-- 1 mcc users 8.6K Feb 25 12:48 CTLCardinality.txt
-rw-r--r-- 1 mcc users 75K Feb 25 12:48 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.3K Feb 25 12:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K Feb 25 12:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.5K Feb 25 17:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 17:08 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Feb 25 17:08 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:08 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 12:49 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 105K Feb 25 12:49 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.5K Feb 25 12:49 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 50K Feb 25 12:49 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 17:08 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 17:08 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 8.1K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-00
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-01
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-02
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-03
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-05
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-07
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-09
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-13
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15

=== Now, execution of the tool begins

BK_START 1679195757191

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT4096DC2048
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 03:16:00] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLCardinality, -timeout, 360, -rebuildPNML]
[2023-03-19 03:16:00] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 03:16:00] [INFO ] Load time of PNML (sax parser for PT used): 28 ms
[2023-03-19 03:16:00] [INFO ] Transformed 9 places.
[2023-03-19 03:16:00] [INFO ] Transformed 8 transitions.
[2023-03-19 03:16:00] [INFO ] Parsed PT model containing 9 places and 8 transitions and 27 arcs in 133 ms.
Parsed 16 properties from file /home/mcc/execution/CTLCardinality.xml in 20 ms.
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 13 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
// Phase 1: matrix 8 rows 9 cols
[2023-03-19 03:16:00] [INFO ] Computed 4 place invariants in 5 ms
[2023-03-19 03:16:00] [INFO ] Implicit Places using invariants in 192 ms returned []
[2023-03-19 03:16:00] [INFO ] Invariant cache hit.
[2023-03-19 03:16:01] [INFO ] Implicit Places using invariants and state equation in 39 ms returned []
Implicit Place search using SMT with State Equation took 274 ms to find 0 implicit places.
[2023-03-19 03:16:01] [INFO ] Invariant cache hit.
[2023-03-19 03:16:01] [INFO ] Dead Transitions using invariants and state equation in 35 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 325 ms. Remains : 9/9 places, 8/8 transitions.
Support contains 9 out of 9 places after structural reductions.
[2023-03-19 03:16:01] [INFO ] Flatten gal took : 20 ms
[2023-03-19 03:16:01] [INFO ] Flatten gal took : 6 ms
[2023-03-19 03:16:01] [INFO ] Input system was already deterministic with 8 transitions.
Incomplete random walk after 10247 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=238 ) properties (out of 83) seen :16
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 88 ms. (steps per millisecond=11 ) properties (out of 67) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 96 ms. (steps per millisecond=10 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 57 ms. (steps per millisecond=17 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 54 ms. (steps per millisecond=18 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 66) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=24 ) properties (out of 66) seen :4
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 62) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 62) seen :0
Running SMT prover for 62 properties.
[2023-03-19 03:16:02] [INFO ] Invariant cache hit.
[2023-03-19 03:16:02] [INFO ] [Real]Absence check using 4 positive place invariants in 1 ms returned sat
[2023-03-19 03:16:02] [INFO ] After 41ms SMT Verify possible using state equation in real domain returned unsat :4 sat :3 real:55
[2023-03-19 03:16:02] [INFO ] After 58ms SMT Verify possible using trap constraints in real domain returned unsat :4 sat :3 real:55
Attempting to minimize the solution found.
Minimization took 19 ms.
[2023-03-19 03:16:02] [INFO ] After 288ms SMT Verify possible using all constraints in real domain returned unsat :4 sat :3 real:55
[2023-03-19 03:16:03] [INFO ] [Nat]Absence check using 4 positive place invariants in 2 ms returned sat
[2023-03-19 03:16:03] [INFO ] After 98ms SMT Verify possible using state equation in natural domain returned unsat :24 sat :38
[2023-03-19 03:16:03] [INFO ] After 215ms SMT Verify possible using trap constraints in natural domain returned unsat :24 sat :38
Attempting to minimize the solution found.
Minimization took 80 ms.
[2023-03-19 03:16:03] [INFO ] After 486ms SMT Verify possible using all constraints in natural domain returned unsat :24 sat :38
Fused 62 Parikh solutions to 38 different solutions.
Finished Parikh walk after 12290 steps, including 0 resets, run visited all 1 properties in 11 ms. (steps per millisecond=1117 )
Parikh walk visited 38 properties in 6174 ms.
Successfully simplified 24 atomic propositions for a total of 16 simplifications.
[2023-03-19 03:16:09] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 5 ms
[2023-03-19 03:16:09] [INFO ] Initial state reduction rules for CTL removed 2 formulas.
FORMULA SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-00 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 3 ms
[2023-03-19 03:16:09] [INFO ] Input system was already deterministic with 8 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 2 ms
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 2 ms
[2023-03-19 03:16:09] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 2 ms
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 2 ms
[2023-03-19 03:16:09] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Applied a total of 0 rules in 6 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 2 ms
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:16:09] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 2 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:16:09] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 2 ms
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:16:09] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 1 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:16:09] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 0 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 2 ms
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:16:09] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 7
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 5 place count 5 transition count 6
Applied a total of 5 rules in 4 ms. Remains 5 /9 variables (removed 4) and now considering 6/8 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 5/9 places, 6/8 transitions.
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 0 ms
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:16:09] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 7
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Applied a total of 2 rules in 1 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:16:09] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 7 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Applied a total of 2 rules in 1 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 0 ms
[2023-03-19 03:16:09] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 1 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:16:09] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 2 ms
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:16:09] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 1 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:16:09] [INFO ] Input system was already deterministic with 7 transitions.
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 2 ms
[2023-03-19 03:16:09] [INFO ] Flatten gal took : 1 ms
[2023-03-19 03:16:09] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLCardinality.sr.xml took 2 ms.
[2023-03-19 03:16:09] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9 places, 8 transitions and 27 arcs took 0 ms.
Total runtime 9311 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT4096DC2048
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374

FORMULA SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679195943537

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:287
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 4 (type EXCL) for 3 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-02
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 41 (type FNDP) for 9 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-07: EXEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/276 10/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-02 2349320 m, 469864 m/sec, 5836271 t fired, .
41 EF DL FNDP 5/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 73287462 t fired, 74 attempts, .

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-07: EXEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/276 19/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-02 4643778 m, 458891 m/sec, 11551109 t fired, .
41 EF DL FNDP 10/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 150492639 t fired, 151 attempts, .

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-07: EXEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/276 28/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-02 6963064 m, 463857 m/sec, 17331117 t fired, .
41 EF DL FNDP 15/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 227822028 t fired, 228 attempts, .

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-07: EXEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 EF DL FNDP 20/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 305818843 t fired, 306 attempts, .

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lola: LAUNCH task # 31 (type EXCL) for 30 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-13
lola: time limit : 298 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-07: EXEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-13: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/298 17/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-13 4140735 m, 828147 m/sec, 8277889 t fired, .
41 EF DL FNDP 25/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 383327891 t fired, 384 attempts, .

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lola: FINISHED task # 31 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-13
lola: result : true
lola: markings : 6859157
lola: fired transitions : 13713078
lola: time used : 9.000000
lola: memory pages used : 28
lola: LAUNCH task # 19 (type EXCL) for 18 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08
lola: time limit : 324 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-13: CTL true CTL model checker

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-07: EXEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 1/324 3/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08 701245 m, 140249 m/sec, 1517817 t fired, .
41 EF DL FNDP 30/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 460646842 t fired, 461 attempts, .

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-13: CTL true CTL model checker

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-07: EXEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 6/324 21/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08 4890645 m, 837880 m/sec, 10592178 t fired, .
41 EF DL FNDP 35/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 538110277 t fired, 539 attempts, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-13: CTL true CTL model checker

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-07: EXEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 EF DL FNDP 40/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 615849104 t fired, 616 attempts, .

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lola: result : true
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lola: fired transitions : 268
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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/395 8/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06 1928838 m, 385767 m/sec, 8647143 t fired, .
41 EF DL FNDP 45/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 693485164 t fired, 694 attempts, .

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/395 15/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06 3607918 m, 335816 m/sec, 16186031 t fired, .
41 EF DL FNDP 50/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 771052556 t fired, 772 attempts, .

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/395 21/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06 5221844 m, 322785 m/sec, 23434908 t fired, .
41 EF DL FNDP 55/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 848660342 t fired, 849 attempts, .

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 20/395 28/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06 6867063 m, 329043 m/sec, 30825783 t fired, .
41 EF DL FNDP 60/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 926283305 t fired, 927 attempts, .

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 EF DL FNDP 65/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 1004217529 t fired, 1005 attempts, .

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/441 13/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-01 3100190 m, 620038 m/sec, 7705636 t fired, .
41 EF DL FNDP 70/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 1081656995 t fired, 1082 attempts, .

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/441 24/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-01 5753192 m, 530600 m/sec, 14315606 t fired, .
41 EF DL FNDP 75/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 1159069001 t fired, 1160 attempts, .

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04: AG NODL 0 1 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 EF DL FNDP 80/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 1236646753 t fired, 1237 attempts, .

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 EF DL EXCL 5/502 1/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 30995298 m, 6199059 m/sec, 30995298 t fired, .
41 EF DL FNDP 85/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 1314069970 t fired, 1315 attempts, .

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 EF DL EXCL 10/502 1/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 60481128 m, 5897166 m/sec, 60481127 t fired, .
41 EF DL FNDP 90/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 1391338254 t fired, 1392 attempts, .

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04: AG NODL 0 0 2 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 EF DL EXCL 15/502 1/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 89923237 m, 5888421 m/sec, 89923237 t fired, .
41 EF DL FNDP 95/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 1468600335 t fired, 1469 attempts, .

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04: AG NODL 0 0 2 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-10: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

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40 EF DL EXCL 20/502 1/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 119393910 m, 5894134 m/sec, 119393910 t fired, .
41 EF DL FNDP 100/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 1545844437 t fired, 1546 attempts, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 EF DL EXCL 25/502 1/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 148815891 m, 5884396 m/sec, 148815891 t fired, .
41 EF DL FNDP 105/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 1623117788 t fired, 1624 attempts, .

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40 EF DL EXCL 30/502 1/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 178203716 m, 5877565 m/sec, 178203716 t fired, .
41 EF DL FNDP 110/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 1700363559 t fired, 1701 attempts, .

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40 EF DL EXCL 35/502 1/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 207647521 m, 5888761 m/sec, 207647521 t fired, .
41 EF DL FNDP 115/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 1777546185 t fired, 1778 attempts, .

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40 EF DL EXCL 40/502 1/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 237078100 m, 5886115 m/sec, 237078100 t fired, .
41 EF DL FNDP 120/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 1854748183 t fired, 1855 attempts, .

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40 EF DL EXCL 45/502 1/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 266361746 m, 5856729 m/sec, 266361746 t fired, .
41 EF DL FNDP 125/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 1931933007 t fired, 1932 attempts, .

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40 EF DL EXCL 51/502 1/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 281575089 m, 3042668 m/sec, 281575090 t fired, .
41 EF DL FNDP 131/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 2018488735 t fired, 2019 attempts, .

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40 EF DL EXCL 56/502 1/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 292937281 m, 2272438 m/sec, 292937280 t fired, .
41 EF DL FNDP 136/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 2084225942 t fired, 2085 attempts, .

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40 EF DL EXCL 62/502 1/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 303320147 m, 2076573 m/sec, 303320146 t fired, .
41 EF DL FNDP 142/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 -2122006939 t fired, 2173 attempts, .

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40 EF DL EXCL 67/502 1/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 314412486 m, 2218467 m/sec, 314412485 t fired, .
41 EF DL FNDP 147/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 -2056731004 t fired, 2239 attempts, .

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40 EF DL EXCL 74/502 1/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 326775836 m, 2472670 m/sec, 326775835 t fired, .
41 EF DL FNDP 154/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 -1958982842 t fired, 2336 attempts, .

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40 EF DL EXCL 79/502 1/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 344387275 m, 3522287 m/sec, 344387274 t fired, .
41 EF DL FNDP 159/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 -1901035473 t fired, 2394 attempts, .

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40 EF DL EXCL 84/502 1/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 355909727 m, 2304490 m/sec, 355909727 t fired, .
41 EF DL FNDP 164/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 -1838089935 t fired, 2457 attempts, .

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SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-12: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 EF DL EXCL 89/502 1/32 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 361037628 m, 1025580 m/sec, 361037627 t fired, .
41 EF DL FNDP 169/3600 0/5 SmallOperatingSystem-PT-MT4096DC2048-CTLCardinality-04 -1765390936 t fired, 2530 attempts, .

Time elapsed: 169 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
/home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin//../BenchKit_head.sh: line 63: 474 Killed lola --conf=$BIN_DIR/configfiles/ctlcardinalityconf --formula=$DIR/CTLCardinality.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT4096DC2048"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmallOperatingSystem-PT-MT4096DC2048, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912647000129"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT4096DC2048.tgz
mv SmallOperatingSystem-PT-MT4096DC2048 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;