About the Execution of LoLa+red for SmallOperatingSystem-PT-MT4096DC1024
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3812.067 | 116611.00 | 119234.00 | 819.40 | TTTT?FFF?TF?T?F? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r455-smll-167912646900121.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmallOperatingSystem-PT-MT4096DC1024, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912646900121
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 472K
-rw-r--r-- 1 mcc users 8.8K Feb 25 12:51 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K Feb 25 12:51 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.6K Feb 25 12:50 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 25 12:50 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.7K Feb 25 17:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 17:08 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Feb 25 17:08 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:08 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.5K Feb 25 12:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 74K Feb 25 12:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 13K Feb 25 12:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 97K Feb 25 12:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 17:08 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 17:08 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 8.1K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-00
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-01
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-02
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-03
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-04
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-05
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-06
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-08
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-12
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-14
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15
=== Now, execution of the tool begins
BK_START 1679193947262
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT4096DC1024
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 02:45:50] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLCardinality, -timeout, 360, -rebuildPNML]
[2023-03-19 02:45:50] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 02:45:51] [INFO ] Load time of PNML (sax parser for PT used): 42 ms
[2023-03-19 02:45:51] [INFO ] Transformed 9 places.
[2023-03-19 02:45:51] [INFO ] Transformed 8 transitions.
[2023-03-19 02:45:51] [INFO ] Parsed PT model containing 9 places and 8 transitions and 27 arcs in 189 ms.
Parsed 16 properties from file /home/mcc/execution/CTLCardinality.xml in 31 ms.
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-12 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 20 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
// Phase 1: matrix 8 rows 9 cols
[2023-03-19 02:45:51] [INFO ] Computed 4 place invariants in 4 ms
[2023-03-19 02:45:51] [INFO ] Implicit Places using invariants in 228 ms returned []
[2023-03-19 02:45:51] [INFO ] Invariant cache hit.
[2023-03-19 02:45:51] [INFO ] Implicit Places using invariants and state equation in 57 ms returned []
Implicit Place search using SMT with State Equation took 349 ms to find 0 implicit places.
[2023-03-19 02:45:51] [INFO ] Invariant cache hit.
[2023-03-19 02:45:51] [INFO ] Dead Transitions using invariants and state equation in 50 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 423 ms. Remains : 9/9 places, 8/8 transitions.
Support contains 9 out of 9 places after structural reductions.
[2023-03-19 02:45:51] [INFO ] Flatten gal took : 29 ms
[2023-03-19 02:45:51] [INFO ] Flatten gal took : 9 ms
[2023-03-19 02:45:52] [INFO ] Input system was already deterministic with 8 transitions.
Incomplete random walk after 10252 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=250 ) properties (out of 88) seen :12
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 95 ms. (steps per millisecond=10 ) properties (out of 76) seen :1
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 52 ms. (steps per millisecond=19 ) properties (out of 75) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 54 ms. (steps per millisecond=18 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 49 ms. (steps per millisecond=20 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 62 ms. (steps per millisecond=16 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 59 ms. (steps per millisecond=16 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=23 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 59 ms. (steps per millisecond=16 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=24 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=23 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 42 ms. (steps per millisecond=23 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 35 ms. (steps per millisecond=28 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 72) seen :0
Running SMT prover for 72 properties.
[2023-03-19 02:45:53] [INFO ] Invariant cache hit.
[2023-03-19 02:45:53] [INFO ] [Real]Absence check using 4 positive place invariants in 2 ms returned sat
[2023-03-19 02:45:53] [INFO ] After 119ms SMT Verify possible using state equation in real domain returned unsat :29 sat :2 real:41
[2023-03-19 02:45:53] [INFO ] After 133ms SMT Verify possible using trap constraints in real domain returned unsat :29 sat :2 real:41
Attempting to minimize the solution found.
Minimization took 16 ms.
[2023-03-19 02:45:53] [INFO ] After 418ms SMT Verify possible using all constraints in real domain returned unsat :29 sat :2 real:41
[2023-03-19 02:45:54] [INFO ] [Nat]Absence check using 4 positive place invariants in 1 ms returned sat
[2023-03-19 02:45:54] [INFO ] After 163ms SMT Verify possible using state equation in natural domain returned unsat :34 sat :38
[2023-03-19 02:45:54] [INFO ] After 348ms SMT Verify possible using trap constraints in natural domain returned unsat :34 sat :38
Attempting to minimize the solution found.
Minimization took 154 ms.
[2023-03-19 02:45:54] [INFO ] After 732ms SMT Verify possible using all constraints in natural domain returned unsat :34 sat :38
Fused 72 Parikh solutions to 38 different solutions.
Finished Parikh walk after 15781 steps, including 0 resets, run visited all 1 properties in 16 ms. (steps per millisecond=986 )
Parikh walk visited 38 properties in 7403 ms.
Successfully simplified 34 atomic propositions for a total of 15 simplifications.
Initial state reduction rules removed 1 formulas.
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-03 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 02:46:02] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 7 ms
[2023-03-19 02:46:02] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-00 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 3 ms
[2023-03-19 02:46:02] [INFO ] Input system was already deterministic with 8 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 3 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:46:02] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 0 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:46:02] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 1 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:46:02] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:46:02] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 7 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 5 place count 5 transition count 6
Applied a total of 5 rules in 9 ms. Remains 5 /9 variables (removed 4) and now considering 6/8 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 5/9 places, 6/8 transitions.
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:46:02] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 7
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 2 rules applied. Total rules applied 3 place count 7 transition count 6
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 5 place count 5 transition count 6
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 3 rules applied. Total rules applied 8 place count 3 transition count 5
Graph (trivial) has 3 edges and 3 vertex of which 2 / 3 are part of one of the 1 SCC in 3 ms
Free SCC test removed 1 places
Iterating global reduction 3 with 1 rules applied. Total rules applied 9 place count 2 transition count 5
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 11 place count 2 transition count 3
Applied a total of 11 rules in 5 ms. Remains 2 /9 variables (removed 7) and now considering 3/8 (removed 5) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 2/9 places, 3/8 transitions.
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 0 ms
[2023-03-19 02:46:02] [INFO ] Input system was already deterministic with 3 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:46:02] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Applied a total of 0 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:46:02] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:46:02] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 0 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:46:02] [INFO ] Input system was already deterministic with 8 transitions.
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:46:02] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:46:02] [INFO ] Export to MCC of 10 properties in file /home/mcc/execution/CTLCardinality.sr.xml took 2 ms.
[2023-03-19 02:46:02] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9 places, 8 transitions and 27 arcs took 0 ms.
Total runtime 11391 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT4096DC1024
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679194063873
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 7 (type EXCL) for 6 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-05
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 35 (type FNDP) for 18 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 36 (type EQUN) for 18 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 38 (type SRCH) for 18 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 35 (type FNDP) for SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10
lola: result : true
lola: fired transitions : 1653
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 36 (type EQUN) for SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10 (obsolete)
lola: CANCELED task # 38 (type SRCH) for SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10 (obsolete)
lola: FINISHED task # 38 (type SRCH) for SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10
lola: result : unknown
lola: markings : 3
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
sara: try reading problem file /home/mcc/execution/375/CTLCardinality-36.sara.
lola: FINISHED task # 36 (type EQUN) for SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10
lola: result : true
lola: FINISHED task # 7 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-05
lola: result : false
lola: markings : 3157727
lola: fired transitions : 6311903
lola: time used : 5.000000
lola: memory pages used : 13
lola: LAUNCH task # 32 (type EXCL) for 31 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15
lola: time limit : 449 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-08: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 0/449 1/32 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15 18992 m, 3798 m/sec, 53755 t fired, .
Time elapsed: 5 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-08: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 5/449 7/32 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15 1615552 m, 319312 m/sec, 4475651 t fired, .
Time elapsed: 10 secs. Pages in use: 13
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-08: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 10/449 13/32 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15 3184589 m, 313807 m/sec, 8809571 t fired, .
Time elapsed: 15 secs. Pages in use: 13
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-08: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 15/449 19/32 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15 4666952 m, 296472 m/sec, 12901226 t fired, .
Time elapsed: 20 secs. Pages in use: 19
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-08: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 20/449 25/32 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15 6217062 m, 310022 m/sec, 17178390 t fired, .
Time elapsed: 25 secs. Pages in use: 25
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-08: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 25/449 32/32 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15 7740208 m, 304629 m/sec, 21380025 t fired, .
Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
lola: CANCELED task # 32 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-08: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 10
lola: LAUNCH task # 10 (type EXCL) for 9 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07
lola: time limit : 509 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07
lola: result : false
lola: markings : 5
lola: fired transitions : 19
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-04
lola: time limit : 594 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-08: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/594 15/32 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-04 3500133 m, 700026 m/sec, 7579846 t fired, .
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10: CONJ false findpath
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-08: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/594 30/32 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-04 7253937 m, 750760 m/sec, 15716920 t fired, .
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-08: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-08: EGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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1 CTL EXCL 5/710 11/32 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-02 2621402 m, 524280 m/sec, 7861212 t fired, .
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lola: result : true
lola: markings : 3354390
lola: fired transitions : 10061337
lola: time used : 7.000000
lola: memory pages used : 14
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-02: CTL true CTL model checker
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10: CONJ false findpath
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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40 LTL EXCL 3/885 12/32 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13 1774022 m, 354804 m/sec, 4404226 t fired, .
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10: CONJ false findpath
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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40 LTL EXCL 8/885 28/32 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13 4295866 m, 504368 m/sec, 10684163 t fired, .
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10: CONJ false findpath
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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13 CTL EXCL 5/1176 12/32 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-08 2720934 m, 544186 m/sec, 9058668 t fired, .
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10: CONJ false findpath
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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13 CTL EXCL 10/1176 23/32 SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-08 5600134 m, 575840 m/sec, 18768432 t fired, .
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07: CTL false CTL model checker
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09: AGEF 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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lola: result : true
lola: markings : 4097
lola: fired transitions : 8268
lola: time used : 0.000000
lola: memory pages used : 1
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-02: CTL true CTL model checker
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-09: AGEF true tscc_search
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10: CONJ false findpath
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07: CTL false CTL model checker
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07: CTL false CTL model checker
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL 0 0 0 0 1 0 1 0
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FINAL RESULTS
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-04: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-07: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-08: EGEF unknown AGGR
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SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-10: CONJ false findpath
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-11: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLCardinality-13: SP ECTL unknown AGGR
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT4096DC1024"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmallOperatingSystem-PT-MT4096DC1024, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912646900121"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT4096DC1024.tgz
mv SmallOperatingSystem-PT-MT4096DC1024 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;