About the Execution of LoLa+red for SmallOperatingSystem-PT-MT2048DC0512
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3579.396 | 132470.00 | 128975.00 | 991.30 | ?T?F?T?FFFFT?TT? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r455-smll-167912646900105.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmallOperatingSystem-PT-MT2048DC0512, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912646900105
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 424K
-rw-r--r-- 1 mcc users 9.0K Feb 25 12:44 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K Feb 25 12:44 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Feb 25 12:44 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 25 12:44 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.7K Feb 25 17:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 17:08 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Feb 25 17:08 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 17:08 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.0K Feb 25 12:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 56K Feb 25 12:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 12:45 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 78K Feb 25 12:45 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 17:08 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 17:08 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 8.1K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-00
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-01
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-02
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-03
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-04
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-05
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-08
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-09
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-10
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-11
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-14
FORMULA_NAME SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-15
=== Now, execution of the tool begins
BK_START 1679192825293
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT2048DC0512
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 02:27:09] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLCardinality, -timeout, 360, -rebuildPNML]
[2023-03-19 02:27:09] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 02:27:09] [INFO ] Load time of PNML (sax parser for PT used): 43 ms
[2023-03-19 02:27:09] [INFO ] Transformed 9 places.
[2023-03-19 02:27:09] [INFO ] Transformed 8 transitions.
[2023-03-19 02:27:09] [INFO ] Parsed PT model containing 9 places and 8 transitions and 27 arcs in 190 ms.
Parsed 16 properties from file /home/mcc/execution/CTLCardinality.xml in 33 ms.
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 18 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
// Phase 1: matrix 8 rows 9 cols
[2023-03-19 02:27:09] [INFO ] Computed 4 place invariants in 6 ms
[2023-03-19 02:27:09] [INFO ] Implicit Places using invariants in 233 ms returned []
[2023-03-19 02:27:09] [INFO ] Invariant cache hit.
[2023-03-19 02:27:09] [INFO ] Implicit Places using invariants and state equation in 55 ms returned []
Implicit Place search using SMT with State Equation took 346 ms to find 0 implicit places.
[2023-03-19 02:27:09] [INFO ] Invariant cache hit.
[2023-03-19 02:27:10] [INFO ] Dead Transitions using invariants and state equation in 51 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 418 ms. Remains : 9/9 places, 8/8 transitions.
Support contains 9 out of 9 places after structural reductions.
[2023-03-19 02:27:10] [INFO ] Flatten gal took : 30 ms
[2023-03-19 02:27:10] [INFO ] Flatten gal took : 10 ms
[2023-03-19 02:27:10] [INFO ] Input system was already deterministic with 8 transitions.
Incomplete random walk after 10262 steps, including 2 resets, run finished after 54 ms. (steps per millisecond=190 ) properties (out of 89) seen :24
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 86 ms. (steps per millisecond=11 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 74 ms. (steps per millisecond=13 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=24 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 61 ms. (steps per millisecond=16 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=26 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=25 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=26 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 52 ms. (steps per millisecond=19 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 53 ms. (steps per millisecond=18 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 47 ms. (steps per millisecond=21 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 65) seen :0
Running SMT prover for 65 properties.
[2023-03-19 02:27:11] [INFO ] Invariant cache hit.
[2023-03-19 02:27:12] [INFO ] [Real]Absence check using 4 positive place invariants in 2 ms returned sat
[2023-03-19 02:27:12] [INFO ] After 110ms SMT Verify possible using state equation in real domain returned unsat :28 sat :2 real:35
[2023-03-19 02:27:12] [INFO ] After 128ms SMT Verify possible using trap constraints in real domain returned unsat :28 sat :0 real:37
[2023-03-19 02:27:12] [INFO ] After 437ms SMT Verify possible using all constraints in real domain returned unsat :28 sat :0 real:37
[2023-03-19 02:27:12] [INFO ] [Nat]Absence check using 4 positive place invariants in 3 ms returned sat
[2023-03-19 02:27:12] [INFO ] After 136ms SMT Verify possible using state equation in natural domain returned unsat :32 sat :33
[2023-03-19 02:27:12] [INFO ] After 294ms SMT Verify possible using trap constraints in natural domain returned unsat :32 sat :33
Attempting to minimize the solution found.
Minimization took 130 ms.
[2023-03-19 02:27:12] [INFO ] After 646ms SMT Verify possible using all constraints in natural domain returned unsat :32 sat :33
Fused 65 Parikh solutions to 32 different solutions.
Finished Parikh walk after 7013 steps, including 0 resets, run visited all 1 properties in 9 ms. (steps per millisecond=779 )
Parikh walk visited 33 properties in 3075 ms.
Successfully simplified 32 atomic propositions for a total of 16 simplifications.
FORMULA SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-10 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 4 ms
[2023-03-19 02:27:16] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 3 ms
[2023-03-19 02:27:16] [INFO ] Input system was already deterministic with 8 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 0 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 2 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 1 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:27:16] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 0 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:27:16] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 7 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Applied a total of 2 rules in 7 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 0 ms
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 1 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 0 ms
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 0 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 7
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 2 rules applied. Total rules applied 3 place count 7 transition count 6
Reduce places removed 2 places and 0 transitions.
Graph (trivial) has 2 edges and 5 vertex of which 2 / 5 are part of one of the 1 SCC in 3 ms
Free SCC test removed 1 places
Iterating post reduction 2 with 3 rules applied. Total rules applied 6 place count 4 transition count 6
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 7 place count 4 transition count 5
Applied a total of 7 rules in 8 ms. Remains 4 /9 variables (removed 5) and now considering 5/8 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 4/9 places, 5/8 transitions.
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Input system was already deterministic with 5 transitions.
Finished random walk after 4100 steps, including 0 resets, run visited all 1 properties in 3 ms. (steps per millisecond=1366 )
FORMULA SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-14 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:27:16] [INFO ] Input system was already deterministic with 8 transitions.
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:27:16] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:27:16] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLCardinality.sr.xml took 2 ms.
[2023-03-19 02:27:16] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9 places, 8 transitions and 27 arcs took 1 ms.
Total runtime 6915 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT2048DC0512
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
FORMULA SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679192957763
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:227
lola: rewrite Frontend/Parser/formula_rewrite.k:114
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 4 (type EXCL) for 3 SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-02
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
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4 CTL EXCL 10/276 27/32 SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-02 6699958 m, 651570 m/sec, 16253875 t fired, .
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 15/324 23/32 SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12 5551443 m, 370336 m/sec, 13459236 t fired, .
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07: F 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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31 CTL EXCL 20/324 30/32 SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12 7418505 m, 373412 m/sec, 17969378 t fired, .
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07: F 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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lola: FINISHED task # 28 (type EXCL) for SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-11
lola: result : true
lola: markings : 436258
lola: fired transitions : 871855
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lola: result : true
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-05: CTL true CTL model checker
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-09: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07: F 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 4/590 7/32 SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-04 1635154 m, 327030 m/sec, 3906963 t fired, .
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-09: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-11: CTL true CTL model checker
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07: F 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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10 CTL EXCL 9/590 14/32 SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-04 3420734 m, 357116 m/sec, 8258760 t fired, .
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-11: CTL true CTL model checker
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07: F 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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10 CTL EXCL 14/590 21/32 SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-04 5165124 m, 348878 m/sec, 12497002 t fired, .
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07: F 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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10 CTL EXCL 19/590 28/32 SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-04 6886786 m, 344332 m/sec, 16675073 t fired, .
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-05: CTL true CTL model checker
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-09: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-11: CTL true CTL model checker
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-03: LTL/CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07: F 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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lola: result : false
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-03: LTL/CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-08: CTL false CTL model checker
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-00: CTL 0 0 1 0 1 0 0 0
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07: F 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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1 CTL EXCL 5/880 12/32 SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-00 2840885 m, 568177 m/sec, 7059921 t fired, .
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06: EFAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07: F 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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1 CTL EXCL 10/880 22/32 SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-00 5377100 m, 507243 m/sec, 13378507 t fired, .
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07: F 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06: EFAG 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07: F 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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40 AGEF EXCL 5/1168 9/32 SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06 2378186 m, 475637 m/sec, 9300650 t fired, .
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07: F 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
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40 AGEF EXCL 10/1168 17/32 SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06 4550366 m, 434436 m/sec, 17856530 t fired, .
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SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-09: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06: EFAG 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07: F 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 AGEF EXCL 15/1168 25/32 SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06 6632600 m, 416446 m/sec, 26060901 t fired, .
Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-03: LTL/CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-09: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06: EFAG 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07: F 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 AGEF EXCL 20/1168 32/32 SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06 8661642 m, 405808 m/sec, 34065729 t fired, .
Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 40 (type EXCL) for SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-03: LTL/CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-09: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-11: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07: F 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 39 (type EXCL) for 18 SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07
lola: time limit : 1740 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07
lola: result : true
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13
lola: time limit : 3480 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13
lola: result : true
lola: markings : 3
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 13
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-00: CTL unknown AGGR
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-02: CTL unknown AGGR
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-03: LTL/CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-04: CTL unknown AGGR
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-06: EFAG unknown AGGR
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-07: F false state space / EG
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-09: CTL false CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-11: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-12: CTL unknown AGGR
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-13: CTL true CTL model checker
SmallOperatingSystem-PT-MT2048DC0512-CTLCardinality-15: CTL unknown AGGR
Time elapsed: 120 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT2048DC0512"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmallOperatingSystem-PT-MT2048DC0512, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912646900105"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT2048DC0512.tgz
mv SmallOperatingSystem-PT-MT2048DC0512 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;