About the Execution of LoLa+red for SmallOperatingSystem-PT-MT1024DC0256
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 5513.035 | 182447.00 | 169088.00 | 1089.70 | ???FFT?TF?F??FTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r455-smll-167912646900090.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmallOperatingSystem-PT-MT1024DC0256, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912646900090
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 496K
-rw-r--r-- 1 mcc users 11K Feb 25 12:40 CTLCardinality.txt
-rw-r--r-- 1 mcc users 97K Feb 25 12:40 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.1K Feb 25 12:40 CTLFireability.txt
-rw-r--r-- 1 mcc users 70K Feb 25 12:40 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.9K Feb 25 17:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Feb 25 17:08 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Feb 25 17:08 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:08 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 12:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 110K Feb 25 12:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.3K Feb 25 12:41 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 48K Feb 25 12:41 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 17:08 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 17:08 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 8.1K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14
FORMULA_NAME SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679191540414
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT1024DC0256
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 02:05:43] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 02:05:44] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 02:05:44] [INFO ] Load time of PNML (sax parser for PT used): 41 ms
[2023-03-19 02:05:44] [INFO ] Transformed 9 places.
[2023-03-19 02:05:44] [INFO ] Transformed 8 transitions.
[2023-03-19 02:05:44] [INFO ] Parsed PT model containing 9 places and 8 transitions and 27 arcs in 203 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 30 ms.
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 20 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
// Phase 1: matrix 8 rows 9 cols
[2023-03-19 02:05:44] [INFO ] Computed 4 place invariants in 6 ms
[2023-03-19 02:05:44] [INFO ] Implicit Places using invariants in 230 ms returned []
[2023-03-19 02:05:44] [INFO ] Invariant cache hit.
[2023-03-19 02:05:44] [INFO ] Implicit Places using invariants and state equation in 58 ms returned []
Implicit Place search using SMT with State Equation took 353 ms to find 0 implicit places.
[2023-03-19 02:05:44] [INFO ] Invariant cache hit.
[2023-03-19 02:05:44] [INFO ] Dead Transitions using invariants and state equation in 56 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 431 ms. Remains : 9/9 places, 8/8 transitions.
Support contains 9 out of 9 places after structural reductions.
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 30 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 10 ms
[2023-03-19 02:05:45] [INFO ] Input system was already deterministic with 8 transitions.
Incomplete random walk after 10025 steps, including 2 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 27) seen :26
Finished Best-First random walk after 169 steps, including 0 resets, run visited all 1 properties in 25 ms. (steps per millisecond=6 )
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 6 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 7 ms
[2023-03-19 02:05:45] [INFO ] Input system was already deterministic with 8 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 6 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 3 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 3 ms
[2023-03-19 02:05:45] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 2 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 3 ms
[2023-03-19 02:05:45] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 3 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 2 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 5 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 2 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 3 ms
[2023-03-19 02:05:45] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 7 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Applied a total of 2 rules in 8 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 3 ms
[2023-03-19 02:05:45] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 2 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 6 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 1 ms
[2023-03-19 02:05:45] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 2 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 2 ms
[2023-03-19 02:05:45] [INFO ] Input system was already deterministic with 8 transitions.
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 4 ms
[2023-03-19 02:05:45] [INFO ] Flatten gal took : 4 ms
[2023-03-19 02:05:45] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 6 ms.
[2023-03-19 02:05:45] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9 places, 8 transitions and 27 arcs took 0 ms.
Total runtime 1840 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT1024DC0256
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679191722861
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 13 (type EXCL) for 12 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04
lola: time limit : 128 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 101 (type FNDP) for 31 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 102 (type EQUN) for 31 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 104 (type SRCH) for 31 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 104 (type SRCH) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 98 (type FNDP) for 31 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 101 (type FNDP) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 98 (type FNDP) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09 (obsolete)
lola: CANCELED task # 102 (type EQUN) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09 (obsolete)
lola: planning for (null) stopped (result already fixed).
lola: FINISHED task # 102 (type EQUN) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 98 (type FNDP) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ 0 3 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/156 3/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04 653360 m, 130672 m/sec, 3917507 t fired, .
Time elapsed: 5 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 13 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04
lola: result : false
lola: markings : 691073
lola: fired transitions : 4144139
lola: time used : 5.000000
lola: memory pages used : 3
lola: LAUNCH task # 94 (type EXCL) for 85 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: FINISHED task # 94 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15
lola: result : true
lola: markings : 8
lola: fired transitions : 10
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 92 (type EXCL) for 85 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: FINISHED task # 92 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 88 (type EXCL) for 85 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: FINISHED task # 88 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15
lola: result : true
lola: markings : 4
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 81 (type EXCL) for 78 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: FINISHED task # 81 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14
lola: result : true
lola: markings : 388963
lola: fired transitions : 841310
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 76 (type EXCL) for 71 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 76 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13
lola: result : false
lola: markings : 5
lola: fired transitions : 10
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 69 (type EXCL) for 68 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12
lola: time limit : 239 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
69 CTL EXCL 4/239 8/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12 1810463 m, 362092 m/sec, 4495043 t fired, .
Time elapsed: 10 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
69 CTL EXCL 9/239 16/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12 3973971 m, 432701 m/sec, 9882230 t fired, .
Time elapsed: 15 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
69 CTL EXCL 14/239 26/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12 6263187 m, 457843 m/sec, 15587075 t fired, .
Time elapsed: 20 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 69 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 26 (type EXCL) for 25 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07
lola: time limit : 255 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07
lola: result : true
lola: markings : 388888
lola: fired transitions : 841148
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 10 (type EXCL) for 9 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03
lola: time limit : 274 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03
lola: result : false
lola: markings : 1280
lola: fired transitions : 4096
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02
lola: time limit : 297 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 4/297 5/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02 1064945 m, 212989 m/sec, 4767151 t fired, .
Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 9/297 10/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02 2343734 m, 255757 m/sec, 10505813 t fired, .
Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 14/297 15/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02 3579549 m, 247163 m/sec, 16054378 t fired, .
Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 19/297 20/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02 4781527 m, 240395 m/sec, 21452747 t fired, .
Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 24/297 24/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02 5978197 m, 239334 m/sec, 26827630 t fired, .
Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 29/297 29/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02 7232671 m, 250894 m/sec, 32463261 t fired, .
Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 7 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 4 (type EXCL) for 3 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01
lola: time limit : 321 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/321 10/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01 2474279 m, 494855 m/sec, 7686006 t fired, .
Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/321 19/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01 4617580 m, 428660 m/sec, 14923576 t fired, .
Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/321 27/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01 6646942 m, 405872 m/sec, 21844078 t fired, .
Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 1 (type EXCL) for 0 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00
lola: time limit : 352 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/352 11/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00 2524733 m, 504946 m/sec, 8949925 t fired, .
Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/352 21/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00 5082739 m, 511601 m/sec, 17754722 t fired, .
Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/352 32/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00 7528165 m, 489085 m/sec, 26283021 t fired, .
Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 2 0 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 29 (type EXCL) for 28 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08
lola: time limit : 388 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08
lola: result : false
lola: markings : 257
lola: fired transitions : 256
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 63 (type EXCL) for 58 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10
lola: time limit : 437 sec
lola: memory limit: 32 pages
lola: FINISHED task # 63 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10
lola: result : false
lola: markings : 1024
lola: fired transitions : 2048
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 61 (type EXCL) for 58 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10
lola: time limit : 500 sec
lola: memory limit: 32 pages
lola: FINISHED task # 61 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10
lola: result : false
lola: markings : 4
lola: fired transitions : 17
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 56 (type EXCL) for 31 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09
lola: time limit : 583 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG false state space / EG
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ false DISJ
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 1 1 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 5/583 7/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09 1744326 m, 348865 m/sec, 7759818 t fired, .
Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG false state space / EG
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ false DISJ
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 1 1 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 10/583 15/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09 3492467 m, 349628 m/sec, 15573784 t fired, .
Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG false state space / EG
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ false DISJ
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 1 1 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 15/583 21/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09 5176312 m, 336769 m/sec, 23107557 t fired, .
Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG false state space / EG
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ false DISJ
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 1 1 0 12 0 0 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 20/583 28/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09 6869435 m, 338624 m/sec, 30687356 t fired, .
Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 56 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG false state space / EG
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ false DISJ
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 1 0 0 12 0 1 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 66 (type EXCL) for 65 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11
lola: time limit : 695 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG false state space / EG
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ false DISJ
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 1 0 0 12 0 1 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 5/695 8/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11 1891730 m, 378346 m/sec, 8769886 t fired, .
Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG false state space / EG
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ false DISJ
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 1 0 0 12 0 1 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 10/695 15/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11 3630396 m, 347733 m/sec, 17557370 t fired, .
Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG false state space / EG
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ false DISJ
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 1 0 0 12 0 1 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 15/695 21/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11 5109053 m, 295731 m/sec, 26143125 t fired, .
Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG false state space / EG
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ false DISJ
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 1 0 0 12 0 1 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 20/695 27/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11 6490263 m, 276242 m/sec, 34219673 t fired, .
Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG false state space / EG
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ false DISJ
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 1 0 0 12 0 1 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 25/695 32/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11 7822615 m, 266470 m/sec, 42028732 t fired, .
Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 66 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG false state space / EG
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ false DISJ
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 1 0 0 12 0 1 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 34 (type EXCL) for 31 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09
lola: time limit : 861 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09
lola: result : false
lola: markings : 3
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 18 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06
lola: time limit : 1148 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06
lola: result : false
lola: markings : 392034
lola: fired transitions : 1240000
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 21 (type EXCL) for 18 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06
lola: time limit : 1722 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG false state space / EG
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ false DISJ
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 0 1 0 3 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 0 0 0 13 0 1 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 4/1722 10/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06 2318808 m, 463761 m/sec, 7745331 t fired, .
Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG false state space / EG
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ false DISJ
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 0 1 0 3 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 0 0 0 13 0 1 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 9/1722 20/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06 4760123 m, 488263 m/sec, 16285713 t fired, .
Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG false state space / EG
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ false DISJ
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 0 1 0 3 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 0 0 0 13 0 1 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 14/1722 30/32 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06 7186595 m, 485294 m/sec, 24788626 t fired, .
Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 21 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG false state space / EG
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ false DISJ
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ 0 0 0 0 13 0 1 6
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 16 (type EXCL) for 15 SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05
lola: time limit : 3425 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05
lola: result : true
lola: markings : 513
lola: fired transitions : 514
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-00: CTL unknown AGGR
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-01: CTL unknown AGGR
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-02: CTL unknown AGGR
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-03: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-04: CTL false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-05: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-06: DISJ unknown DISJ
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-08: EG false state space / EG
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-09: DISJ unknown DISJ
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-10: DISJ false DISJ
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-11: CTL unknown AGGR
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-12: CTL unknown AGGR
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-13: CONJ false CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-14: DISJ true CTL model checker
SmallOperatingSystem-PT-MT1024DC0256-CTLFireability-15: CONJ true CONJ
Time elapsed: 175 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT1024DC0256"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmallOperatingSystem-PT-MT1024DC0256, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912646900090"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT1024DC0256.tgz
mv SmallOperatingSystem-PT-MT1024DC0256 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;