fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r455-smll-167912646900066
Last Updated
May 14, 2023

About the Execution of LoLa+red for SmallOperatingSystem-PT-MT0256DC0128

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
5539.371 202192.00 185095.00 1282.90 ?????TTTFF?FFTTT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r455-smll-167912646900066.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmallOperatingSystem-PT-MT0256DC0128, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912646900066
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 516K
-rw-r--r-- 1 mcc users 9.1K Feb 25 12:46 CTLCardinality.txt
-rw-r--r-- 1 mcc users 80K Feb 25 12:46 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Feb 25 12:46 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K Feb 25 12:46 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Feb 25 17:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 17:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 17:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 17:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 18K Feb 25 12:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 155K Feb 25 12:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.6K Feb 25 12:47 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 69K Feb 25 12:47 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 17:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 17:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 8.2K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-00
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-01
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-02
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-03
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-04
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-05
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-06
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-07
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-08
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-09
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-10
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-11
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-12
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-13
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-14
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679184636221

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT0256DC0128
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 00:10:39] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 00:10:39] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 00:10:39] [INFO ] Load time of PNML (sax parser for PT used): 40 ms
[2023-03-19 00:10:39] [INFO ] Transformed 9 places.
[2023-03-19 00:10:39] [INFO ] Transformed 8 transitions.
[2023-03-19 00:10:39] [INFO ] Parsed PT model containing 9 places and 8 transitions and 27 arcs in 189 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 25 ms.
FORMULA SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 19 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
// Phase 1: matrix 8 rows 9 cols
[2023-03-19 00:10:40] [INFO ] Computed 4 place invariants in 6 ms
[2023-03-19 00:10:40] [INFO ] Implicit Places using invariants in 205 ms returned []
[2023-03-19 00:10:40] [INFO ] Invariant cache hit.
[2023-03-19 00:10:40] [INFO ] Implicit Places using invariants and state equation in 60 ms returned []
Implicit Place search using SMT with State Equation took 327 ms to find 0 implicit places.
[2023-03-19 00:10:40] [INFO ] Invariant cache hit.
[2023-03-19 00:10:40] [INFO ] Dead Transitions using invariants and state equation in 52 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 400 ms. Remains : 9/9 places, 8/8 transitions.
Support contains 9 out of 9 places after structural reductions.
[2023-03-19 00:10:40] [INFO ] Flatten gal took : 27 ms
[2023-03-19 00:10:40] [INFO ] Flatten gal took : 9 ms
[2023-03-19 00:10:40] [INFO ] Input system was already deterministic with 8 transitions.
Incomplete random walk after 10057 steps, including 2 resets, run finished after 70 ms. (steps per millisecond=143 ) properties (out of 23) seen :22
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 64 ms. (steps per millisecond=156 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-19 00:10:41] [INFO ] Invariant cache hit.
[2023-03-19 00:10:41] [INFO ] After 37ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 1 atomic propositions for a total of 15 simplifications.
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 4 ms
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 5 ms
[2023-03-19 00:10:41] [INFO ] Input system was already deterministic with 8 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 6 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 3 ms
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 2 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 2 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 7
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Applied a total of 2 rules in 7 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 7
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 5 place count 5 transition count 6
Applied a total of 5 rules in 5 ms. Remains 5 /9 variables (removed 4) and now considering 6/8 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 5/9 places, 6/8 transitions.
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:10:41] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:10:41] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:10:41] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 8 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 8 transition count 7
Applied a total of 2 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 8/9 places, 7/8 transitions.
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 8 transition count 6
Reduce places removed 3 places and 0 transitions.
Graph (trivial) has 3 edges and 5 vertex of which 2 / 5 are part of one of the 1 SCC in 3 ms
Free SCC test removed 1 places
Iterating post reduction 1 with 4 rules applied. Total rules applied 6 place count 4 transition count 6
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 7 place count 4 transition count 5
Applied a total of 7 rules in 6 ms. Remains 4 /9 variables (removed 5) and now considering 5/8 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 4/9 places, 5/8 transitions.
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:10:41] [INFO ] Input system was already deterministic with 5 transitions.
Finished random walk after 1 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=0 )
FORMULA SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:10:41] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 8 transition count 6
Reduce places removed 3 places and 0 transitions.
Graph (trivial) has 3 edges and 5 vertex of which 2 / 5 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Iterating post reduction 1 with 4 rules applied. Total rules applied 6 place count 4 transition count 6
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 7 place count 4 transition count 5
Applied a total of 7 rules in 2 ms. Remains 4 /9 variables (removed 5) and now considering 5/8 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 4/9 places, 5/8 transitions.
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 0 ms
[2023-03-19 00:10:41] [INFO ] Input system was already deterministic with 5 transitions.
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 3 ms
[2023-03-19 00:10:41] [INFO ] Flatten gal took : 3 ms
[2023-03-19 00:10:41] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-19 00:10:41] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9 places, 8 transitions and 27 arcs took 1 ms.
Total runtime 1700 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT0256DC0128
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/372
CTLFireability

FORMULA SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679184838413

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/372/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/372/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/372/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
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lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:314
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lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:253
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lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
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lola: Rule S: 0 transitions removed,0 places removed
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lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 4 (type EXCL) for 3 SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-01
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

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SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-15: EG 0 1 0 0 1 0 0 0

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4 CTL EXCL 5/225 8/32 SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-01 1900059 m, 380011 m/sec, 8470621 t fired, .

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SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-15: EG 0 1 0 0 1 0 0 0

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4 CTL EXCL 10/225 16/32 SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-01 3834571 m, 386902 m/sec, 17367260 t fired, .

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4 CTL EXCL 15/225 23/32 SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-01 5734878 m, 380061 m/sec, 26390514 t fired, .

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4 CTL EXCL 20/225 31/32 SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-01 7681322 m, 389288 m/sec, 35624940 t fired, .

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lola: result : true
lola: markings : 3
lola: fired transitions : 7
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SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-13: CTL true CTL model checker

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SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-15: EG 0 1 0 0 1 0 0 0

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42 CTL EXCL 5/255 7/32 SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-11 1516715 m, 303343 m/sec, 6646320 t fired, .

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42 CTL EXCL 10/255 13/32 SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-11 3061744 m, 309005 m/sec, 13500010 t fired, .

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42 CTL EXCL 15/255 20/32 SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-11 4637972 m, 315245 m/sec, 20487493 t fired, .

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SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-06: CONJ 0 3 0 0 3 0 0 0
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SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-15: EG 0 1 0 0 1 0 0 0

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42 CTL EXCL 20/255 26/32 SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-11 6220702 m, 316546 m/sec, 28266497 t fired, .

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SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-09: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-13: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-15: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-10: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 10/3440 20/32 SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-10 4810360 m, 465346 m/sec, 16776427 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-05: AGEF true tscc_search
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-06: CONJ true CONJ
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-09: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-13: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-15: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-10: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 15/3440 23/32 SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-10 5657857 m, 169499 m/sec, 24072976 t fired, .

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SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-05: AGEF true tscc_search
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-06: CONJ true CONJ
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-09: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-13: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-15: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-10: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 20/3440 23/32 SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-10 5657857 m, 0 m/sec, 32010900 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-05: AGEF true tscc_search
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-06: CONJ true CONJ
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-09: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-13: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-15: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-10: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 25/3440 24/32 SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-10 5789441 m, 26316 m/sec, 40064521 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-05: AGEF true tscc_search
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-06: CONJ true CONJ
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-09: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-13: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-15: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-10: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 30/3440 30/32 SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-10 7319402 m, 305992 m/sec, 49155638 t fired, .

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lola: CANCELED task # 39 (type EXCL) for SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-05: AGEF true tscc_search
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-06: CONJ true CONJ
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-09: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-13: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-15: EG true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-10: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-00: CTL unknown AGGR
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-01: CTL unknown AGGR
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-02: CTL unknown AGGR
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-03: CTL unknown AGGR
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-04: CTL unknown AGGR
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-05: AGEF true tscc_search
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-06: CONJ true CONJ
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-07: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-08: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-09: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-10: CTL unknown AGGR
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-11: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-13: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0128-CTLFireability-15: EG true state space / EG


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT0256DC0128"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmallOperatingSystem-PT-MT0256DC0128, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912646900066"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT0256DC0128.tgz
mv SmallOperatingSystem-PT-MT0256DC0128 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;