fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r455-smll-167912646900058
Last Updated
May 14, 2023

About the Execution of LoLa+red for SmallOperatingSystem-PT-MT0256DC0064

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
4881.684 147095.00 140477.00 1114.40 TFT?????TFF?FTFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r455-smll-167912646900058.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SmallOperatingSystem-PT-MT0256DC0064, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r455-smll-167912646900058
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 500K
-rw-r--r-- 1 mcc users 8.0K Feb 25 12:48 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Feb 25 12:48 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Feb 25 12:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 25 12:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.7K Feb 25 17:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 17:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 17:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 17:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 25 12:49 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 138K Feb 25 12:49 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 25 12:48 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 84K Feb 25 12:48 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 17:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 17:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 8.1K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-00
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-01
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-02
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-03
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-04
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-05
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-06
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-07
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-08
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-09
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-10
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-11
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-12
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-13
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-14
FORMULA_NAME SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679184134408

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT0256DC0064
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 00:02:17] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 00:02:17] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 00:02:18] [INFO ] Load time of PNML (sax parser for PT used): 41 ms
[2023-03-19 00:02:18] [INFO ] Transformed 9 places.
[2023-03-19 00:02:18] [INFO ] Transformed 8 transitions.
[2023-03-19 00:02:18] [INFO ] Parsed PT model containing 9 places and 8 transitions and 27 arcs in 186 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 25 ms.
Initial state reduction rules removed 3 formulas.
FORMULA SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 9 out of 9 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 19 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
// Phase 1: matrix 8 rows 9 cols
[2023-03-19 00:02:18] [INFO ] Computed 4 place invariants in 6 ms
[2023-03-19 00:02:18] [INFO ] Implicit Places using invariants in 226 ms returned []
[2023-03-19 00:02:18] [INFO ] Invariant cache hit.
[2023-03-19 00:02:18] [INFO ] Implicit Places using invariants and state equation in 55 ms returned []
Implicit Place search using SMT with State Equation took 354 ms to find 0 implicit places.
[2023-03-19 00:02:18] [INFO ] Invariant cache hit.
[2023-03-19 00:02:18] [INFO ] Dead Transitions using invariants and state equation in 63 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 459 ms. Remains : 9/9 places, 8/8 transitions.
Support contains 9 out of 9 places after structural reductions.
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 28 ms
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 10 ms
[2023-03-19 00:02:19] [INFO ] Input system was already deterministic with 8 transitions.
Finished random walk after 1363 steps, including 0 resets, run visited all 17 properties in 62 ms. (steps per millisecond=21 )
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 4 ms
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 5 ms
[2023-03-19 00:02:19] [INFO ] Input system was already deterministic with 8 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 11 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:02:19] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 3 ms
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 8 ms
[2023-03-19 00:02:19] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 3 ms
[2023-03-19 00:02:19] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 3 ms
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 9 ms
[2023-03-19 00:02:19] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 5 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 3 ms
[2023-03-19 00:02:19] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:02:19] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Applied a total of 0 rules in 5 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:02:19] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 7 transition count 7
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 7 transition count 7
Applied a total of 2 rules in 2 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:02:19] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 9 /9 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 9/9 places, 8/8 transitions.
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:02:19] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 1 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:02:19] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:02:19] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Applied a total of 1 rules in 1 ms. Remains 8 /9 variables (removed 1) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 8/9 places, 8/8 transitions.
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:02:19] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 9/9 places, 8/8 transitions.
Ensure Unique test removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 8 transition count 8
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 7 transition count 7
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 7 transition count 7
Applied a total of 3 rules in 1 ms. Remains 7 /9 variables (removed 2) and now considering 7/8 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 7/9 places, 7/8 transitions.
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 1 ms
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:02:19] [INFO ] Input system was already deterministic with 7 transitions.
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 3 ms
[2023-03-19 00:02:19] [INFO ] Flatten gal took : 2 ms
[2023-03-19 00:02:19] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-19 00:02:19] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9 places, 8 transitions and 27 arcs took 1 ms.
Total runtime 1754 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT0256DC0064
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/363
CTLFireability

FORMULA SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679184281503

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/363/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/363/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/363/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: RELEASE
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lola: RELEASE
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lola: RELEASE
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lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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22 CTL EXCL 5/355 8/32 SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-03 1917391 m, 383478 m/sec, 8927992 t fired, .

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33 CTL EXCL 3/1175 7/32 SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-06 1592078 m, 318415 m/sec, 4266947 t fired, .

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33 CTL EXCL 8/1175 17/32 SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-06 4144327 m, 510449 m/sec, 11695353 t fired, .

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33 CTL EXCL 13/1175 27/32 SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-06 6575423 m, 486219 m/sec, 18728874 t fired, .

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SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-15: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-03: DISJ 0 0 0 0 5 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-06: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/3489 6/32 SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-04 1462138 m, 292427 m/sec, 8990307 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-00: DISJ true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-01: EG false state space / EG
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-15: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-03: DISJ 0 0 0 0 5 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-06: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 10/3489 12/32 SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-04 2914092 m, 290390 m/sec, 18110282 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-00: DISJ true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-01: EG false state space / EG
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-15: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-03: DISJ 0 0 0 0 5 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-06: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 15/3489 18/32 SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-04 4251097 m, 267401 m/sec, 26624872 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-00: DISJ true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-01: EG false state space / EG
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-15: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-03: DISJ 0 0 0 0 5 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-06: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 20/3489 23/32 SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-04 5568400 m, 263460 m/sec, 35029425 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-00: DISJ true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-01: EG false state space / EG
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-15: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-03: DISJ 0 0 0 0 5 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-06: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 25/3489 28/32 SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-04 6852080 m, 256736 m/sec, 43307951 t fired, .

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lola: CANCELED task # 25 (type EXCL) for SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-00: DISJ true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-01: EG false state space / EG
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-15: CONJ false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-03: DISJ 0 0 0 0 5 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-06: CONJ 0 0 0 0 3 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-11: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-00: DISJ true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-01: EG false state space / EG
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-03: DISJ unknown DISJ
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-04: CTL unknown AGGR
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-05: CTL unknown AGGR
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-06: CONJ unknown CONJ
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-07: CTL unknown AGGR
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-11: CTL unknown AGGR
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT0256DC0064-CTLFireability-15: CONJ false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT0256DC0064"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SmallOperatingSystem-PT-MT0256DC0064, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r455-smll-167912646900058"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT0256DC0064.tgz
mv SmallOperatingSystem-PT-MT0256DC0064 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;