About the Execution of LoLA for StigmergyElection-PT-11a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4690.172 | 393715.00 | 490013.00 | 1760.00 | FFFTTFFFFFFFFTTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r454-smll-167912646800700.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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Generated by BenchKit 2-5348
Executing tool lola
Input is StigmergyElection-PT-11a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r454-smll-167912646800700
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preparation of the directory to be used:
/home/mcc/execution
total 154M
-rw-r--r-- 1 mcc users 7.6K Feb 26 17:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 85K Feb 26 17:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Feb 26 16:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 16:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 17:15 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 17:15 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 17:15 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:15 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 18:07 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 144K Feb 26 18:07 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.4K Feb 26 17:35 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 57K Feb 26 17:35 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 17:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 17:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 153M Mar 5 18:23 model.pnml
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content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-00
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-01
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-02
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-03
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-04
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-05
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-06
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-07
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-08
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-09
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-10
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-11
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-12
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-13
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-14
FORMULA_NAME StigmergyElection-PT-11a-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1679492329327
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=StigmergyElection-PT-11a
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT StigmergyElection-PT-11a
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability
FORMULA StigmergyElection-PT-11a-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA StigmergyElection-PT-11a-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679492723042
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:518
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:418
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: Created skeleton in 3.000000 secs.
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StigmergyElection-PT-11a-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-04: F 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-06: CONJ 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
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StigmergyElection-PT-11a-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-12: AG 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-13: F 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
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StigmergyElection-PT-11a-LTLFireability-04: F 0 0 0 0 0 0 0 0
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StigmergyElection-PT-11a-LTLFireability-06: CONJ 0 0 0 0 0 0 0 0
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StigmergyElection-PT-11a-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-12: AG 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-13: F 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
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StigmergyElection-PT-11a-LTLFireability-12: AG 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-13: F 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
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StigmergyElection-PT-11a-LTLFireability-06: CONJ 0 0 0 0 2 0 0 0
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StigmergyElection-PT-11a-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
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StigmergyElection-PT-11a-LTLFireability-12: AG 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-13: F 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
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StigmergyElection-PT-11a-LTLFireability-13: F 0 0 0 0 0 0 0 0
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StigmergyElection-PT-11a-LTLFireability-13: F 0 0 0 0 0 0 0 0
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StigmergyElection-PT-11a-LTLFireability-10: CONJ 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-12: AG 0 0 0 0 0 0 0 0
StigmergyElection-PT-11a-LTLFireability-13: F 0 0 0 0 0 0 0 0
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StigmergyElection-PT-11a-LTLFireability-04: F 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-06: CONJ 0 0 0 0 2 0 0 0
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
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StigmergyElection-PT-11a-LTLFireability-14: LTL true LTL model checker
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StigmergyElection-PT-11a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-04: F 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-13: F 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 61/365 5/32 StigmergyElection-PT-11a-LTLFireability-03 668478 m, 11774 m/sec, 9669074 t fired, .
Time elapsed: 371 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 10 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-03
lola: result : true
lola: markings : 712694
lola: fired transitions : 10400846
lola: time used : 65.000000
lola: memory pages used : 5
lola: LAUNCH task # 4 (type EXCL) for 3 StigmergyElection-PT-11a-LTLFireability-01
lola: time limit : 403 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-01
lola: result : false
lola: markings : 24
lola: fired transitions : 24
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 StigmergyElection-PT-11a-LTLFireability-00
lola: time limit : 460 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyElection-PT-11a-LTLFireability-01: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-03: LTL true LTL model checker
StigmergyElection-PT-11a-LTLFireability-05: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-06: CONJ false LTL model checker
StigmergyElection-PT-11a-LTLFireability-07: CONJ false LTL model checker
StigmergyElection-PT-11a-LTLFireability-10: CONJ false findpath
StigmergyElection-PT-11a-LTLFireability-11: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-12: AG false findpath
StigmergyElection-PT-11a-LTLFireability-14: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyElection-PT-11a-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-04: F 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-13: F 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 LTL EXCL 1/460 1/32 StigmergyElection-PT-11a-LTLFireability-00 13950 m, 2790 m/sec, 87020 t fired, .
Time elapsed: 376 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyElection-PT-11a-LTLFireability-01: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-03: LTL true LTL model checker
StigmergyElection-PT-11a-LTLFireability-05: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-06: CONJ false LTL model checker
StigmergyElection-PT-11a-LTLFireability-07: CONJ false LTL model checker
StigmergyElection-PT-11a-LTLFireability-10: CONJ false findpath
StigmergyElection-PT-11a-LTLFireability-11: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-12: AG false findpath
StigmergyElection-PT-11a-LTLFireability-14: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyElection-PT-11a-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-04: F 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-13: F 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 LTL EXCL 6/460 1/32 StigmergyElection-PT-11a-LTLFireability-00 68653 m, 10940 m/sec, 473247 t fired, .
Time elapsed: 381 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyElection-PT-11a-LTLFireability-01: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-03: LTL true LTL model checker
StigmergyElection-PT-11a-LTLFireability-05: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-06: CONJ false LTL model checker
StigmergyElection-PT-11a-LTLFireability-07: CONJ false LTL model checker
StigmergyElection-PT-11a-LTLFireability-10: CONJ false findpath
StigmergyElection-PT-11a-LTLFireability-11: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-12: AG false findpath
StigmergyElection-PT-11a-LTLFireability-14: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyElection-PT-11a-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-04: F 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-13: F 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 LTL EXCL 11/460 1/32 StigmergyElection-PT-11a-LTLFireability-00 129862 m, 12241 m/sec, 928483 t fired, .
Time elapsed: 386 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 1 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-00
lola: result : false
lola: markings : 177177
lola: fired transitions : 1299136
lola: time used : 15.000000
lola: memory pages used : 2
lola: LAUNCH task # 62 (type EXCL) for 51 StigmergyElection-PT-11a-LTLFireability-13
lola: time limit : 535 sec
lola: memory limit: 32 pages
lola: FINISHED task # 62 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-13
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 61 (type EXCL) for 12 StigmergyElection-PT-11a-LTLFireability-04
lola: time limit : 642 sec
lola: memory limit: 32 pages
lola: FINISHED task # 61 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-04
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 33 (type EXCL) for 32 StigmergyElection-PT-11a-LTLFireability-08
lola: time limit : 802 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-08
lola: result : false
lola: markings : 15
lola: fired transitions : 17
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 35 StigmergyElection-PT-11a-LTLFireability-09
lola: time limit : 1070 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyElection-PT-11a-LTLFireability-00: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-01: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-03: LTL true LTL model checker
StigmergyElection-PT-11a-LTLFireability-04: F true state space / EG
StigmergyElection-PT-11a-LTLFireability-05: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-06: CONJ false LTL model checker
StigmergyElection-PT-11a-LTLFireability-07: CONJ false LTL model checker
StigmergyElection-PT-11a-LTLFireability-08: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-10: CONJ false findpath
StigmergyElection-PT-11a-LTLFireability-11: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-12: AG false findpath
StigmergyElection-PT-11a-LTLFireability-13: F true state space / EG
StigmergyElection-PT-11a-LTLFireability-14: LTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
StigmergyElection-PT-11a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
StigmergyElection-PT-11a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 LTL EXCL 1/1070 1/32 StigmergyElection-PT-11a-LTLFireability-09 5071 m, 1014 m/sec, 5072 t fired, .
Time elapsed: 391 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 36 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-09
lola: result : false
lola: markings : 12333
lola: fired transitions : 32881
lola: time used : 3.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 StigmergyElection-PT-11a-LTLFireability-02
lola: time limit : 1603 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-02
lola: result : false
lola: markings : 12
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 58 (type EXCL) for 57 StigmergyElection-PT-11a-LTLFireability-15
lola: time limit : 3207 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type EXCL) for StigmergyElection-PT-11a-LTLFireability-15
lola: result : false
lola: markings : 2064
lola: fired transitions : 20491
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
StigmergyElection-PT-11a-LTLFireability-00: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-01: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-02: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-03: LTL true LTL model checker
StigmergyElection-PT-11a-LTLFireability-04: F true state space / EG
StigmergyElection-PT-11a-LTLFireability-05: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-06: CONJ false LTL model checker
StigmergyElection-PT-11a-LTLFireability-07: CONJ false LTL model checker
StigmergyElection-PT-11a-LTLFireability-08: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-09: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-10: CONJ false findpath
StigmergyElection-PT-11a-LTLFireability-11: LTL false LTL model checker
StigmergyElection-PT-11a-LTLFireability-12: AG false findpath
StigmergyElection-PT-11a-LTLFireability-13: F true state space / EG
StigmergyElection-PT-11a-LTLFireability-14: LTL true LTL model checker
StigmergyElection-PT-11a-LTLFireability-15: LTL false LTL model checker
Time elapsed: 393 secs. Pages in use: 8
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="StigmergyElection-PT-11a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is StigmergyElection-PT-11a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r454-smll-167912646800700"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/StigmergyElection-PT-11a.tgz
mv StigmergyElection-PT-11a execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;