fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r454-smll-167912646000132
Last Updated
May 14, 2023

About the Execution of LoLA for SmallOperatingSystem-PT-MT4096DC2048

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
1830.623 26243.00 21662.00 234.70 FFFTFFTFFF?FFFFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r454-smll-167912646000132.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is SmallOperatingSystem-PT-MT4096DC2048, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r454-smll-167912646000132
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 448K
-rw-r--r-- 1 mcc users 8.6K Feb 25 12:48 CTLCardinality.txt
-rw-r--r-- 1 mcc users 75K Feb 25 12:48 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.3K Feb 25 12:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K Feb 25 12:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.5K Feb 25 17:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 17:08 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Feb 25 17:08 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:08 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 12:49 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 105K Feb 25 12:49 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.5K Feb 25 12:49 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 50K Feb 25 12:49 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 17:08 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 17:08 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 8.1K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-00
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-01
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-02
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-03
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-04
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-05
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-06
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-07
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-08
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-09
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-10
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-11
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-12
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-13
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-14
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1679214855680

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT4096DC2048
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT4096DC2048
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability

FORMULA SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679214881923

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:427
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 10 (type EXCL) for 9 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-03
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 49 (type FNDP) for 42 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type EQUN) for 42 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 52 (type SRCH) for 42 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 52 (type SRCH) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-14
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 49 (type FNDP) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-14
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 50 (type EQUN) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-14 (obsolete)
lola: FINISHED task # 50 (type EQUN) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-14
lola: result : unknown
lola: FINISHED task # 10 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-03
lola: result : true
lola: markings : 8192
lola: fired transitions : 12284
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 46 (type EXCL) for 45 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-15
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 46 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-15
lola: result : false
lola: markings : 10240
lola: fired transitions : 10240
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-12
lola: time limit : 276 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-03: LTL true LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-14: AG false findpath
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-13: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 LTL EXCL 5/276 19/32 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-12 2693278 m, 538655 m/sec, 5378799 t fired, .

Time elapsed: 5 secs. Pages in use: 19
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lola: FINISHED task # 37 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-12
lola: result : false
lola: markings : 4212735
lola: fired transitions : 8411813
lola: time used : 8.000000
lola: memory pages used : 29
lola: LAUNCH task # 34 (type EXCL) for 33 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-11
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-11
lola: result : false
lola: markings : 8194
lola: fired transitions : 8194
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-10
lola: time limit : 326 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-03: LTL true LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-11: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-12: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-14: AG false findpath
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-13: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 LTL EXCL 2/326 10/32 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-10 1415749 m, 283149 m/sec, 2823532 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-03: LTL true LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-11: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-12: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-14: AG false findpath
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-13: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 LTL EXCL 7/326 32/32 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-10 4789230 m, 674696 m/sec, 9571050 t fired, .

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lola: CANCELED task # 31 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-03: LTL true LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-11: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-12: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-14: AG false findpath
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-13: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 20 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 28 (type EXCL) for 27 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-09
lola: time limit : 358 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-09
lola: result : false
lola: markings : 16377
lola: fired transitions : 26601
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-06
lola: time limit : 397 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-06
lola: result : true
lola: markings : 12286
lola: fired transitions : 20467
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-05
lola: time limit : 447 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-05
lola: result : false
lola: markings : 8194
lola: fired transitions : 8194
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-04
lola: time limit : 511 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-04
lola: result : false
lola: markings : 8195
lola: fired transitions : 8195
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-02
lola: time limit : 596 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-03: LTL true LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-04: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-05: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-06: LTL true LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-09: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-11: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-12: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-14: AG false findpath
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-02: LTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-13: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 5/596 23/32 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-02 3464902 m, 692980 m/sec, 6922171 t fired, .

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lola: FINISHED task # 7 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-02
lola: result : false
lola: markings : 4212737
lola: fired transitions : 8411816
lola: time used : 6.000000
lola: memory pages used : 28
lola: LAUNCH task # 1 (type EXCL) for 0 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-00
lola: time limit : 714 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-00
lola: result : false
lola: markings : 8194
lola: fired transitions : 8194
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-08
lola: time limit : 893 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-08
lola: result : false
lola: markings : 8195
lola: fired transitions : 8196
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-07
lola: time limit : 1191 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-07
lola: result : false
lola: markings : 4
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-01
lola: time limit : 1787 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-01
lola: result : false
lola: markings : 4097
lola: fired transitions : 4097
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 39 SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-13
lola: time limit : 3574 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-13
lola: result : false
lola: markings : 8193
lola: fired transitions : 8193
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-00: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-01: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-02: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-03: LTL true LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-04: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-05: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-06: LTL true LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-07: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-08: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-09: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-10: LTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-11: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-12: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-13: LTL false LTL model checker
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-14: AG false findpath
SmallOperatingSystem-PT-MT4096DC2048-LTLFireability-15: LTL false LTL model checker


Time elapsed: 26 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT4096DC2048"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is SmallOperatingSystem-PT-MT4096DC2048, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r454-smll-167912646000132"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT4096DC2048.tgz
mv SmallOperatingSystem-PT-MT4096DC2048 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;