About the Execution of LoLA for SmallOperatingSystem-PT-MT4096DC1024
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4450.947 | 160415.00 | 147740.00 | 655.40 | ??TF?FT?TFF?FFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r454-smll-167912646000122.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is SmallOperatingSystem-PT-MT4096DC1024, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r454-smll-167912646000122
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 472K
-rw-r--r-- 1 mcc users 8.8K Feb 25 12:51 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K Feb 25 12:51 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.6K Feb 25 12:50 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 25 12:50 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.7K Feb 25 17:08 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 17:08 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Feb 25 17:08 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:08 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.5K Feb 25 12:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 74K Feb 25 12:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 13K Feb 25 12:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 97K Feb 25 12:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 17:08 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 17:08 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 8.1K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679210328558
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SmallOperatingSystem-PT-MT4096DC1024
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT4096DC1024
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679210488973
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: Created skeleton in 0.000000 secs.
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lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 43 (type EXCL) for 42 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: FINISHED task # 43 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 40 (type EXCL) for 39 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:737
lola: rewrite Frontend/Parser/formula_rewrite.k:693
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 40 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13
lola: result : false
lola: markings : 8194
lola: fired transitions : 54286
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 50 (type EXCL) for 45 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15
lola: result : false
lola: markings : 3152895
lola: fired transitions : 6315006
lola: time used : 5.000000
lola: memory pages used : 14
lola: LAUNCH task # 34 (type EXCL) for 33 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11
lola: time limit : 276 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 0/276 1/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11 34819 m, 6963 m/sec, 97300 t fired, .
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 5/276 10/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11 1978784 m, 388793 m/sec, 5929827 t fired, .
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 10/276 15/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11 3152893 m, 234821 m/sec, 11716795 t fired, .
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 15/276 15/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11 3164641 m, 2349 m/sec, 18930074 t fired, .
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 20/276 21/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11 4640343 m, 295140 m/sec, 23357662 t fired, .
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
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22 CTL EXCL 35/296 32/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07 7591557 m, 257358 m/sec, 49819275 t fired, .
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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lola: result : true
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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lola: FINISHED task # 16 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05
lola: result : false
lola: markings : 1024
lola: fired transitions : 1023
lola: time used : 0.000000
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lola: result : true
lola: markings : 2049
lola: fired transitions : 2050
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/438 10/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01 2034502 m, 406900 m/sec, 6095973 t fired, .
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/438 19/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01 4349765 m, 463052 m/sec, 11838473 t fired, .
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/438 27/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01 6304765 m, 391000 m/sec, 17286937 t fired, .
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/438 27/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01 6304765 m, 0 m/sec, 24944618 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/497 21/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00 4783670 m, 956734 m/sec, 5995393 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG 0 1 0 0 1 0 0 0
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lola: FINISHED task # 28 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09
lola: result : false
lola: markings : 1025
lola: fired transitions : 1024
lola: time used : 0.000000
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lola: LAUNCH task # 10 (type EXCL) for 9 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03
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lola: result : false
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lola: fired transitions : 1024
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lola: result : false
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lola: FINISHED task # 52 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10
lola: result : true
lola: markings : 1024
lola: fired transitions : 1023
lola: time used : 0.000000
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lola: result : true
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lola: fired transitions : 10247
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR false state space /EU
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/3475 5/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04 1077426 m, 215485 m/sec, 5383377 t fired, .
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR false state space /EU
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/3475 10/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04 2171853 m, 218885 m/sec, 10855869 t fired, .
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR false state space /EU
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/3475 14/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04 3160065 m, 197642 m/sec, 16025178 t fired, .
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR false state space /EU
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR false state space /EU
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/3475 24/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04 5530493 m, 474085 m/sec, 32357749 t fired, .
Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR false state space /EU
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 30/3475 30/32 SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04 7066981 m, 307297 m/sec, 38489071 t fired, .
Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 13 (type EXCL) for SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR false state space /EU
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-00: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-01: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-02: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-03: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-04: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-05: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-06: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-07: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-08: CTL true CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-09: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-10: AR false state space /EU
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-11: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-12: EG false state space / EG
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC1024-CTLFireability-15: CONJ false CTL model checker
Time elapsed: 160 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT4096DC1024"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is SmallOperatingSystem-PT-MT4096DC1024, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r454-smll-167912646000122"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT4096DC1024.tgz
mv SmallOperatingSystem-PT-MT4096DC1024 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;