Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/mnt/tpsp/fkordon/mcc2023-input.r423-tajo-167905976800482.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2023-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SieveSingleMsgMbox-PT-d2m64, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-tajo-167905976800482
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.5M
-rw-r--r-- 1 mcc users 6.0K Feb 26 10:30 CTLCardinality.txt
-rw-r--r-- 1 mcc users 57K Feb 26 10:30 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 26 10:29 CTLFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 26 10:29 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 17:06 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 17:06 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 17:06 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 17:06 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 10:32 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 116K Feb 26 10:32 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Feb 26 10:32 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 26 10:32 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:06 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 17:06 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 1.1M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SieveSingleMsgMbox-PT-d2m64-CTLFireability-00
FORMULA_NAME SieveSingleMsgMbox-PT-d2m64-CTLFireability-01
FORMULA_NAME SieveSingleMsgMbox-PT-d2m64-CTLFireability-02
FORMULA_NAME SieveSingleMsgMbox-PT-d2m64-CTLFireability-03
FORMULA_NAME SieveSingleMsgMbox-PT-d2m64-CTLFireability-04
FORMULA_NAME SieveSingleMsgMbox-PT-d2m64-CTLFireability-05
FORMULA_NAME SieveSingleMsgMbox-PT-d2m64-CTLFireability-06
FORMULA_NAME SieveSingleMsgMbox-PT-d2m64-CTLFireability-07
FORMULA_NAME SieveSingleMsgMbox-PT-d2m64-CTLFireability-08
FORMULA_NAME SieveSingleMsgMbox-PT-d2m64-CTLFireability-09
FORMULA_NAME SieveSingleMsgMbox-PT-d2m64-CTLFireability-10
FORMULA_NAME SieveSingleMsgMbox-PT-d2m64-CTLFireability-11
FORMULA_NAME SieveSingleMsgMbox-PT-d2m64-CTLFireability-12
FORMULA_NAME SieveSingleMsgMbox-PT-d2m64-CTLFireability-13
FORMULA_NAME SieveSingleMsgMbox-PT-d2m64-CTLFireability-14
FORMULA_NAME SieveSingleMsgMbox-PT-d2m64-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679248998762

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SieveSingleMsgMbox-PT-d2m64
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 18:03:20] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 18:03:20] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 18:03:20] [INFO ] Load time of PNML (sax parser for PT used): 121 ms
[2023-03-19 18:03:20] [INFO ] Transformed 2398 places.
[2023-03-19 18:03:20] [INFO ] Transformed 1954 transitions.
[2023-03-19 18:03:20] [INFO ] Parsed PT model containing 2398 places and 1954 transitions and 7816 arcs in 197 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 8 ms.
Deduced a syphon composed of 1984 places in 14 ms
Reduce places removed 1984 places and 0 transitions.
Support contains 63 out of 414 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 414/414 places, 1954/1954 transitions.
Reduce places removed 25 places and 0 transitions.
Ensure Unique test removed 828 transitions
Reduce isomorphic transitions removed 828 transitions.
Iterating post reduction 0 with 853 rules applied. Total rules applied 853 place count 389 transition count 1126
Discarding 73 places :
Symmetric choice reduction at 1 with 73 rule applications. Total rules 926 place count 316 transition count 996
Iterating global reduction 1 with 73 rules applied. Total rules applied 999 place count 316 transition count 996
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 1 with 9 rules applied. Total rules applied 1008 place count 316 transition count 987
Discarding 50 places :
Symmetric choice reduction at 2 with 50 rule applications. Total rules 1058 place count 266 transition count 937
Iterating global reduction 2 with 50 rules applied. Total rules applied 1108 place count 266 transition count 937
Ensure Unique test removed 27 transitions
Reduce isomorphic transitions removed 27 transitions.
Iterating post reduction 2 with 27 rules applied. Total rules applied 1135 place count 266 transition count 910
Discarding 22 places :
Symmetric choice reduction at 3 with 22 rule applications. Total rules 1157 place count 244 transition count 885
Iterating global reduction 3 with 22 rules applied. Total rules applied 1179 place count 244 transition count 885
Ensure Unique test removed 80 transitions
Reduce isomorphic transitions removed 80 transitions.
Iterating post reduction 3 with 80 rules applied. Total rules applied 1259 place count 244 transition count 805
Discarding 3 places :
Symmetric choice reduction at 4 with 3 rule applications. Total rules 1262 place count 241 transition count 800
Iterating global reduction 4 with 3 rules applied. Total rules applied 1265 place count 241 transition count 800
Discarding 3 places :
Symmetric choice reduction at 4 with 3 rule applications. Total rules 1268 place count 238 transition count 797
Iterating global reduction 4 with 3 rules applied. Total rules applied 1271 place count 238 transition count 797
Applied a total of 1271 rules in 87 ms. Remains 238 /414 variables (removed 176) and now considering 797/1954 (removed 1157) transitions.
// Phase 1: matrix 797 rows 238 cols
[2023-03-19 18:03:20] [INFO ] Computed 5 place invariants in 25 ms
[2023-03-19 18:03:20] [INFO ] Implicit Places using invariants in 288 ms returned []
[2023-03-19 18:03:20] [INFO ] Invariant cache hit.
[2023-03-19 18:03:21] [INFO ] State equation strengthened by 620 read => feed constraints.
[2023-03-19 18:03:22] [INFO ] Implicit Places using invariants and state equation in 1361 ms returned []
Implicit Place search using SMT with State Equation took 1672 ms to find 0 implicit places.
[2023-03-19 18:03:22] [INFO ] Invariant cache hit.
[2023-03-19 18:03:22] [INFO ] Dead Transitions using invariants and state equation in 370 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 238/414 places, 797/1954 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2132 ms. Remains : 238/414 places, 797/1954 transitions.
Support contains 63 out of 238 places after structural reductions.
[2023-03-19 18:03:23] [INFO ] Flatten gal took : 92 ms
[2023-03-19 18:03:23] [INFO ] Flatten gal took : 56 ms
[2023-03-19 18:03:23] [INFO ] Input system was already deterministic with 797 transitions.
Support contains 62 out of 238 places (down from 63) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2257 resets, run finished after 617 ms. (steps per millisecond=16 ) properties (out of 66) seen :2
Incomplete Best-First random walk after 1000 steps, including 36 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 43 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 44 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 44 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 59 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 35 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 52 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 48 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 104 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 55 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 50 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 45 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 42 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 43 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 57 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 88 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 49 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 105 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 45 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 45 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 44 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 47 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 41 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 108 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 37 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 52 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 42 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 49 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 49 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 54 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 43 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 51 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 40 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 39 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 33 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 45 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 54 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 47 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 41 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 43 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 94 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 57 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 42 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 45 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 42 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 87 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 53 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 51 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 43 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 47 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 64) seen :0
Interrupted probabilistic random walk after 177873 steps, run timeout after 3001 ms. (steps per millisecond=59 ) properties seen :{0=1, 1=1, 5=1, 7=1, 9=1, 10=1, 11=1, 12=1, 16=1, 17=1, 20=1, 23=1, 27=1, 30=1, 31=1, 36=1, 38=1, 44=1, 46=1, 48=1, 55=1, 62=1}
Probabilistic random walk after 177873 steps, saw 85296 distinct states, run finished after 3002 ms. (steps per millisecond=59 ) properties seen :22
Running SMT prover for 42 properties.
[2023-03-19 18:03:27] [INFO ] Invariant cache hit.
[2023-03-19 18:03:27] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 18:03:27] [INFO ] [Real]Absence check using 2 positive and 3 generalized place invariants in 6 ms returned sat
[2023-03-19 18:03:28] [INFO ] After 1231ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0 real:40
[2023-03-19 18:03:29] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 18:03:29] [INFO ] [Nat]Absence check using 2 positive and 3 generalized place invariants in 7 ms returned sat
[2023-03-19 18:03:32] [INFO ] After 2760ms SMT Verify possible using state equation in natural domain returned unsat :7 sat :35
[2023-03-19 18:03:32] [INFO ] State equation strengthened by 620 read => feed constraints.
[2023-03-19 18:03:38] [INFO ] After 6115ms SMT Verify possible using 620 Read/Feed constraints in natural domain returned unsat :7 sat :35
[2023-03-19 18:03:38] [INFO ] Deduced a trap composed of 73 places in 100 ms of which 6 ms to minimize.
[2023-03-19 18:03:38] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 214 ms
[2023-03-19 18:03:39] [INFO ] Deduced a trap composed of 31 places in 87 ms of which 2 ms to minimize.
[2023-03-19 18:03:39] [INFO ] Deduced a trap composed of 62 places in 73 ms of which 2 ms to minimize.
[2023-03-19 18:03:39] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 290 ms
[2023-03-19 18:03:45] [INFO ] After 13565ms SMT Verify possible using trap constraints in natural domain returned unsat :7 sat :35
Attempting to minimize the solution found.
Minimization took 5738 ms.
[2023-03-19 18:03:51] [INFO ] After 22531ms SMT Verify possible using all constraints in natural domain returned unsat :7 sat :35
Fused 42 Parikh solutions to 35 different solutions.
Parikh walk visited 0 properties in 1043 ms.
Support contains 43 out of 238 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 238/238 places, 797/797 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 222 transition count 626
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 222 transition count 626
Ensure Unique test removed 28 transitions
Reduce isomorphic transitions removed 28 transitions.
Iterating post reduction 0 with 28 rules applied. Total rules applied 60 place count 222 transition count 598
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 70 place count 212 transition count 588
Iterating global reduction 1 with 10 rules applied. Total rules applied 80 place count 212 transition count 588
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 82 place count 212 transition count 586
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 83 place count 211 transition count 584
Iterating global reduction 2 with 1 rules applied. Total rules applied 84 place count 211 transition count 584
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 85 place count 210 transition count 583
Iterating global reduction 2 with 1 rules applied. Total rules applied 86 place count 210 transition count 583
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 87 place count 209 transition count 582
Iterating global reduction 2 with 1 rules applied. Total rules applied 88 place count 209 transition count 582
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 89 place count 208 transition count 581
Iterating global reduction 2 with 1 rules applied. Total rules applied 90 place count 208 transition count 581
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 91 place count 207 transition count 580
Iterating global reduction 2 with 1 rules applied. Total rules applied 92 place count 207 transition count 580
Applied a total of 92 rules in 106 ms. Remains 207 /238 variables (removed 31) and now considering 580/797 (removed 217) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 107 ms. Remains : 207/238 places, 580/797 transitions.
Incomplete random walk after 10000 steps, including 2214 resets, run finished after 353 ms. (steps per millisecond=28 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 35 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 46 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 49 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1000 steps, including 125 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 45 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1000 steps, including 56 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1000 steps, including 112 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 53 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 51 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 54 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1000 steps, including 61 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 44 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 41 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 42 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1000 steps, including 39 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 48 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 43 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1000 steps, including 53 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 63 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 92 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1000 steps, including 42 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 53 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1000 steps, including 50 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 98 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1000 steps, including 48 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1000 steps, including 115 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1000 steps, including 35 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1000 steps, including 43 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 39 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1000 steps, including 52 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 51 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 47 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 45 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 54 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 35) seen :0
Incomplete Best-First random walk after 1001 steps, including 108 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 35) seen :0
Interrupted probabilistic random walk after 187040 steps, run timeout after 3001 ms. (steps per millisecond=62 ) properties seen :{0=1, 1=1, 2=1, 4=1, 7=1, 10=1, 15=1, 16=1, 17=1, 21=1, 26=1, 27=1, 28=1, 33=1}
Probabilistic random walk after 187040 steps, saw 89708 distinct states, run finished after 3001 ms. (steps per millisecond=62 ) properties seen :14
Running SMT prover for 21 properties.
// Phase 1: matrix 580 rows 207 cols
[2023-03-19 18:03:56] [INFO ] Computed 5 place invariants in 17 ms
[2023-03-19 18:03:56] [INFO ] [Real]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 18:03:56] [INFO ] [Real]Absence check using 2 positive and 3 generalized place invariants in 9 ms returned sat
[2023-03-19 18:03:57] [INFO ] After 1340ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:21
[2023-03-19 18:03:57] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 18:03:57] [INFO ] [Nat]Absence check using 2 positive and 3 generalized place invariants in 6 ms returned sat
[2023-03-19 18:03:59] [INFO ] After 1494ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :21
[2023-03-19 18:03:59] [INFO ] State equation strengthened by 421 read => feed constraints.
[2023-03-19 18:04:01] [INFO ] After 2281ms SMT Verify possible using 421 Read/Feed constraints in natural domain returned unsat :0 sat :21
[2023-03-19 18:04:01] [INFO ] Deduced a trap composed of 54 places in 62 ms of which 1 ms to minimize.
[2023-03-19 18:04:02] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 114 ms
[2023-03-19 18:04:02] [INFO ] Deduced a trap composed of 63 places in 75 ms of which 1 ms to minimize.
[2023-03-19 18:04:02] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 137 ms
[2023-03-19 18:04:05] [INFO ] After 6032ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :21
Attempting to minimize the solution found.
Minimization took 2853 ms.
[2023-03-19 18:04:08] [INFO ] After 10634ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :21
Parikh walk visited 0 properties in 1442 ms.
Support contains 29 out of 207 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 207/207 places, 580/580 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 195 transition count 437
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 195 transition count 437
Discarding 11 places :
Symmetric choice reduction at 0 with 11 rule applications. Total rules 35 place count 184 transition count 426
Iterating global reduction 0 with 11 rules applied. Total rules applied 46 place count 184 transition count 426
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 51 place count 184 transition count 421
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 55 place count 180 transition count 414
Iterating global reduction 1 with 4 rules applied. Total rules applied 59 place count 180 transition count 414
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 61 place count 180 transition count 412
Applied a total of 61 rules in 40 ms. Remains 180 /207 variables (removed 27) and now considering 412/580 (removed 168) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 41 ms. Remains : 180/207 places, 412/580 transitions.
Incomplete random walk after 10000 steps, including 2273 resets, run finished after 284 ms. (steps per millisecond=35 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1000 steps, including 92 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1000 steps, including 53 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1000 steps, including 96 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 49 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 53 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 48 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 46 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 40 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 36 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 48 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1000 steps, including 99 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1000 steps, including 53 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1000 steps, including 44 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 107 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 45 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 103 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 51 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1000 steps, including 45 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 52 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 46 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 21) seen :0
Incomplete Best-First random walk after 1001 steps, including 105 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 21) seen :0
Interrupted probabilistic random walk after 188930 steps, run timeout after 3001 ms. (steps per millisecond=62 ) properties seen :{}
Probabilistic random walk after 188930 steps, saw 86833 distinct states, run finished after 3002 ms. (steps per millisecond=62 ) properties seen :0
Running SMT prover for 21 properties.
// Phase 1: matrix 412 rows 180 cols
[2023-03-19 18:04:13] [INFO ] Computed 5 place invariants in 4 ms
[2023-03-19 18:04:13] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 18:04:13] [INFO ] [Real]Absence check using 2 positive and 3 generalized place invariants in 5 ms returned sat
[2023-03-19 18:04:14] [INFO ] After 582ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:21
[2023-03-19 18:04:14] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 18:04:14] [INFO ] [Nat]Absence check using 2 positive and 3 generalized place invariants in 7 ms returned sat
[2023-03-19 18:04:15] [INFO ] After 1241ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :21
[2023-03-19 18:04:15] [INFO ] State equation strengthened by 277 read => feed constraints.
[2023-03-19 18:04:17] [INFO ] After 1968ms SMT Verify possible using 277 Read/Feed constraints in natural domain returned unsat :0 sat :21
[2023-03-19 18:04:17] [INFO ] Deduced a trap composed of 54 places in 58 ms of which 2 ms to minimize.
[2023-03-19 18:04:17] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 106 ms
[2023-03-19 18:04:18] [INFO ] Deduced a trap composed of 60 places in 60 ms of which 1 ms to minimize.
[2023-03-19 18:04:18] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 112 ms
[2023-03-19 18:04:20] [INFO ] After 4929ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :21
Attempting to minimize the solution found.
Minimization took 2134 ms.
[2023-03-19 18:04:22] [INFO ] After 8543ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :21
Parikh walk visited 0 properties in 1819 ms.
Support contains 29 out of 180 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 180/180 places, 412/412 transitions.
Applied a total of 0 rules in 18 ms. Remains 180 /180 variables (removed 0) and now considering 412/412 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 19 ms. Remains : 180/180 places, 412/412 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 180/180 places, 412/412 transitions.
Applied a total of 0 rules in 14 ms. Remains 180 /180 variables (removed 0) and now considering 412/412 (removed 0) transitions.
[2023-03-19 18:04:24] [INFO ] Invariant cache hit.
[2023-03-19 18:04:24] [INFO ] Implicit Places using invariants in 66 ms returned []
[2023-03-19 18:04:24] [INFO ] Invariant cache hit.
[2023-03-19 18:04:24] [INFO ] State equation strengthened by 277 read => feed constraints.
[2023-03-19 18:04:25] [INFO ] Implicit Places using invariants and state equation in 470 ms returned []
Implicit Place search using SMT with State Equation took 541 ms to find 0 implicit places.
[2023-03-19 18:04:25] [INFO ] Redundant transitions in 27 ms returned []
[2023-03-19 18:04:25] [INFO ] Invariant cache hit.
[2023-03-19 18:04:25] [INFO ] Dead Transitions using invariants and state equation in 135 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 723 ms. Remains : 180/180 places, 412/412 transitions.
Graph (complete) has 640 edges and 180 vertex of which 179 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.2 ms
Discarding 1 places :
Also discarding 0 output transitions
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded 6 transitions
Performed 6 trivial Post agglomeration. Transition count delta: 6
Iterating post reduction 0 with 8 rules applied. Total rules applied 9 place count 179 transition count 404
Reduce places removed 6 places and 0 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 15 place count 173 transition count 404
Performed 18 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 18 Pre rules applied. Total rules applied 15 place count 173 transition count 386
Deduced a syphon composed of 18 places in 0 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 2 with 36 rules applied. Total rules applied 51 place count 155 transition count 386
Performed 13 Post agglomeration using F-continuation condition.Transition count delta: 13
Deduced a syphon composed of 13 places in 0 ms
Reduce places removed 13 places and 0 transitions.
Iterating global reduction 2 with 26 rules applied. Total rules applied 77 place count 142 transition count 373
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -11
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 79 place count 141 transition count 384
Free-agglomeration rule applied 1 times.
Iterating global reduction 2 with 1 rules applied. Total rules applied 80 place count 141 transition count 383
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 81 place count 140 transition count 383
Applied a total of 81 rules in 51 ms. Remains 140 /180 variables (removed 40) and now considering 383/412 (removed 29) transitions.
Running SMT prover for 21 properties.
// Phase 1: matrix 383 rows 140 cols
[2023-03-19 18:04:25] [INFO ] Computed 4 place invariants in 3 ms
[2023-03-19 18:04:25] [INFO ] [Real]Absence check using 4 positive place invariants in 2 ms returned sat
[2023-03-19 18:04:25] [INFO ] After 590ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:21
[2023-03-19 18:04:26] [INFO ] [Nat]Absence check using 4 positive place invariants in 2 ms returned sat
[2023-03-19 18:04:27] [INFO ] After 1400ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :21
[2023-03-19 18:04:27] [INFO ] Deduced a trap composed of 45 places in 61 ms of which 1 ms to minimize.
[2023-03-19 18:04:27] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 99 ms
[2023-03-19 18:04:29] [INFO ] After 2963ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :21
Attempting to minimize the solution found.
Minimization took 968 ms.
[2023-03-19 18:04:30] [INFO ] After 4100ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :21
Successfully simplified 7 atomic propositions for a total of 16 simplifications.
[2023-03-19 18:04:30] [INFO ] Flatten gal took : 59 ms
[2023-03-19 18:04:30] [INFO ] Flatten gal took : 41 ms
[2023-03-19 18:04:30] [INFO ] Input system was already deterministic with 797 transitions.
Computed a total of 53 stabilizing places and 105 stable transitions
Graph (complete) has 1241 edges and 238 vertex of which 237 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.13 ms
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 797/797 transitions.
Discarding 41 places :
Symmetric choice reduction at 0 with 41 rule applications. Total rules 41 place count 197 transition count 356
Iterating global reduction 0 with 41 rules applied. Total rules applied 82 place count 197 transition count 356
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 0 with 10 rules applied. Total rules applied 92 place count 197 transition count 346
Discarding 36 places :
Symmetric choice reduction at 1 with 36 rule applications. Total rules 128 place count 161 transition count 310
Iterating global reduction 1 with 36 rules applied. Total rules applied 164 place count 161 transition count 310
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 1 with 13 rules applied. Total rules applied 177 place count 161 transition count 297
Discarding 12 places :
Symmetric choice reduction at 2 with 12 rule applications. Total rules 189 place count 149 transition count 276
Iterating global reduction 2 with 12 rules applied. Total rules applied 201 place count 149 transition count 276
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 2 with 13 rules applied. Total rules applied 214 place count 149 transition count 263
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 218 place count 145 transition count 259
Iterating global reduction 3 with 4 rules applied. Total rules applied 222 place count 145 transition count 259
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 225 place count 142 transition count 256
Iterating global reduction 3 with 3 rules applied. Total rules applied 228 place count 142 transition count 256
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 230 place count 140 transition count 254
Iterating global reduction 3 with 2 rules applied. Total rules applied 232 place count 140 transition count 254
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 234 place count 138 transition count 252
Iterating global reduction 3 with 2 rules applied. Total rules applied 236 place count 138 transition count 252
Applied a total of 236 rules in 18 ms. Remains 138 /238 variables (removed 100) and now considering 252/797 (removed 545) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 18 ms. Remains : 138/238 places, 252/797 transitions.
[2023-03-19 18:04:30] [INFO ] Flatten gal took : 11 ms
[2023-03-19 18:04:30] [INFO ] Flatten gal took : 11 ms
[2023-03-19 18:04:30] [INFO ] Input system was already deterministic with 252 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 238/238 places, 797/797 transitions.
Discarding 39 places :
Symmetric choice reduction at 0 with 39 rule applications. Total rules 39 place count 199 transition count 400
Iterating global reduction 0 with 39 rules applied. Total rules applied 78 place count 199 transition count 400
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 0 with 14 rules applied. Total rules applied 92 place count 199 transition count 386
Discarding 32 places :
Symmetric choice reduction at 1 with 32 rule applications. Total rules 124 place count 167 transition count 354
Iterating global reduction 1 with 32 rules applied. Total rules applied 156 place count 167 transition count 354
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Iterating post reduction 1 with 11 rules applied. Total rules applied 167 place count 167 transition count 343
Discarding 10 places :
Symmetric choice reduction at 2 with 10 rule applications. Total rules 177 place count 157 transition count 327
Iterating global reduction 2 with 10 rules applied. Total rules applied 187 place count 157 transition count 327
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 2 with 15 rules applied. Total rules applied 202 place count 157 transition count 312
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 205 place count 154 transition count 309
Iterating global reduction 3 with 3 rules applied. Total rules applied 208 place count 154 transition count 309
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 211 place count 151 transition count 306
Iterating global reduction 3 with 3 rules applied. Total rules applied 214 place count 151 transition count 306
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 217 place count 148 transition count 303
Iterating global reduction 3 with 3 rules applied. Total rules applied 220 place count 148 transition count 303
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 223 place count 145 transition count 300
Iterating global reduction 3 with 3 rules applied. Total rules applied 226 place count 145 transition count 300
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 227 place count 144 transition count 297
Iterating global reduction 3 with 1 rules applied. Total rules applied 228 place count 144 transition count 297
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 229 place count 143 transition count 296
Iterating global reduction 3 with 1 rules applied. Total rules applied 230 place count 143 transition count 296
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 231 place count 142 transition count 295
Iterating global reduction 3 with 1 rules applied. Total rules applied 232 place count 142 transition count 295
Applied a total of 232 rules in 63 ms. Remains 142 /238 variables (removed 96) and now considering 295/797 (removed 502) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 64 ms. Remains : 142/238 places, 295/797 transitions.
[2023-03-19 18:04:30] [INFO ] Flatten gal took : 11 ms
[2023-03-19 18:04:30] [INFO ] Flatten gal took : 12 ms
[2023-03-19 18:04:30] [INFO ] Input system was already deterministic with 295 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 238/238 places, 797/797 transitions.
Discarding 46 places :
Symmetric choice reduction at 0 with 46 rule applications. Total rules 46 place count 192 transition count 268
Iterating global reduction 0 with 46 rules applied. Total rules applied 92 place count 192 transition count 268
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 97 place count 192 transition count 263
Discarding 40 places :
Symmetric choice reduction at 1 with 40 rule applications. Total rules 137 place count 152 transition count 223
Iterating global reduction 1 with 40 rules applied. Total rules applied 177 place count 152 transition count 223
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 193 place count 152 transition count 207
Discarding 15 places :
Symmetric choice reduction at 2 with 15 rule applications. Total rules 208 place count 137 transition count 180
Iterating global reduction 2 with 15 rules applied. Total rules applied 223 place count 137 transition count 180
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 2 with 10 rules applied. Total rules applied 233 place count 137 transition count 170
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 237 place count 133 transition count 166
Iterating global reduction 3 with 4 rules applied. Total rules applied 241 place count 133 transition count 166
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 245 place count 129 transition count 162
Iterating global reduction 3 with 4 rules applied. Total rules applied 249 place count 129 transition count 162
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 251 place count 127 transition count 160
Iterating global reduction 3 with 2 rules applied. Total rules applied 253 place count 127 transition count 160
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 255 place count 125 transition count 158
Iterating global reduction 3 with 2 rules applied. Total rules applied 257 place count 125 transition count 158
Applied a total of 257 rules in 32 ms. Remains 125 /238 variables (removed 113) and now considering 158/797 (removed 639) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 33 ms. Remains : 125/238 places, 158/797 transitions.
[2023-03-19 18:04:30] [INFO ] Flatten gal took : 7 ms
[2023-03-19 18:04:30] [INFO ] Flatten gal took : 7 ms
[2023-03-19 18:04:30] [INFO ] Input system was already deterministic with 158 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 238/238 places, 797/797 transitions.
Discarding 47 places :
Symmetric choice reduction at 0 with 47 rule applications. Total rules 47 place count 191 transition count 280
Iterating global reduction 0 with 47 rules applied. Total rules applied 94 place count 191 transition count 280
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 0 with 6 rules applied. Total rules applied 100 place count 191 transition count 274
Discarding 42 places :
Symmetric choice reduction at 1 with 42 rule applications. Total rules 142 place count 149 transition count 232
Iterating global reduction 1 with 42 rules applied. Total rules applied 184 place count 149 transition count 232
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 200 place count 149 transition count 216
Discarding 17 places :
Symmetric choice reduction at 2 with 17 rule applications. Total rules 217 place count 132 transition count 186
Iterating global reduction 2 with 17 rules applied. Total rules applied 234 place count 132 transition count 186
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 2 with 12 rules applied. Total rules applied 246 place count 132 transition count 174
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 251 place count 127 transition count 169
Iterating global reduction 3 with 5 rules applied. Total rules applied 256 place count 127 transition count 169
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 261 place count 122 transition count 164
Iterating global reduction 3 with 5 rules applied. Total rules applied 266 place count 122 transition count 164
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 270 place count 118 transition count 160
Iterating global reduction 3 with 4 rules applied. Total rules applied 274 place count 118 transition count 160
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 277 place count 115 transition count 157
Iterating global reduction 3 with 3 rules applied. Total rules applied 280 place count 115 transition count 157
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 281 place count 114 transition count 154
Iterating global reduction 3 with 1 rules applied. Total rules applied 282 place count 114 transition count 154
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 283 place count 113 transition count 153
Iterating global reduction 3 with 1 rules applied. Total rules applied 284 place count 113 transition count 153
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 285 place count 112 transition count 152
Iterating global reduction 3 with 1 rules applied. Total rules applied 286 place count 112 transition count 152
Applied a total of 286 rules in 33 ms. Remains 112 /238 variables (removed 126) and now considering 152/797 (removed 645) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 33 ms. Remains : 112/238 places, 152/797 transitions.
[2023-03-19 18:04:30] [INFO ] Flatten gal took : 6 ms
[2023-03-19 18:04:30] [INFO ] Flatten gal took : 6 ms
[2023-03-19 18:04:30] [INFO ] Input system was already deterministic with 152 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 238/238 places, 797/797 transitions.
Discarding 48 places :
Symmetric choice reduction at 0 with 48 rule applications. Total rules 48 place count 190 transition count 265
Iterating global reduction 0 with 48 rules applied. Total rules applied 96 place count 190 transition count 265
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 101 place count 190 transition count 260
Discarding 43 places :
Symmetric choice reduction at 1 with 43 rule applications. Total rules 144 place count 147 transition count 217
Iterating global reduction 1 with 43 rules applied. Total rules applied 187 place count 147 transition count 217
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 203 place count 147 transition count 201
Discarding 18 places :
Symmetric choice reduction at 2 with 18 rule applications. Total rules 221 place count 129 transition count 169
Iterating global reduction 2 with 18 rules applied. Total rules applied 239 place count 129 transition count 169
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 2 with 12 rules applied. Total rules applied 251 place count 129 transition count 157
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 257 place count 123 transition count 151
Iterating global reduction 3 with 6 rules applied. Total rules applied 263 place count 123 transition count 151
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 269 place count 117 transition count 145
Iterating global reduction 3 with 6 rules applied. Total rules applied 275 place count 117 transition count 145
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 280 place count 112 transition count 140
Iterating global reduction 3 with 5 rules applied. Total rules applied 285 place count 112 transition count 140
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 287 place count 112 transition count 138
Discarding 4 places :
Symmetric choice reduction at 4 with 4 rule applications. Total rules 291 place count 108 transition count 134
Iterating global reduction 4 with 4 rules applied. Total rules applied 295 place count 108 transition count 134
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 296 place count 107 transition count 131
Iterating global reduction 4 with 1 rules applied. Total rules applied 297 place count 107 transition count 131
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 298 place count 106 transition count 130
Iterating global reduction 4 with 1 rules applied. Total rules applied 299 place count 106 transition count 130
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 300 place count 105 transition count 129
Iterating global reduction 4 with 1 rules applied. Total rules applied 301 place count 105 transition count 129
Applied a total of 301 rules in 31 ms. Remains 105 /238 variables (removed 133) and now considering 129/797 (removed 668) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 32 ms. Remains : 105/238 places, 129/797 transitions.
[2023-03-19 18:04:30] [INFO ] Flatten gal took : 5 ms
[2023-03-19 18:04:30] [INFO ] Flatten gal took : 6 ms
[2023-03-19 18:04:30] [INFO ] Input system was already deterministic with 129 transitions.
Incomplete random walk after 10000 steps, including 2222 resets, run finished after 22 ms. (steps per millisecond=454 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 479 resets, run finished after 12 ms. (steps per millisecond=833 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2176440 steps, run timeout after 3001 ms. (steps per millisecond=725 ) properties seen :{}
Probabilistic random walk after 2176440 steps, saw 962723 distinct states, run finished after 3001 ms. (steps per millisecond=725 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 129 rows 105 cols
[2023-03-19 18:04:33] [INFO ] Computed 5 place invariants in 6 ms
[2023-03-19 18:04:33] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 18:04:33] [INFO ] [Real]Absence check using 2 positive and 3 generalized place invariants in 4 ms returned sat
[2023-03-19 18:04:33] [INFO ] After 99ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 18:04:33] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 18:04:33] [INFO ] [Nat]Absence check using 2 positive and 3 generalized place invariants in 3 ms returned sat
[2023-03-19 18:04:33] [INFO ] After 60ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 18:04:33] [INFO ] State equation strengthened by 57 read => feed constraints.
[2023-03-19 18:04:33] [INFO ] After 33ms SMT Verify possible using 57 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 18:04:34] [INFO ] Deduced a trap composed of 23 places in 59 ms of which 1 ms to minimize.
[2023-03-19 18:04:34] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 81 ms
[2023-03-19 18:04:34] [INFO ] After 138ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 42 ms.
[2023-03-19 18:04:34] [INFO ] After 296ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 77 ms.
Support contains 2 out of 105 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 105/105 places, 129/129 transitions.
Graph (complete) has 307 edges and 105 vertex of which 104 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.0 ms
Discarding 1 places :
Also discarding 0 output transitions
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 3 place count 104 transition count 127
Applied a total of 3 rules in 8 ms. Remains 104 /105 variables (removed 1) and now considering 127/129 (removed 2) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 9 ms. Remains : 104/105 places, 127/129 transitions.
Incomplete random walk after 1000000 steps, including 224301 resets, run finished after 1416 ms. (steps per millisecond=706 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 1000001 steps, including 47293 resets, run finished after 480 ms. (steps per millisecond=2083 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2302527 steps, run timeout after 3001 ms. (steps per millisecond=767 ) properties seen :{}
Probabilistic random walk after 2302527 steps, saw 1019814 distinct states, run finished after 3001 ms. (steps per millisecond=767 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 127 rows 104 cols
[2023-03-19 18:04:39] [INFO ] Computed 4 place invariants in 4 ms
[2023-03-19 18:04:39] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 18:04:39] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 2 ms returned sat
[2023-03-19 18:04:39] [INFO ] After 102ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 18:04:39] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 18:04:39] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 2 ms returned sat
[2023-03-19 18:04:39] [INFO ] After 54ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 18:04:39] [INFO ] State equation strengthened by 55 read => feed constraints.
[2023-03-19 18:04:39] [INFO ] After 25ms SMT Verify possible using 55 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 18:04:39] [INFO ] After 51ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 26 ms.
[2023-03-19 18:04:39] [INFO ] After 182ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 30 ms.
Support contains 2 out of 104 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 104/104 places, 127/127 transitions.
Applied a total of 0 rules in 2 ms. Remains 104 /104 variables (removed 0) and now considering 127/127 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 2 ms. Remains : 104/104 places, 127/127 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 104/104 places, 127/127 transitions.
Applied a total of 0 rules in 2 ms. Remains 104 /104 variables (removed 0) and now considering 127/127 (removed 0) transitions.
[2023-03-19 18:04:39] [INFO ] Invariant cache hit.
[2023-03-19 18:04:39] [INFO ] Implicit Places using invariants in 76 ms returned []
[2023-03-19 18:04:39] [INFO ] Invariant cache hit.
[2023-03-19 18:04:39] [INFO ] State equation strengthened by 55 read => feed constraints.
[2023-03-19 18:04:39] [INFO ] Implicit Places using invariants and state equation in 157 ms returned []
Implicit Place search using SMT with State Equation took 236 ms to find 0 implicit places.
[2023-03-19 18:04:39] [INFO ] Redundant transitions in 0 ms returned []
[2023-03-19 18:04:39] [INFO ] Invariant cache hit.
[2023-03-19 18:04:39] [INFO ] Dead Transitions using invariants and state equation in 66 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 312 ms. Remains : 104/104 places, 127/127 transitions.
Incomplete random walk after 100000 steps, including 22298 resets, run finished after 344 ms. (steps per millisecond=290 ) properties (out of 2) seen :1
Running SMT prover for 1 properties.
[2023-03-19 18:04:40] [INFO ] Invariant cache hit.
[2023-03-19 18:04:40] [INFO ] [Real]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 18:04:40] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 2 ms returned sat
[2023-03-19 18:04:40] [INFO ] After 45ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 18:04:40] [INFO ] State equation strengthened by 55 read => feed constraints.
[2023-03-19 18:04:40] [INFO ] After 37ms SMT Verify possible using 55 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-19 18:04:40] [INFO ] After 54ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 18:04:40] [INFO ] After 154ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 18:04:40] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 18:04:40] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 18:04:40] [INFO ] After 37ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 18:04:40] [INFO ] After 30ms SMT Verify possible using 55 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 18:04:40] [INFO ] Deduced a trap composed of 22 places in 38 ms of which 0 ms to minimize.
[2023-03-19 18:04:40] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 59 ms
[2023-03-19 18:04:40] [INFO ] After 99ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 5 ms.
[2023-03-19 18:04:40] [INFO ] After 181ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Incomplete random walk after 1000000 steps, including 224404 resets, run finished after 1594 ms. (steps per millisecond=627 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 1000001 steps, including 46922 resets, run finished after 528 ms. (steps per millisecond=1893 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 4589635 steps, run timeout after 6001 ms. (steps per millisecond=764 ) properties seen :{}
Probabilistic random walk after 4589635 steps, saw 2026941 distinct states, run finished after 6001 ms. (steps per millisecond=764 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-19 18:04:48] [INFO ] Invariant cache hit.
[2023-03-19 18:04:48] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 18:04:48] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 3 ms returned sat
[2023-03-19 18:04:48] [INFO ] After 111ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 18:04:48] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 18:04:48] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 2 ms returned sat
[2023-03-19 18:04:48] [INFO ] After 51ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 18:04:48] [INFO ] State equation strengthened by 55 read => feed constraints.
[2023-03-19 18:04:48] [INFO ] After 23ms SMT Verify possible using 55 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 18:04:48] [INFO ] After 53ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 30 ms.
[2023-03-19 18:04:48] [INFO ] After 179ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 42 ms.
Support contains 2 out of 104 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 104/104 places, 127/127 transitions.
Applied a total of 0 rules in 7 ms. Remains 104 /104 variables (removed 0) and now considering 127/127 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 7 ms. Remains : 104/104 places, 127/127 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 104/104 places, 127/127 transitions.
Applied a total of 0 rules in 5 ms. Remains 104 /104 variables (removed 0) and now considering 127/127 (removed 0) transitions.
[2023-03-19 18:04:48] [INFO ] Invariant cache hit.
[2023-03-19 18:04:48] [INFO ] Implicit Places using invariants in 100 ms returned []
[2023-03-19 18:04:48] [INFO ] Invariant cache hit.
[2023-03-19 18:04:49] [INFO ] State equation strengthened by 55 read => feed constraints.
[2023-03-19 18:04:49] [INFO ] Implicit Places using invariants and state equation in 193 ms returned []
Implicit Place search using SMT with State Equation took 296 ms to find 0 implicit places.
[2023-03-19 18:04:49] [INFO ] Redundant transitions in 0 ms returned []
[2023-03-19 18:04:49] [INFO ] Invariant cache hit.
[2023-03-19 18:04:49] [INFO ] Dead Transitions using invariants and state equation in 71 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 380 ms. Remains : 104/104 places, 127/127 transitions.
Incomplete random walk after 100000 steps, including 22414 resets, run finished after 152 ms. (steps per millisecond=657 ) properties (out of 2) seen :1
Running SMT prover for 1 properties.
[2023-03-19 18:04:49] [INFO ] Invariant cache hit.
[2023-03-19 18:04:49] [INFO ] [Real]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 18:04:49] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 2 ms returned sat
[2023-03-19 18:04:49] [INFO ] After 47ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 18:04:49] [INFO ] State equation strengthened by 55 read => feed constraints.
[2023-03-19 18:04:49] [INFO ] After 19ms SMT Verify possible using 55 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-19 18:04:49] [INFO ] After 35ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 18:04:49] [INFO ] After 130ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 18:04:49] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 18:04:49] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 18:04:49] [INFO ] After 39ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 18:04:49] [INFO ] After 17ms SMT Verify possible using 55 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 18:04:49] [INFO ] Deduced a trap composed of 22 places in 55 ms of which 1 ms to minimize.
[2023-03-19 18:04:49] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 68 ms
[2023-03-19 18:04:49] [INFO ] After 92ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 4 ms.
[2023-03-19 18:04:49] [INFO ] After 170ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Finished random walk after 1 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=1 )
Incomplete random walk after 10000 steps, including 2286 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 1080 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2209635 steps, run timeout after 3001 ms. (steps per millisecond=736 ) properties seen :{}
Probabilistic random walk after 2209635 steps, saw 980393 distinct states, run finished after 3001 ms. (steps per millisecond=736 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-19 18:04:52] [INFO ] Invariant cache hit.
[2023-03-19 18:04:52] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 18:04:52] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 2 ms returned sat
[2023-03-19 18:04:52] [INFO ] After 49ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 18:04:52] [INFO ] State equation strengthened by 55 read => feed constraints.
[2023-03-19 18:04:52] [INFO ] After 25ms SMT Verify possible using 55 Read/Feed constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 18:04:52] [INFO ] After 125ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 18:04:52] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 18:04:52] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 3 ms returned sat
[2023-03-19 18:04:52] [INFO ] After 55ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 18:04:53] [INFO ] After 29ms SMT Verify possible using 55 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 18:04:53] [INFO ] Deduced a trap composed of 22 places in 49 ms of which 1 ms to minimize.
[2023-03-19 18:04:53] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 64 ms
[2023-03-19 18:04:53] [INFO ] After 102ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 12 ms.
[2023-03-19 18:04:53] [INFO ] After 209ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 1 ms.
Support contains 1 out of 104 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 104/104 places, 127/127 transitions.
Applied a total of 0 rules in 3 ms. Remains 104 /104 variables (removed 0) and now considering 127/127 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 3 ms. Remains : 104/104 places, 127/127 transitions.
Incomplete random walk after 10000 steps, including 2235 resets, run finished after 14 ms. (steps per millisecond=714 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 1037 resets, run finished after 8 ms. (steps per millisecond=1250 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2546804 steps, run timeout after 3001 ms. (steps per millisecond=848 ) properties seen :{}
Probabilistic random walk after 2546804 steps, saw 1123937 distinct states, run finished after 3003 ms. (steps per millisecond=848 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-19 18:04:56] [INFO ] Invariant cache hit.
[2023-03-19 18:04:56] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 18:04:56] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 18:04:56] [INFO ] After 47ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 18:04:56] [INFO ] State equation strengthened by 55 read => feed constraints.
[2023-03-19 18:04:56] [INFO ] After 25ms SMT Verify possible using 55 Read/Feed constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 18:04:56] [INFO ] After 123ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 18:04:56] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 18:04:56] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 18:04:56] [INFO ] After 36ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 18:04:56] [INFO ] After 21ms SMT Verify possible using 55 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 18:04:56] [INFO ] Deduced a trap composed of 22 places in 49 ms of which 0 ms to minimize.
[2023-03-19 18:04:56] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 60 ms
[2023-03-19 18:04:56] [INFO ] After 88ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 8 ms.
[2023-03-19 18:04:56] [INFO ] After 180ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 1 ms.
Support contains 1 out of 104 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 104/104 places, 127/127 transitions.
Applied a total of 0 rules in 5 ms. Remains 104 /104 variables (removed 0) and now considering 127/127 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 5 ms. Remains : 104/104 places, 127/127 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 104/104 places, 127/127 transitions.
Applied a total of 0 rules in 4 ms. Remains 104 /104 variables (removed 0) and now considering 127/127 (removed 0) transitions.
[2023-03-19 18:04:56] [INFO ] Invariant cache hit.
[2023-03-19 18:04:56] [INFO ] Implicit Places using invariants in 94 ms returned []
[2023-03-19 18:04:56] [INFO ] Invariant cache hit.
[2023-03-19 18:04:56] [INFO ] State equation strengthened by 55 read => feed constraints.
[2023-03-19 18:04:56] [INFO ] Implicit Places using invariants and state equation in 230 ms returned []
Implicit Place search using SMT with State Equation took 328 ms to find 0 implicit places.
[2023-03-19 18:04:56] [INFO ] Redundant transitions in 0 ms returned []
[2023-03-19 18:04:56] [INFO ] Invariant cache hit.
[2023-03-19 18:04:56] [INFO ] Dead Transitions using invariants and state equation in 87 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 431 ms. Remains : 104/104 places, 127/127 transitions.
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded 6 transitions
Performed 6 trivial Post agglomeration. Transition count delta: 6
Iterating post reduction 0 with 8 rules applied. Total rules applied 8 place count 104 transition count 119
Reduce places removed 6 places and 0 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 14 place count 98 transition count 119
Performed 17 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 17 Pre rules applied. Total rules applied 14 place count 98 transition count 102
Deduced a syphon composed of 17 places in 0 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 2 with 34 rules applied. Total rules applied 48 place count 81 transition count 102
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 2 with 12 rules applied. Total rules applied 60 place count 75 transition count 96
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -9
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 62 place count 74 transition count 105
Applied a total of 62 rules in 9 ms. Remains 74 /104 variables (removed 30) and now considering 105/127 (removed 22) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 105 rows 74 cols
[2023-03-19 18:04:56] [INFO ] Computed 5 place invariants in 2 ms
[2023-03-19 18:04:56] [INFO ] [Real]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 18:04:56] [INFO ] [Real]Absence check using 2 positive and 3 generalized place invariants in 2 ms returned sat
[2023-03-19 18:04:56] [INFO ] After 39ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 18:04:57] [INFO ] Deduced a trap composed of 13 places in 49 ms of which 0 ms to minimize.
[2023-03-19 18:04:57] [INFO ] Deduced a trap composed of 40 places in 43 ms of which 0 ms to minimize.
[2023-03-19 18:04:57] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 113 ms
[2023-03-19 18:04:57] [INFO ] After 159ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 18:04:57] [INFO ] After 203ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 18:04:57] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 18:04:57] [INFO ] [Nat]Absence check using 2 positive and 3 generalized place invariants in 2 ms returned sat
[2023-03-19 18:04:57] [INFO ] After 45ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 18:04:57] [INFO ] Deduced a trap composed of 13 places in 52 ms of which 0 ms to minimize.
[2023-03-19 18:04:57] [INFO ] Deduced a trap composed of 40 places in 40 ms of which 1 ms to minimize.
[2023-03-19 18:04:57] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 113 ms
[2023-03-19 18:04:57] [INFO ] After 163ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 6 ms.
[2023-03-19 18:04:57] [INFO ] After 218ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded 6 transitions
Performed 6 trivial Post agglomeration. Transition count delta: 6
Iterating post reduction 0 with 7 rules applied. Total rules applied 7 place count 104 transition count 120
Reduce places removed 6 places and 0 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 13 place count 98 transition count 120
Performed 17 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 17 Pre rules applied. Total rules applied 13 place count 98 transition count 103
Deduced a syphon composed of 17 places in 0 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 2 with 34 rules applied. Total rules applied 47 place count 81 transition count 103
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 2 with 12 rules applied. Total rules applied 59 place count 75 transition count 97
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -9
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 61 place count 74 transition count 106
Applied a total of 61 rules in 11 ms. Remains 74 /104 variables (removed 30) and now considering 106/127 (removed 21) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 106 rows 74 cols
[2023-03-19 18:04:57] [INFO ] Computed 4 place invariants in 1 ms
[2023-03-19 18:04:57] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 18:04:57] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 18:04:57] [INFO ] After 93ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 18:04:57] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 18:04:57] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 18:04:57] [INFO ] After 47ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 18:04:57] [INFO ] After 66ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 14 ms.
[2023-03-19 18:04:57] [INFO ] After 115ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Starting structural reductions in SI_CTL mode, iteration 0 : 238/238 places, 797/797 transitions.
Discarding 47 places :
Symmetric choice reduction at 0 with 47 rule applications. Total rules 47 place count 191 transition count 280
Iterating global reduction 0 with 47 rules applied. Total rules applied 94 place count 191 transition count 280
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 0 with 6 rules applied. Total rules applied 100 place count 191 transition count 274
Discarding 42 places :
Symmetric choice reduction at 1 with 42 rule applications. Total rules 142 place count 149 transition count 232
Iterating global reduction 1 with 42 rules applied. Total rules applied 184 place count 149 transition count 232
Ensure Unique test removed 17 transitions
Reduce isomorphic transitions removed 17 transitions.
Iterating post reduction 1 with 17 rules applied. Total rules applied 201 place count 149 transition count 215
Discarding 16 places :
Symmetric choice reduction at 2 with 16 rule applications. Total rules 217 place count 133 transition count 187
Iterating global reduction 2 with 16 rules applied. Total rules applied 233 place count 133 transition count 187
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Iterating post reduction 2 with 11 rules applied. Total rules applied 244 place count 133 transition count 176
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 248 place count 129 transition count 172
Iterating global reduction 3 with 4 rules applied. Total rules applied 252 place count 129 transition count 172
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 256 place count 125 transition count 168
Iterating global reduction 3 with 4 rules applied. Total rules applied 260 place count 125 transition count 168
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 264 place count 121 transition count 164
Iterating global reduction 3 with 4 rules applied. Total rules applied 268 place count 121 transition count 164
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 271 place count 118 transition count 161
Iterating global reduction 3 with 3 rules applied. Total rules applied 274 place count 118 transition count 161
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 275 place count 117 transition count 158
Iterating global reduction 3 with 1 rules applied. Total rules applied 276 place count 117 transition count 158
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 277 place count 116 transition count 157
Iterating global reduction 3 with 1 rules applied. Total rules applied 278 place count 116 transition count 157
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 279 place count 115 transition count 156
Iterating global reduction 3 with 1 rules applied. Total rules applied 280 place count 115 transition count 156
Applied a total of 280 rules in 32 ms. Remains 115 /238 variables (removed 123) and now considering 156/797 (removed 641) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 32 ms. Remains : 115/238 places, 156/797 transitions.
[2023-03-19 18:04:57] [INFO ] Flatten gal took : 7 ms
[2023-03-19 18:04:57] [INFO ] Flatten gal took : 7 ms
[2023-03-19 18:04:57] [INFO ] Input system was already deterministic with 156 transitions.
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 797/797 transitions.
Discarding 42 places :
Symmetric choice reduction at 0 with 42 rule applications. Total rules 42 place count 196 transition count 355
Iterating global reduction 0 with 42 rules applied. Total rules applied 84 place count 196 transition count 355
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Iterating post reduction 0 with 11 rules applied. Total rules applied 95 place count 196 transition count 344
Discarding 37 places :
Symmetric choice reduction at 1 with 37 rule applications. Total rules 132 place count 159 transition count 307
Iterating global reduction 1 with 37 rules applied. Total rules applied 169 place count 159 transition count 307
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 1 with 12 rules applied. Total rules applied 181 place count 159 transition count 295
Discarding 13 places :
Symmetric choice reduction at 2 with 13 rule applications. Total rules 194 place count 146 transition count 273
Iterating global reduction 2 with 13 rules applied. Total rules applied 207 place count 146 transition count 273
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 2 with 13 rules applied. Total rules applied 220 place count 146 transition count 260
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 224 place count 142 transition count 256
Iterating global reduction 3 with 4 rules applied. Total rules applied 228 place count 142 transition count 256
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 232 place count 138 transition count 252
Iterating global reduction 3 with 4 rules applied. Total rules applied 236 place count 138 transition count 252
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 240 place count 134 transition count 248
Iterating global reduction 3 with 4 rules applied. Total rules applied 244 place count 134 transition count 248
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 247 place count 131 transition count 245
Iterating global reduction 3 with 3 rules applied. Total rules applied 250 place count 131 transition count 245
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 251 place count 130 transition count 242
Iterating global reduction 3 with 1 rules applied. Total rules applied 252 place count 130 transition count 242
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 253 place count 129 transition count 241
Iterating global reduction 3 with 1 rules applied. Total rules applied 254 place count 129 transition count 241
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 255 place count 128 transition count 240
Iterating global reduction 3 with 1 rules applied. Total rules applied 256 place count 128 transition count 240
Applied a total of 256 rules in 20 ms. Remains 128 /238 variables (removed 110) and now considering 240/797 (removed 557) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 20 ms. Remains : 128/238 places, 240/797 transitions.
[2023-03-19 18:04:57] [INFO ] Flatten gal took : 9 ms
[2023-03-19 18:04:57] [INFO ] Flatten gal took : 9 ms
[2023-03-19 18:04:57] [INFO ] Input system was already deterministic with 240 transitions.
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 797/797 transitions.
Discarding 47 places :
Symmetric choice reduction at 0 with 47 rule applications. Total rules 47 place count 191 transition count 280
Iterating global reduction 0 with 47 rules applied. Total rules applied 94 place count 191 transition count 280
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 0 with 6 rules applied. Total rules applied 100 place count 191 transition count 274
Discarding 42 places :
Symmetric choice reduction at 1 with 42 rule applications. Total rules 142 place count 149 transition count 232
Iterating global reduction 1 with 42 rules applied. Total rules applied 184 place count 149 transition count 232
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 1 with 15 rules applied. Total rules applied 199 place count 149 transition count 217
Discarding 17 places :
Symmetric choice reduction at 2 with 17 rule applications. Total rules 216 place count 132 transition count 187
Iterating global reduction 2 with 17 rules applied. Total rules applied 233 place count 132 transition count 187
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 2 with 12 rules applied. Total rules applied 245 place count 132 transition count 175
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 250 place count 127 transition count 170
Iterating global reduction 3 with 5 rules applied. Total rules applied 255 place count 127 transition count 170
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 260 place count 122 transition count 165
Iterating global reduction 3 with 5 rules applied. Total rules applied 265 place count 122 transition count 165
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 269 place count 118 transition count 161
Iterating global reduction 3 with 4 rules applied. Total rules applied 273 place count 118 transition count 161
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 276 place count 115 transition count 158
Iterating global reduction 3 with 3 rules applied. Total rules applied 279 place count 115 transition count 158
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 280 place count 114 transition count 155
Iterating global reduction 3 with 1 rules applied. Total rules applied 281 place count 114 transition count 155
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 282 place count 113 transition count 154
Iterating global reduction 3 with 1 rules applied. Total rules applied 283 place count 113 transition count 154
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 284 place count 112 transition count 153
Iterating global reduction 3 with 1 rules applied. Total rules applied 285 place count 112 transition count 153
Applied a total of 285 rules in 16 ms. Remains 112 /238 variables (removed 126) and now considering 153/797 (removed 644) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 18 ms. Remains : 112/238 places, 153/797 transitions.
[2023-03-19 18:04:57] [INFO ] Flatten gal took : 6 ms
[2023-03-19 18:04:57] [INFO ] Flatten gal took : 6 ms
[2023-03-19 18:04:57] [INFO ] Input system was already deterministic with 153 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 238/238 places, 797/797 transitions.
Discarding 39 places :
Symmetric choice reduction at 0 with 39 rule applications. Total rules 39 place count 199 transition count 386
Iterating global reduction 0 with 39 rules applied. Total rules applied 78 place count 199 transition count 386
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 0 with 13 rules applied. Total rules applied 91 place count 199 transition count 373
Discarding 34 places :
Symmetric choice reduction at 1 with 34 rule applications. Total rules 125 place count 165 transition count 339
Iterating global reduction 1 with 34 rules applied. Total rules applied 159 place count 165 transition count 339
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Iterating post reduction 1 with 11 rules applied. Total rules applied 170 place count 165 transition count 328
Discarding 12 places :
Symmetric choice reduction at 2 with 12 rule applications. Total rules 182 place count 153 transition count 308
Iterating global reduction 2 with 12 rules applied. Total rules applied 194 place count 153 transition count 308
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 2 with 16 rules applied. Total rules applied 210 place count 153 transition count 292
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 213 place count 150 transition count 289
Iterating global reduction 3 with 3 rules applied. Total rules applied 216 place count 150 transition count 289
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 219 place count 147 transition count 286
Iterating global reduction 3 with 3 rules applied. Total rules applied 222 place count 147 transition count 286
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 225 place count 144 transition count 283
Iterating global reduction 3 with 3 rules applied. Total rules applied 228 place count 144 transition count 283
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 231 place count 141 transition count 280
Iterating global reduction 3 with 3 rules applied. Total rules applied 234 place count 141 transition count 280
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 235 place count 140 transition count 277
Iterating global reduction 3 with 1 rules applied. Total rules applied 236 place count 140 transition count 277
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 237 place count 139 transition count 276
Iterating global reduction 3 with 1 rules applied. Total rules applied 238 place count 139 transition count 276
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 239 place count 138 transition count 275
Iterating global reduction 3 with 1 rules applied. Total rules applied 240 place count 138 transition count 275
Applied a total of 240 rules in 36 ms. Remains 138 /238 variables (removed 100) and now considering 275/797 (removed 522) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 36 ms. Remains : 138/238 places, 275/797 transitions.
[2023-03-19 18:04:57] [INFO ] Flatten gal took : 9 ms
[2023-03-19 18:04:57] [INFO ] Flatten gal took : 11 ms
[2023-03-19 18:04:57] [INFO ] Input system was already deterministic with 275 transitions.
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 797/797 transitions.
Discarding 44 places :
Symmetric choice reduction at 0 with 44 rule applications. Total rules 44 place count 194 transition count 311
Iterating global reduction 0 with 44 rules applied. Total rules applied 88 place count 194 transition count 311
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 0 with 8 rules applied. Total rules applied 96 place count 194 transition count 303
Discarding 39 places :
Symmetric choice reduction at 1 with 39 rule applications. Total rules 135 place count 155 transition count 264
Iterating global reduction 1 with 39 rules applied. Total rules applied 174 place count 155 transition count 264
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 1 with 14 rules applied. Total rules applied 188 place count 155 transition count 250
Discarding 14 places :
Symmetric choice reduction at 2 with 14 rule applications. Total rules 202 place count 141 transition count 226
Iterating global reduction 2 with 14 rules applied. Total rules applied 216 place count 141 transition count 226
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 2 with 12 rules applied. Total rules applied 228 place count 141 transition count 214
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 231 place count 138 transition count 211
Iterating global reduction 3 with 3 rules applied. Total rules applied 234 place count 138 transition count 211
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 237 place count 135 transition count 208
Iterating global reduction 3 with 3 rules applied. Total rules applied 240 place count 135 transition count 208
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 243 place count 132 transition count 205
Iterating global reduction 3 with 3 rules applied. Total rules applied 246 place count 132 transition count 205
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 248 place count 130 transition count 203
Iterating global reduction 3 with 2 rules applied. Total rules applied 250 place count 130 transition count 203
Applied a total of 250 rules in 14 ms. Remains 130 /238 variables (removed 108) and now considering 203/797 (removed 594) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 14 ms. Remains : 130/238 places, 203/797 transitions.
[2023-03-19 18:04:57] [INFO ] Flatten gal took : 7 ms
[2023-03-19 18:04:57] [INFO ] Flatten gal took : 8 ms
[2023-03-19 18:04:57] [INFO ] Input system was already deterministic with 203 transitions.
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 797/797 transitions.
Discarding 46 places :
Symmetric choice reduction at 0 with 46 rule applications. Total rules 46 place count 192 transition count 295
Iterating global reduction 0 with 46 rules applied. Total rules applied 92 place count 192 transition count 295
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 0 with 7 rules applied. Total rules applied 99 place count 192 transition count 288
Discarding 41 places :
Symmetric choice reduction at 1 with 41 rule applications. Total rules 140 place count 151 transition count 247
Iterating global reduction 1 with 41 rules applied. Total rules applied 181 place count 151 transition count 247
Ensure Unique test removed 17 transitions
Reduce isomorphic transitions removed 17 transitions.
Iterating post reduction 1 with 17 rules applied. Total rules applied 198 place count 151 transition count 230
Discarding 16 places :
Symmetric choice reduction at 2 with 16 rule applications. Total rules 214 place count 135 transition count 202
Iterating global reduction 2 with 16 rules applied. Total rules applied 230 place count 135 transition count 202
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 2 with 12 rules applied. Total rules applied 242 place count 135 transition count 190
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 246 place count 131 transition count 186
Iterating global reduction 3 with 4 rules applied. Total rules applied 250 place count 131 transition count 186
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 254 place count 127 transition count 182
Iterating global reduction 3 with 4 rules applied. Total rules applied 258 place count 127 transition count 182
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 262 place count 123 transition count 178
Iterating global reduction 3 with 4 rules applied. Total rules applied 266 place count 123 transition count 178
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 269 place count 120 transition count 175
Iterating global reduction 3 with 3 rules applied. Total rules applied 272 place count 120 transition count 175
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 273 place count 119 transition count 172
Iterating global reduction 3 with 1 rules applied. Total rules applied 274 place count 119 transition count 172
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 275 place count 118 transition count 171
Iterating global reduction 3 with 1 rules applied. Total rules applied 276 place count 118 transition count 171
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 277 place count 117 transition count 170
Iterating global reduction 3 with 1 rules applied. Total rules applied 278 place count 117 transition count 170
Applied a total of 278 rules in 17 ms. Remains 117 /238 variables (removed 121) and now considering 170/797 (removed 627) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 17 ms. Remains : 117/238 places, 170/797 transitions.
[2023-03-19 18:04:57] [INFO ] Flatten gal took : 5 ms
[2023-03-19 18:04:57] [INFO ] Flatten gal took : 6 ms
[2023-03-19 18:04:57] [INFO ] Input system was already deterministic with 170 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 238/238 places, 797/797 transitions.
Discarding 46 places :
Symmetric choice reduction at 0 with 46 rule applications. Total rules 46 place count 192 transition count 267
Iterating global reduction 0 with 46 rules applied. Total rules applied 92 place count 192 transition count 267
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 96 place count 192 transition count 263
Discarding 42 places :
Symmetric choice reduction at 1 with 42 rule applications. Total rules 138 place count 150 transition count 221
Iterating global reduction 1 with 42 rules applied. Total rules applied 180 place count 150 transition count 221
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 1 with 15 rules applied. Total rules applied 195 place count 150 transition count 206
Discarding 17 places :
Symmetric choice reduction at 2 with 17 rule applications. Total rules 212 place count 133 transition count 176
Iterating global reduction 2 with 17 rules applied. Total rules applied 229 place count 133 transition count 176
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 2 with 12 rules applied. Total rules applied 241 place count 133 transition count 164
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 246 place count 128 transition count 159
Iterating global reduction 3 with 5 rules applied. Total rules applied 251 place count 128 transition count 159
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 256 place count 123 transition count 154
Iterating global reduction 3 with 5 rules applied. Total rules applied 261 place count 123 transition count 154
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 265 place count 119 transition count 150
Iterating global reduction 3 with 4 rules applied. Total rules applied 269 place count 119 transition count 150
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 271 place count 119 transition count 148
Discarding 3 places :
Symmetric choice reduction at 4 with 3 rule applications. Total rules 274 place count 116 transition count 145
Iterating global reduction 4 with 3 rules applied. Total rules applied 277 place count 116 transition count 145
Applied a total of 277 rules in 22 ms. Remains 116 /238 variables (removed 122) and now considering 145/797 (removed 652) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 22 ms. Remains : 116/238 places, 145/797 transitions.
[2023-03-19 18:04:57] [INFO ] Flatten gal took : 4 ms
[2023-03-19 18:04:57] [INFO ] Flatten gal took : 5 ms
[2023-03-19 18:04:57] [INFO ] Input system was already deterministic with 145 transitions.
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 797/797 transitions.
Discarding 44 places :
Symmetric choice reduction at 0 with 44 rule applications. Total rules 44 place count 194 transition count 325
Iterating global reduction 0 with 44 rules applied. Total rules applied 88 place count 194 transition count 325
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 0 with 9 rules applied. Total rules applied 97 place count 194 transition count 316
Discarding 38 places :
Symmetric choice reduction at 1 with 38 rule applications. Total rules 135 place count 156 transition count 278
Iterating global reduction 1 with 38 rules applied. Total rules applied 173 place count 156 transition count 278
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 1 with 13 rules applied. Total rules applied 186 place count 156 transition count 265
Discarding 14 places :
Symmetric choice reduction at 2 with 14 rule applications. Total rules 200 place count 142 transition count 241
Iterating global reduction 2 with 14 rules applied. Total rules applied 214 place count 142 transition count 241
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 2 with 12 rules applied. Total rules applied 226 place count 142 transition count 229
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 230 place count 138 transition count 225
Iterating global reduction 3 with 4 rules applied. Total rules applied 234 place count 138 transition count 225
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 238 place count 134 transition count 221
Iterating global reduction 3 with 4 rules applied. Total rules applied 242 place count 134 transition count 221
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 246 place count 130 transition count 217
Iterating global reduction 3 with 4 rules applied. Total rules applied 250 place count 130 transition count 217
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 253 place count 127 transition count 214
Iterating global reduction 3 with 3 rules applied. Total rules applied 256 place count 127 transition count 214
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 257 place count 126 transition count 211
Iterating global reduction 3 with 1 rules applied. Total rules applied 258 place count 126 transition count 211
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 259 place count 125 transition count 210
Iterating global reduction 3 with 1 rules applied. Total rules applied 260 place count 125 transition count 210
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 261 place count 124 transition count 209
Iterating global reduction 3 with 1 rules applied. Total rules applied 262 place count 124 transition count 209
Applied a total of 262 rules in 16 ms. Remains 124 /238 variables (removed 114) and now considering 209/797 (removed 588) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 17 ms. Remains : 124/238 places, 209/797 transitions.
[2023-03-19 18:04:57] [INFO ] Flatten gal took : 7 ms
[2023-03-19 18:04:57] [INFO ] Flatten gal took : 7 ms
[2023-03-19 18:04:57] [INFO ] Input system was already deterministic with 209 transitions.
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 797/797 transitions.
Discarding 38 places :
Symmetric choice reduction at 0 with 38 rule applications. Total rules 38 place count 200 transition count 415
Iterating global reduction 0 with 38 rules applied. Total rules applied 76 place count 200 transition count 415
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 0 with 15 rules applied. Total rules applied 91 place count 200 transition count 400
Discarding 33 places :
Symmetric choice reduction at 1 with 33 rule applications. Total rules 124 place count 167 transition count 367
Iterating global reduction 1 with 33 rules applied. Total rules applied 157 place count 167 transition count 367
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 1 with 13 rules applied. Total rules applied 170 place count 167 transition count 354
Discarding 11 places :
Symmetric choice reduction at 2 with 11 rule applications. Total rules 181 place count 156 transition count 336
Iterating global reduction 2 with 11 rules applied. Total rules applied 192 place count 156 transition count 336
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 2 with 15 rules applied. Total rules applied 207 place count 156 transition count 321
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 211 place count 152 transition count 317
Iterating global reduction 3 with 4 rules applied. Total rules applied 215 place count 152 transition count 317
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 219 place count 148 transition count 313
Iterating global reduction 3 with 4 rules applied. Total rules applied 223 place count 148 transition count 313
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 227 place count 144 transition count 309
Iterating global reduction 3 with 4 rules applied. Total rules applied 231 place count 144 transition count 309
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 234 place count 141 transition count 306
Iterating global reduction 3 with 3 rules applied. Total rules applied 237 place count 141 transition count 306
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 238 place count 140 transition count 303
Iterating global reduction 3 with 1 rules applied. Total rules applied 239 place count 140 transition count 303
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 240 place count 139 transition count 302
Iterating global reduction 3 with 1 rules applied. Total rules applied 241 place count 139 transition count 302
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 242 place count 138 transition count 301
Iterating global reduction 3 with 1 rules applied. Total rules applied 243 place count 138 transition count 301
Applied a total of 243 rules in 20 ms. Remains 138 /238 variables (removed 100) and now considering 301/797 (removed 496) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 138/238 places, 301/797 transitions.
[2023-03-19 18:04:57] [INFO ] Flatten gal took : 10 ms
[2023-03-19 18:04:58] [INFO ] Flatten gal took : 10 ms
[2023-03-19 18:04:58] [INFO ] Input system was already deterministic with 301 transitions.
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 797/797 transitions.
Discarding 40 places :
Symmetric choice reduction at 0 with 40 rule applications. Total rules 40 place count 198 transition count 347
Iterating global reduction 0 with 40 rules applied. Total rules applied 80 place count 198 transition count 347
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 0 with 9 rules applied. Total rules applied 89 place count 198 transition count 338
Discarding 36 places :
Symmetric choice reduction at 1 with 36 rule applications. Total rules 125 place count 162 transition count 302
Iterating global reduction 1 with 36 rules applied. Total rules applied 161 place count 162 transition count 302
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 177 place count 162 transition count 286
Discarding 11 places :
Symmetric choice reduction at 2 with 11 rule applications. Total rules 188 place count 151 transition count 266
Iterating global reduction 2 with 11 rules applied. Total rules applied 199 place count 151 transition count 266
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 2 with 4 rules applied. Total rules applied 203 place count 151 transition count 262
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 207 place count 147 transition count 258
Iterating global reduction 3 with 4 rules applied. Total rules applied 211 place count 147 transition count 258
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 215 place count 143 transition count 254
Iterating global reduction 3 with 4 rules applied. Total rules applied 219 place count 143 transition count 254
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 222 place count 140 transition count 251
Iterating global reduction 3 with 3 rules applied. Total rules applied 225 place count 140 transition count 251
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 227 place count 138 transition count 249
Iterating global reduction 3 with 2 rules applied. Total rules applied 229 place count 138 transition count 249
Applied a total of 229 rules in 15 ms. Remains 138 /238 variables (removed 100) and now considering 249/797 (removed 548) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16 ms. Remains : 138/238 places, 249/797 transitions.
[2023-03-19 18:04:58] [INFO ] Flatten gal took : 8 ms
[2023-03-19 18:04:58] [INFO ] Flatten gal took : 9 ms
[2023-03-19 18:04:58] [INFO ] Input system was already deterministic with 249 transitions.
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 797/797 transitions.
Discarding 47 places :
Symmetric choice reduction at 0 with 47 rule applications. Total rules 47 place count 191 transition count 266
Iterating global reduction 0 with 47 rules applied. Total rules applied 94 place count 191 transition count 266
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 99 place count 191 transition count 261
Discarding 42 places :
Symmetric choice reduction at 1 with 42 rule applications. Total rules 141 place count 149 transition count 219
Iterating global reduction 1 with 42 rules applied. Total rules applied 183 place count 149 transition count 219
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 1 with 15 rules applied. Total rules applied 198 place count 149 transition count 204
Discarding 17 places :
Symmetric choice reduction at 2 with 17 rule applications. Total rules 215 place count 132 transition count 174
Iterating global reduction 2 with 17 rules applied. Total rules applied 232 place count 132 transition count 174
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 2 with 12 rules applied. Total rules applied 244 place count 132 transition count 162
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 249 place count 127 transition count 157
Iterating global reduction 3 with 5 rules applied. Total rules applied 254 place count 127 transition count 157
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 259 place count 122 transition count 152
Iterating global reduction 3 with 5 rules applied. Total rules applied 264 place count 122 transition count 152
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 268 place count 118 transition count 148
Iterating global reduction 3 with 4 rules applied. Total rules applied 272 place count 118 transition count 148
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 274 place count 118 transition count 146
Discarding 3 places :
Symmetric choice reduction at 4 with 3 rule applications. Total rules 277 place count 115 transition count 143
Iterating global reduction 4 with 3 rules applied. Total rules applied 280 place count 115 transition count 143
Applied a total of 280 rules in 12 ms. Remains 115 /238 variables (removed 123) and now considering 143/797 (removed 654) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 13 ms. Remains : 115/238 places, 143/797 transitions.
[2023-03-19 18:04:58] [INFO ] Flatten gal took : 4 ms
[2023-03-19 18:04:58] [INFO ] Flatten gal took : 5 ms
[2023-03-19 18:04:58] [INFO ] Input system was already deterministic with 143 transitions.
[2023-03-19 18:04:58] [INFO ] Flatten gal took : 19 ms
[2023-03-19 18:04:58] [INFO ] Flatten gal took : 17 ms
[2023-03-19 18:04:58] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-19 18:04:58] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 238 places, 797 transitions and 3150 arcs took 4 ms.
Total runtime 97876 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SieveSingleMsgMbox-PT-d2m64
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376
CTLFireability

FORMULA SieveSingleMsgMbox-PT-d2m64-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d2m64-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d2m64-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d2m64-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d2m64-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679249724430

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 11 (type EXCL) for 10 SieveSingleMsgMbox-PT-d2m64-CTLFireability-02
lola: time limit : 119 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 11 (type EXCL) for SieveSingleMsgMbox-PT-d2m64-CTLFireability-02
lola: result : true
lola: markings : 12
lola: fired transitions : 57
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 SieveSingleMsgMbox-PT-d2m64-CTLFireability-07
lola: time limit : 128 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:738
lola: rewrite Frontend/Parser/formula_rewrite.k:694
lola: LAUNCH task # 69 (type FNDP) for 16 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 70 (type EQUN) for 16 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 72 (type SRCH) for 16 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 72 (type SRCH) for SieveSingleMsgMbox-PT-d2m64-CTLFireability-04
lola: result : unknown
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
sara: try reading problem file /home/mcc/execution/376/CTLFireability-70.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:735
lola: rewrite Frontend/Parser/formula_rewrite.k:695
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d2m64-CTLFireability-02: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d2m64-CTLFireability-00: CONJ 0 2 0 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 4/179 2/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-07 413229 m, 82645 m/sec, 519439 t fired, .
69 EF FNDP 4/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 524230 t fired, 73593 attempts, .
70 EF STEQ 4/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d2m64-CTLFireability-00: CONJ 0 2 0 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 9/179 4/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-07 867963 m, 90946 m/sec, 1133085 t fired, .
69 EF FNDP 9/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 1118901 t fired, 157117 attempts, .
70 EF STEQ 9/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d2m64-CTLFireability-00: CONJ 0 2 0 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 14/179 7/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-07 1330141 m, 92435 m/sec, 1714425 t fired, .
69 EF FNDP 14/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 1716927 t fired, 240967 attempts, .
70 EF STEQ 14/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-00: CONJ 0 2 0 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 19/179 9/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-07 1786925 m, 91356 m/sec, 2292997 t fired, .
69 EF FNDP 19/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 2328692 t fired, 327008 attempts, .
70 EF STEQ 19/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d2m64-CTLFireability-00: CONJ 0 2 0 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 24/179 11/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-07 2242858 m, 91186 m/sec, 2894215 t fired, .
69 EF FNDP 24/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 2947023 t fired, 414004 attempts, .
70 EF STEQ 24/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

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26 CTL EXCL 29/179 13/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-07 2691493 m, 89727 m/sec, 3526113 t fired, .
69 EF FNDP 29/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 3558112 t fired, 499690 attempts, .
70 EF STEQ 29/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

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26 CTL EXCL 34/179 15/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-07 3143584 m, 90418 m/sec, 4124970 t fired, .
69 EF FNDP 34/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 4140337 t fired, 581387 attempts, .
70 EF STEQ 34/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

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26 CTL EXCL 39/179 17/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-07 3589635 m, 89210 m/sec, 4778551 t fired, .
69 EF FNDP 39/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 4720667 t fired, 662913 attempts, .
70 EF STEQ 39/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

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26 CTL EXCL 44/179 19/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-07 4042813 m, 90635 m/sec, 5357713 t fired, .
69 EF FNDP 44/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 5301375 t fired, 744411 attempts, .
70 EF STEQ 44/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

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26 CTL EXCL 49/179 21/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-07 4502293 m, 91896 m/sec, 5929711 t fired, .
69 EF FNDP 49/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 5883737 t fired, 826237 attempts, .
70 EF STEQ 49/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 54/179 23/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-07 4957353 m, 91012 m/sec, 6510812 t fired, .
69 EF FNDP 54/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 6468979 t fired, 908643 attempts, .
70 EF STEQ 54/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

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26 CTL EXCL 59/179 25/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-07 5412044 m, 90938 m/sec, 7101626 t fired, .
69 EF FNDP 59/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 7055903 t fired, 991324 attempts, .
70 EF STEQ 59/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

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26 CTL EXCL 64/179 27/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-07 5864355 m, 90462 m/sec, 7681438 t fired, .
69 EF FNDP 64/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 7641765 t fired, 1073617 attempts, .
70 EF STEQ 64/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

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26 CTL EXCL 69/179 28/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-07 6310738 m, 89276 m/sec, 8282553 t fired, .
69 EF FNDP 69/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 8227657 t fired, 1155958 attempts, .
70 EF STEQ 69/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

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26 CTL EXCL 74/179 30/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-07 6764023 m, 90657 m/sec, 8845124 t fired, .
69 EF FNDP 74/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 8813004 t fired, 1238272 attempts, .
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 79/179 32/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-07 7219669 m, 91129 m/sec, 9409878 t fired, .
69 EF FNDP 79/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 9405035 t fired, 1321474 attempts, .
70 EF STEQ 79/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
69 EF FNDP 84/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 9992131 t fired, 1404128 attempts, .
70 EF STEQ 84/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-02: CTL true CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 EXEF EXCL 5/195 3/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-15 625308 m, 125061 m/sec, 749532 t fired, .
69 EF FNDP 89/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 10580727 t fired, 1487132 attempts, .
70 EF STEQ 89/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 EXEF EXCL 10/195 6/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-15 1333660 m, 141670 m/sec, 1606311 t fired, .
69 EF FNDP 94/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 11168732 t fired, 1569578 attempts, .
70 EF STEQ 94/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 EXEF EXCL 15/195 9/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-15 2038314 m, 140930 m/sec, 2469597 t fired, .
69 EF FNDP 99/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 11767294 t fired, 1653872 attempts, .
70 EF STEQ 99/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-00: CONJ 0 2 0 0 2 0 0 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 EXEF EXCL 20/195 11/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-15 2748383 m, 142013 m/sec, 3335706 t fired, .
69 EF FNDP 104/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 12354157 t fired, 1736362 attempts, .
70 EF STEQ 104/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 EXEF EXCL 25/195 14/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-15 3449762 m, 140275 m/sec, 4203754 t fired, .
69 EF FNDP 109/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 12938157 t fired, 1818395 attempts, .
70 EF STEQ 109/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 EXEF EXCL 30/195 17/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-15 4162210 m, 142489 m/sec, 5065598 t fired, .
69 EF FNDP 114/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 13524660 t fired, 1901168 attempts, .
70 EF STEQ 114/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 EXEF EXCL 35/195 20/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-15 4867801 m, 141118 m/sec, 5938981 t fired, .
69 EF FNDP 119/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 14115340 t fired, 1984159 attempts, .
70 EF STEQ 119/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 EXEF EXCL 40/195 22/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-15 5566932 m, 139826 m/sec, 6804637 t fired, .
69 EF FNDP 124/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 14701423 t fired, 2066551 attempts, .
70 EF STEQ 124/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 1 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 EXEF EXCL 45/195 25/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-15 6265320 m, 139677 m/sec, 7682345 t fired, .
69 EF FNDP 129/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 15288033 t fired, 2149044 attempts, .
70 EF STEQ 129/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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64 EXEF EXCL 50/195 28/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-15 6983581 m, 143652 m/sec, 8530364 t fired, .
69 EF FNDP 134/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 15868821 t fired, 2230872 attempts, .
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 1 0 0 1 0 0 0
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64 EXEF EXCL 55/195 30/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-15 7679699 m, 139223 m/sec, 9414313 t fired, .
69 EF FNDP 139/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 16458423 t fired, 2313733 attempts, .
70 EF STEQ 139/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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69 EF FNDP 144/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 17048271 t fired, 2396724 attempts, .
70 EF STEQ 144/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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53 EXEF EXCL 5/230 3/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-12 664521 m, 132904 m/sec, 799498 t fired, .
69 EF FNDP 149/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 17640961 t fired, 2479894 attempts, .
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53 EXEF EXCL 10/230 6/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-12 1371755 m, 141446 m/sec, 1660238 t fired, .
69 EF FNDP 154/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 18233857 t fired, 2563380 attempts, .
70 EF STEQ 154/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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53 EXEF EXCL 15/230 9/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-12 2075152 m, 140679 m/sec, 2522497 t fired, .
69 EF FNDP 159/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 18827066 t fired, 2646997 attempts, .
70 EF STEQ 159/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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53 EXEF EXCL 20/230 13/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-12 2796607 m, 144291 m/sec, 3383422 t fired, .
69 EF FNDP 164/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 19419652 t fired, 2730170 attempts, .
70 EF STEQ 164/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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53 EXEF EXCL 25/230 16/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-12 3500735 m, 140825 m/sec, 4240034 t fired, .
69 EF FNDP 169/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 20013287 t fired, 2813481 attempts, .
70 EF STEQ 169/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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53 EXEF EXCL 30/230 19/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-12 4215368 m, 142926 m/sec, 5106293 t fired, .
69 EF FNDP 174/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 20607788 t fired, 2897078 attempts, .
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53 EXEF EXCL 35/230 21/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-12 4905056 m, 137937 m/sec, 5965376 t fired, .
69 EF FNDP 179/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 21201543 t fired, 2980740 attempts, .
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53 EXEF EXCL 40/230 25/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-12 5632896 m, 145568 m/sec, 6811578 t fired, .
69 EF FNDP 184/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 21795121 t fired, 3064147 attempts, .
70 EF STEQ 184/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 45/230 28/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-12 6330508 m, 139522 m/sec, 7680224 t fired, .
69 EF FNDP 189/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 22388280 t fired, 3147240 attempts, .
70 EF STEQ 189/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EXEF EXCL 50/230 30/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-12 7007492 m, 135396 m/sec, 8540364 t fired, .
69 EF FNDP 194/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 22981681 t fired, 3230789 attempts, .
70 EF STEQ 194/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
69 EF FNDP 199/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 23575053 t fired, 3314131 attempts, .
70 EF STEQ 199/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-02: CTL true CTL model checker
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 5/261 4/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-09 779308 m, 155861 m/sec, 1028199 t fired, .
69 EF FNDP 204/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 24167213 t fired, 3397256 attempts, .
70 EF STEQ 204/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 10/261 8/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-09 1615359 m, 167210 m/sec, 2083732 t fired, .
69 EF FNDP 209/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 24759171 t fired, 3480658 attempts, .
70 EF STEQ 209/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 15/261 11/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-09 2434297 m, 163787 m/sec, 3157555 t fired, .
69 EF FNDP 214/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 25349643 t fired, 3563698 attempts, .
70 EF STEQ 214/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 20/261 15/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-09 3238685 m, 160877 m/sec, 4257275 t fired, .
69 EF FNDP 219/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 25943516 t fired, 3647061 attempts, .
70 EF STEQ 219/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 25/261 19/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-09 4047156 m, 161694 m/sec, 5364550 t fired, .
69 EF FNDP 224/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 26537463 t fired, 3730433 attempts, .
70 EF STEQ 224/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 30/261 22/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-09 4881380 m, 166844 m/sec, 6418022 t fired, .
69 EF FNDP 229/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 27129987 t fired, 3813734 attempts, .
70 EF STEQ 229/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 35/261 26/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-09 5707239 m, 165171 m/sec, 7474211 t fired, .
69 EF FNDP 234/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 27724142 t fired, 3897220 attempts, .
70 EF STEQ 234/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 40/261 29/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-09 6519952 m, 162542 m/sec, 8536841 t fired, .
69 EF FNDP 239/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 28316835 t fired, 3980643 attempts, .
70 EF STEQ 239/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
69 EF FNDP 244/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 28913113 t fired, 4064645 attempts, .
70 EF STEQ 244/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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23 CTL EXCL 5/279 4/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-06 778568 m, 155713 m/sec, 1026941 t fired, .
69 EF FNDP 249/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 29509262 t fired, 4148014 attempts, .
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 10/279 8/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-06 1609672 m, 166220 m/sec, 2077291 t fired, .
69 EF FNDP 254/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 30105840 t fired, 4231852 attempts, .
70 EF STEQ 254/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 15/279 11/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-06 2425864 m, 163238 m/sec, 3144897 t fired, .
69 EF FNDP 259/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 30699448 t fired, 4315174 attempts, .
70 EF STEQ 259/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 20/279 15/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-06 3226594 m, 160146 m/sec, 4238319 t fired, .
69 EF FNDP 264/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 31294786 t fired, 4398755 attempts, .
70 EF STEQ 264/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

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23 CTL EXCL 25/279 18/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-06 4032053 m, 161091 m/sec, 5341495 t fired, .
69 EF FNDP 269/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 31892468 t fired, 4482699 attempts, .
70 EF STEQ 269/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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23 CTL EXCL 31/279 22/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-06 4859541 m, 165497 m/sec, 6393159 t fired, .
69 EF FNDP 275/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 32488017 t fired, 4566207 attempts, .
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

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23 CTL EXCL 36/279 26/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-06 5677623 m, 163616 m/sec, 7437178 t fired, .
69 EF FNDP 280/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 33104033 t fired, 4652886 attempts, .
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23 CTL EXCL 41/279 29/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-06 6487437 m, 161962 m/sec, 8494155 t fired, .
69 EF FNDP 285/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 33720856 t fired, 4739640 attempts, .
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69 EF FNDP 290/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 34335606 t fired, 4826094 attempts, .
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-00: CONJ 0 1 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 5/300 4/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-00 839711 m, 167942 m/sec, 1100320 t fired, .
69 EF FNDP 295/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 34960386 t fired, 4914102 attempts, .
70 EF STEQ 295/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-02: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL false CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 10/300 8/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-00 1601667 m, 152391 m/sec, 2067526 t fired, .
69 EF FNDP 300/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 35530978 t fired, 4994458 attempts, .
70 EF STEQ 300/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-02: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL false CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 15/300 11/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-00 2369429 m, 153552 m/sec, 3066873 t fired, .
69 EF FNDP 305/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 36094113 t fired, 5073518 attempts, .
70 EF STEQ 305/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-02: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL false CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 20/300 15/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-00 3143508 m, 154815 m/sec, 4124886 t fired, .
69 EF FNDP 310/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 36666183 t fired, 5153934 attempts, .
70 EF STEQ 310/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-02: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL false CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-00: CONJ 0 1 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 25/300 18/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-00 3934942 m, 158286 m/sec, 5219397 t fired, .
69 EF FNDP 315/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 37272351 t fired, 5238945 attempts, .
70 EF STEQ 315/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-02: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL false CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-00: CONJ 0 1 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 30/300 22/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-00 4744721 m, 161955 m/sec, 6234461 t fired, .
69 EF FNDP 320/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 37856709 t fired, 5321000 attempts, .
70 EF STEQ 320/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-02: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL false CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-00: CONJ 0 1 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 35/300 25/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-00 5555708 m, 162197 m/sec, 7283723 t fired, .
69 EF FNDP 325/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 38424472 t fired, 5400585 attempts, .
70 EF STEQ 325/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-02: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL false CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-00: CONJ 0 1 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 40/300 28/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-00 6284691 m, 145796 m/sec, 8252178 t fired, .
69 EF FNDP 330/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 38961579 t fired, 5475856 attempts, .
70 EF STEQ 330/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-02: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL false CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-00: CONJ 0 1 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 45/300 32/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-00 7055364 m, 154134 m/sec, 9204671 t fired, .
69 EF FNDP 335/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 39499456 t fired, 5551540 attempts, .
70 EF STEQ 335/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-02: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL false CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-00: CONJ 0 1 0 0 2 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
69 EF FNDP 340/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 40108429 t fired, 5636808 attempts, .
70 EF STEQ 340/3599 0/5 SieveSingleMsgMbox-PT-d2m64-CTLFireability-04 sara is running.

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lola: result : true
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-02: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG false state space
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL false CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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74 AGEF EXCL 5/407 4/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-05 741054 m, 148210 m/sec, 965600 t fired, .

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74 AGEF EXCL 10/407 7/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-05 1534072 m, 158603 m/sec, 1972066 t fired, .

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14 CTL EXCL 25/1043 18/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-03 4032422 m, 161498 m/sec, 5342007 t fired, .

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3 CTL EXCL 15/1542 11/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-00 2402395 m, 160401 m/sec, 3112869 t fired, .

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3 CTL EXCL 20/1542 15/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-00 3147093 m, 148939 m/sec, 4130010 t fired, .

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3 CTL EXCL 25/1542 18/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-00 3890072 m, 148595 m/sec, 5160179 t fired, .

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3 CTL EXCL 30/1542 21/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-00 4669183 m, 155822 m/sec, 6138561 t fired, .

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3 CTL EXCL 45/1542 31/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-00 6967931 m, 153200 m/sec, 9093799 t fired, .

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 25/3034 15/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-01 3187848 m, 130453 m/sec, 7372703 t fired, .

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG false state space
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ false DISJ
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL false CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-00: CONJ 0 0 0 0 2 0 2 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 30/3034 18/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-01 3837025 m, 129835 m/sec, 8927288 t fired, .

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ false DISJ
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL false CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-00: CONJ 0 0 0 0 2 0 2 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

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8 CTL EXCL 35/3034 21/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-01 4508630 m, 134321 m/sec, 10447914 t fired, .

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ false DISJ
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL false CTL model checker
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 40/3034 24/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-01 5174589 m, 133191 m/sec, 11954326 t fired, .

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG false state space
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ false DISJ
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL false CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 45/3034 26/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-01 5833741 m, 131830 m/sec, 13473933 t fired, .

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ false DISJ
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL false CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 50/3034 29/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-01 6489258 m, 131103 m/sec, 14985899 t fired, .

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-02: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG false state space
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ false DISJ
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL false CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 55/3034 32/32 SieveSingleMsgMbox-PT-d2m64-CTLFireability-01 7151550 m, 132458 m/sec, 16482766 t fired, .

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SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG false state space
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ false DISJ
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL false CTL model checker
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
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SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d2m64-CTLFireability-00: CONJ unknown CONJ
SieveSingleMsgMbox-PT-d2m64-CTLFireability-01: CTL unknown AGGR
SieveSingleMsgMbox-PT-d2m64-CTLFireability-02: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-03: CTL unknown AGGR
SieveSingleMsgMbox-PT-d2m64-CTLFireability-04: AG false state space
SieveSingleMsgMbox-PT-d2m64-CTLFireability-05: EFAG unknown AGGR
SieveSingleMsgMbox-PT-d2m64-CTLFireability-06: CTL unknown AGGR
SieveSingleMsgMbox-PT-d2m64-CTLFireability-07: CTL unknown AGGR
SieveSingleMsgMbox-PT-d2m64-CTLFireability-08: DISJ false DISJ
SieveSingleMsgMbox-PT-d2m64-CTLFireability-09: CTL unknown AGGR
SieveSingleMsgMbox-PT-d2m64-CTLFireability-10: CTL false CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-11: EU unknown AGGR
SieveSingleMsgMbox-PT-d2m64-CTLFireability-12: EXEF unknown AGGR
SieveSingleMsgMbox-PT-d2m64-CTLFireability-13: CTL true CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-14: CTL false CTL model checker
SieveSingleMsgMbox-PT-d2m64-CTLFireability-15: DISJ unknown DISJ


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SieveSingleMsgMbox-PT-d2m64"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SieveSingleMsgMbox-PT-d2m64, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-tajo-167905976800482"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SieveSingleMsgMbox-PT-d2m64.tgz
mv SieveSingleMsgMbox-PT-d2m64 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;