fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r423-tajo-167905976700434
Last Updated
May 14, 2023

About the Execution of LoLa+red for SieveSingleMsgMbox-PT-d1m64

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16217.676 3600000.00 6604943.00 4956.00 ?TTFTTT?TF???TFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/mnt/tpsp/fkordon/mcc2023-input.r423-tajo-167905976700434.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2023-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SieveSingleMsgMbox-PT-d1m64, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r423-tajo-167905976700434
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 864K
-rw-r--r-- 1 mcc users 7.0K Feb 26 10:28 CTLCardinality.txt
-rw-r--r-- 1 mcc users 74K Feb 26 10:28 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.8K Feb 26 10:27 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 10:27 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 17:06 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:06 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 17:06 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 17:06 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 10:30 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 116K Feb 26 10:30 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Feb 26 10:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 26 10:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:06 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 17:06 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 450K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SieveSingleMsgMbox-PT-d1m64-CTLFireability-00
FORMULA_NAME SieveSingleMsgMbox-PT-d1m64-CTLFireability-01
FORMULA_NAME SieveSingleMsgMbox-PT-d1m64-CTLFireability-02
FORMULA_NAME SieveSingleMsgMbox-PT-d1m64-CTLFireability-03
FORMULA_NAME SieveSingleMsgMbox-PT-d1m64-CTLFireability-04
FORMULA_NAME SieveSingleMsgMbox-PT-d1m64-CTLFireability-05
FORMULA_NAME SieveSingleMsgMbox-PT-d1m64-CTLFireability-06
FORMULA_NAME SieveSingleMsgMbox-PT-d1m64-CTLFireability-07
FORMULA_NAME SieveSingleMsgMbox-PT-d1m64-CTLFireability-08
FORMULA_NAME SieveSingleMsgMbox-PT-d1m64-CTLFireability-09
FORMULA_NAME SieveSingleMsgMbox-PT-d1m64-CTLFireability-10
FORMULA_NAME SieveSingleMsgMbox-PT-d1m64-CTLFireability-11
FORMULA_NAME SieveSingleMsgMbox-PT-d1m64-CTLFireability-12
FORMULA_NAME SieveSingleMsgMbox-PT-d1m64-CTLFireability-13
FORMULA_NAME SieveSingleMsgMbox-PT-d1m64-CTLFireability-14
FORMULA_NAME SieveSingleMsgMbox-PT-d1m64-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679247358742

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SieveSingleMsgMbox-PT-d1m64
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-19 17:36:00] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-19 17:36:00] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-19 17:36:00] [INFO ] Load time of PNML (sax parser for PT used): 125 ms
[2023-03-19 17:36:00] [INFO ] Transformed 1295 places.
[2023-03-19 17:36:00] [INFO ] Transformed 749 transitions.
[2023-03-19 17:36:00] [INFO ] Parsed PT model containing 1295 places and 749 transitions and 2996 arcs in 273 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Deduced a syphon composed of 1036 places in 9 ms
Reduce places removed 1036 places and 0 transitions.
Support contains 65 out of 259 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 259/259 places, 749/749 transitions.
Reduce places removed 17 places and 0 transitions.
Ensure Unique test removed 240 transitions
Reduce isomorphic transitions removed 240 transitions.
Iterating post reduction 0 with 257 rules applied. Total rules applied 257 place count 242 transition count 509
Discarding 28 places :
Symmetric choice reduction at 1 with 28 rule applications. Total rules 285 place count 214 transition count 468
Iterating global reduction 1 with 28 rules applied. Total rules applied 313 place count 214 transition count 468
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 319 place count 214 transition count 462
Discarding 13 places :
Symmetric choice reduction at 2 with 13 rule applications. Total rules 332 place count 201 transition count 449
Iterating global reduction 2 with 13 rules applied. Total rules applied 345 place count 201 transition count 449
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 346 place count 201 transition count 448
Discarding 9 places :
Symmetric choice reduction at 3 with 9 rule applications. Total rules 355 place count 192 transition count 437
Iterating global reduction 3 with 9 rules applied. Total rules applied 364 place count 192 transition count 437
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 3 with 3 rules applied. Total rules applied 367 place count 192 transition count 434
Applied a total of 367 rules in 56 ms. Remains 192 /259 variables (removed 67) and now considering 434/749 (removed 315) transitions.
// Phase 1: matrix 434 rows 192 cols
[2023-03-19 17:36:00] [INFO ] Computed 5 place invariants in 16 ms
[2023-03-19 17:36:00] [INFO ] Implicit Places using invariants in 241 ms returned []
[2023-03-19 17:36:00] [INFO ] Invariant cache hit.
[2023-03-19 17:36:01] [INFO ] State equation strengthened by 303 read => feed constraints.
[2023-03-19 17:36:01] [INFO ] Implicit Places using invariants and state equation in 623 ms returned []
Implicit Place search using SMT with State Equation took 888 ms to find 0 implicit places.
[2023-03-19 17:36:01] [INFO ] Invariant cache hit.
[2023-03-19 17:36:01] [INFO ] Dead Transitions using invariants and state equation in 131 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 192/259 places, 434/749 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1075 ms. Remains : 192/259 places, 434/749 transitions.
Support contains 65 out of 192 places after structural reductions.
[2023-03-19 17:36:01] [INFO ] Flatten gal took : 50 ms
[2023-03-19 17:36:01] [INFO ] Flatten gal took : 22 ms
[2023-03-19 17:36:01] [INFO ] Input system was already deterministic with 434 transitions.
Support contains 64 out of 192 places (down from 65) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2238 resets, run finished after 284 ms. (steps per millisecond=35 ) properties (out of 62) seen :4
Incomplete Best-First random walk after 1000 steps, including 38 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 62 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1000 steps, including 46 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 49 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1000 steps, including 105 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 52 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 41 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 44 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 44 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 50 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 49 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 41 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 50 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 44 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 39 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 46 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1000 steps, including 43 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 106 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 97 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1000 steps, including 35 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 42 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 41 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 44 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 46 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1000 steps, including 54 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1000 steps, including 48 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 84 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1000 steps, including 48 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 43 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1000 steps, including 93 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 98 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 98 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 49 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1000 steps, including 45 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 46 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 42 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 56 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 42 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 38 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1000 steps, including 37 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1000 steps, including 51 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1000 steps, including 52 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1000 steps, including 39 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 42 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 42 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 96 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 43 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 100 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1000 steps, including 40 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 58) seen :0
Incomplete Best-First random walk after 1001 steps, including 44 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 58) seen :0
Interrupted probabilistic random walk after 313893 steps, run timeout after 3001 ms. (steps per millisecond=104 ) properties seen :{0=1, 4=1, 7=1, 9=1, 10=1, 11=1, 23=1, 25=1, 26=1, 27=1, 28=1, 29=1, 33=1, 34=1, 35=1, 36=1, 38=1, 45=1, 49=1, 51=1, 53=1, 54=1, 57=1}
Probabilistic random walk after 313893 steps, saw 146130 distinct states, run finished after 3002 ms. (steps per millisecond=104 ) properties seen :23
Running SMT prover for 35 properties.
[2023-03-19 17:36:05] [INFO ] Invariant cache hit.
[2023-03-19 17:36:06] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:06] [INFO ] [Real]Absence check using 2 positive and 3 generalized place invariants in 8 ms returned sat
[2023-03-19 17:36:06] [INFO ] After 464ms SMT Verify possible using all constraints in real domain returned unsat :4 sat :0 real:31
[2023-03-19 17:36:06] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 17:36:06] [INFO ] [Nat]Absence check using 2 positive and 3 generalized place invariants in 4 ms returned sat
[2023-03-19 17:36:07] [INFO ] After 1126ms SMT Verify possible using state equation in natural domain returned unsat :8 sat :27
[2023-03-19 17:36:07] [INFO ] State equation strengthened by 303 read => feed constraints.
[2023-03-19 17:36:10] [INFO ] After 2431ms SMT Verify possible using 303 Read/Feed constraints in natural domain returned unsat :8 sat :27
[2023-03-19 17:36:10] [INFO ] Deduced a trap composed of 72 places in 47 ms of which 6 ms to minimize.
[2023-03-19 17:36:10] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 76 ms
[2023-03-19 17:36:12] [INFO ] After 4817ms SMT Verify possible using trap constraints in natural domain returned unsat :8 sat :27
Attempting to minimize the solution found.
Minimization took 2407 ms.
[2023-03-19 17:36:14] [INFO ] After 8633ms SMT Verify possible using all constraints in natural domain returned unsat :8 sat :27
Fused 35 Parikh solutions to 27 different solutions.
Parikh walk visited 4 properties in 1022 ms.
Support contains 27 out of 192 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 192/192 places, 434/434 transitions.
Graph (complete) has 734 edges and 192 vertex of which 191 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.2 ms
Discarding 1 places :
Also discarding 0 output transitions
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 3 place count 191 transition count 432
Discarding 14 places :
Symmetric choice reduction at 1 with 14 rule applications. Total rules 17 place count 177 transition count 373
Iterating global reduction 1 with 14 rules applied. Total rules applied 31 place count 177 transition count 373
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 47 place count 177 transition count 357
Discarding 10 places :
Symmetric choice reduction at 2 with 10 rule applications. Total rules 57 place count 167 transition count 347
Iterating global reduction 2 with 10 rules applied. Total rules applied 67 place count 167 transition count 347
Ensure Unique test removed 20 transitions
Reduce isomorphic transitions removed 20 transitions.
Iterating post reduction 2 with 20 rules applied. Total rules applied 87 place count 167 transition count 327
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 91 place count 163 transition count 322
Iterating global reduction 3 with 4 rules applied. Total rules applied 95 place count 163 transition count 322
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 3 with 3 rules applied. Total rules applied 98 place count 163 transition count 319
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 99 place count 162 transition count 318
Iterating global reduction 4 with 1 rules applied. Total rules applied 100 place count 162 transition count 318
Applied a total of 100 rules in 66 ms. Remains 162 /192 variables (removed 30) and now considering 318/434 (removed 116) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 67 ms. Remains : 162/192 places, 318/434 transitions.
Incomplete random walk after 10000 steps, including 2241 resets, run finished after 161 ms. (steps per millisecond=62 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 49 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1000 steps, including 51 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 44 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 50 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 48 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 52 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 56 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1000 steps, including 106 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1000 steps, including 53 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1000 steps, including 44 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 43 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 44 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1000 steps, including 102 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1000 steps, including 95 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 44 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1000 steps, including 41 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1000 steps, including 54 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 56 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 43 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1000 steps, including 38 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1000 steps, including 109 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 50 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 44 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 23) seen :0
Interrupted probabilistic random walk after 402007 steps, run timeout after 3001 ms. (steps per millisecond=133 ) properties seen :{4=1, 21=1}
Probabilistic random walk after 402007 steps, saw 184769 distinct states, run finished after 3001 ms. (steps per millisecond=133 ) properties seen :2
Running SMT prover for 21 properties.
// Phase 1: matrix 318 rows 162 cols
[2023-03-19 17:36:19] [INFO ] Computed 4 place invariants in 5 ms
[2023-03-19 17:36:19] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:19] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 11 ms returned sat
[2023-03-19 17:36:19] [INFO ] After 231ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:21
[2023-03-19 17:36:19] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 17:36:19] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 3 ms returned sat
[2023-03-19 17:36:20] [INFO ] After 691ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :21
[2023-03-19 17:36:20] [INFO ] State equation strengthened by 207 read => feed constraints.
[2023-03-19 17:36:21] [INFO ] After 1493ms SMT Verify possible using 207 Read/Feed constraints in natural domain returned unsat :0 sat :21
[2023-03-19 17:36:22] [INFO ] Deduced a trap composed of 21 places in 30 ms of which 1 ms to minimize.
[2023-03-19 17:36:22] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 55 ms
[2023-03-19 17:36:23] [INFO ] Deduced a trap composed of 54 places in 31 ms of which 1 ms to minimize.
[2023-03-19 17:36:23] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 93 ms
[2023-03-19 17:36:24] [INFO ] After 3700ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :21
Attempting to minimize the solution found.
Minimization took 1836 ms.
[2023-03-19 17:36:26] [INFO ] After 6396ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :21
Parikh walk visited 2 properties in 1093 ms.
Support contains 23 out of 162 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 162/162 places, 318/318 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 158 transition count 293
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 158 transition count 293
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 12 place count 154 transition count 289
Iterating global reduction 0 with 4 rules applied. Total rules applied 16 place count 154 transition count 289
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 19 place count 154 transition count 286
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 23 place count 150 transition count 281
Iterating global reduction 1 with 4 rules applied. Total rules applied 27 place count 150 transition count 281
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 29 place count 150 transition count 279
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 30 place count 149 transition count 278
Iterating global reduction 2 with 1 rules applied. Total rules applied 31 place count 149 transition count 278
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 32 place count 148 transition count 277
Iterating global reduction 2 with 1 rules applied. Total rules applied 33 place count 148 transition count 277
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 34 place count 147 transition count 276
Iterating global reduction 2 with 1 rules applied. Total rules applied 35 place count 147 transition count 276
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 36 place count 146 transition count 275
Iterating global reduction 2 with 1 rules applied. Total rules applied 37 place count 146 transition count 275
Applied a total of 37 rules in 38 ms. Remains 146 /162 variables (removed 16) and now considering 275/318 (removed 43) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 38 ms. Remains : 146/162 places, 275/318 transitions.
Incomplete random walk after 10000 steps, including 2177 resets, run finished after 167 ms. (steps per millisecond=59 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 51 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 41 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 61 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 44 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 46 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 93 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 44 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 45 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 55 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 53 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1000 steps, including 102 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 95 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 37 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 45 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 47 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 41 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1000 steps, including 51 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 39 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1000 steps, including 51 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 19) seen :0
Interrupted probabilistic random walk after 399533 steps, run timeout after 3001 ms. (steps per millisecond=133 ) properties seen :{}
Probabilistic random walk after 399533 steps, saw 178589 distinct states, run finished after 3001 ms. (steps per millisecond=133 ) properties seen :0
Running SMT prover for 19 properties.
// Phase 1: matrix 275 rows 146 cols
[2023-03-19 17:36:30] [INFO ] Computed 4 place invariants in 10 ms
[2023-03-19 17:36:30] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:30] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:30] [INFO ] After 261ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:19
[2023-03-19 17:36:30] [INFO ] [Nat]Absence check using 2 positive place invariants in 0 ms returned sat
[2023-03-19 17:36:30] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 3 ms returned sat
[2023-03-19 17:36:31] [INFO ] After 447ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :19
[2023-03-19 17:36:31] [INFO ] State equation strengthened by 177 read => feed constraints.
[2023-03-19 17:36:33] [INFO ] After 1841ms SMT Verify possible using 177 Read/Feed constraints in natural domain returned unsat :0 sat :19
[2023-03-19 17:36:33] [INFO ] Deduced a trap composed of 21 places in 36 ms of which 1 ms to minimize.
[2023-03-19 17:36:33] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 57 ms
[2023-03-19 17:36:35] [INFO ] Deduced a trap composed of 45 places in 47 ms of which 0 ms to minimize.
[2023-03-19 17:36:35] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 136 ms
[2023-03-19 17:36:35] [INFO ] After 4181ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :19
Attempting to minimize the solution found.
Minimization took 1296 ms.
[2023-03-19 17:36:36] [INFO ] After 6030ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :19
Parikh walk visited 0 properties in 867 ms.
Support contains 23 out of 146 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 146/146 places, 275/275 transitions.
Applied a total of 0 rules in 21 ms. Remains 146 /146 variables (removed 0) and now considering 275/275 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 21 ms. Remains : 146/146 places, 275/275 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 146/146 places, 275/275 transitions.
Applied a total of 0 rules in 8 ms. Remains 146 /146 variables (removed 0) and now considering 275/275 (removed 0) transitions.
[2023-03-19 17:36:37] [INFO ] Invariant cache hit.
[2023-03-19 17:36:37] [INFO ] Implicit Places using invariants in 63 ms returned []
[2023-03-19 17:36:37] [INFO ] Invariant cache hit.
[2023-03-19 17:36:37] [INFO ] State equation strengthened by 177 read => feed constraints.
[2023-03-19 17:36:38] [INFO ] Implicit Places using invariants and state equation in 380 ms returned []
Implicit Place search using SMT with State Equation took 459 ms to find 0 implicit places.
[2023-03-19 17:36:38] [INFO ] Redundant transitions in 16 ms returned []
[2023-03-19 17:36:38] [INFO ] Invariant cache hit.
[2023-03-19 17:36:38] [INFO ] Dead Transitions using invariants and state equation in 91 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 584 ms. Remains : 146/146 places, 275/275 transitions.
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 0 with 5 rules applied. Total rules applied 5 place count 146 transition count 270
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 9 place count 142 transition count 270
Performed 14 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 14 Pre rules applied. Total rules applied 9 place count 142 transition count 256
Deduced a syphon composed of 14 places in 0 ms
Reduce places removed 14 places and 0 transitions.
Iterating global reduction 2 with 28 rules applied. Total rules applied 37 place count 128 transition count 256
Performed 14 Post agglomeration using F-continuation condition.Transition count delta: 14
Deduced a syphon composed of 14 places in 1 ms
Reduce places removed 14 places and 0 transitions.
Iterating global reduction 2 with 28 rules applied. Total rules applied 65 place count 114 transition count 242
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 66 place count 114 transition count 241
Applied a total of 66 rules in 25 ms. Remains 114 /146 variables (removed 32) and now considering 241/275 (removed 34) transitions.
Running SMT prover for 19 properties.
// Phase 1: matrix 241 rows 114 cols
[2023-03-19 17:36:38] [INFO ] Computed 4 place invariants in 2 ms
[2023-03-19 17:36:38] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:38] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 0 ms returned sat
[2023-03-19 17:36:38] [INFO ] After 139ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:19
[2023-03-19 17:36:38] [INFO ] [Nat]Absence check using 2 positive place invariants in 0 ms returned sat
[2023-03-19 17:36:38] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:38] [INFO ] After 369ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :19
[2023-03-19 17:36:39] [INFO ] Deduced a trap composed of 13 places in 49 ms of which 1 ms to minimize.
[2023-03-19 17:36:39] [INFO ] Deduced a trap composed of 33 places in 45 ms of which 2 ms to minimize.
[2023-03-19 17:36:39] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 138 ms
[2023-03-19 17:36:39] [INFO ] After 1303ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :19
Attempting to minimize the solution found.
Minimization took 430 ms.
[2023-03-19 17:36:40] [INFO ] After 1804ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :19
Successfully simplified 8 atomic propositions for a total of 16 simplifications.
[2023-03-19 17:36:40] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-19 17:36:40] [INFO ] Flatten gal took : 27 ms
FORMULA SieveSingleMsgMbox-PT-d1m64-CTLFireability-02 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-19 17:36:40] [INFO ] Flatten gal took : 24 ms
[2023-03-19 17:36:40] [INFO ] Input system was already deterministic with 434 transitions.
Support contains 46 out of 192 places (down from 53) after GAL structural reductions.
Computed a total of 51 stabilizing places and 91 stable transitions
Graph (complete) has 805 edges and 192 vertex of which 191 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.9 ms
Starting structural reductions in LTL mode, iteration 0 : 192/192 places, 434/434 transitions.
Discarding 31 places :
Symmetric choice reduction at 0 with 31 rule applications. Total rules 31 place count 161 transition count 267
Iterating global reduction 0 with 31 rules applied. Total rules applied 62 place count 161 transition count 267
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 0 with 9 rules applied. Total rules applied 71 place count 161 transition count 258
Discarding 26 places :
Symmetric choice reduction at 1 with 26 rule applications. Total rules 97 place count 135 transition count 232
Iterating global reduction 1 with 26 rules applied. Total rules applied 123 place count 135 transition count 232
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Iterating post reduction 1 with 18 rules applied. Total rules applied 141 place count 135 transition count 214
Discarding 13 places :
Symmetric choice reduction at 2 with 13 rule applications. Total rules 154 place count 122 transition count 198
Iterating global reduction 2 with 13 rules applied. Total rules applied 167 place count 122 transition count 198
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Iterating post reduction 2 with 18 rules applied. Total rules applied 185 place count 122 transition count 180
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 189 place count 118 transition count 176
Iterating global reduction 3 with 4 rules applied. Total rules applied 193 place count 118 transition count 176
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 196 place count 115 transition count 173
Iterating global reduction 3 with 3 rules applied. Total rules applied 199 place count 115 transition count 173
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 201 place count 113 transition count 170
Iterating global reduction 3 with 2 rules applied. Total rules applied 203 place count 113 transition count 170
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 205 place count 111 transition count 168
Iterating global reduction 3 with 2 rules applied. Total rules applied 207 place count 111 transition count 168
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 208 place count 110 transition count 167
Iterating global reduction 3 with 1 rules applied. Total rules applied 209 place count 110 transition count 167
Applied a total of 209 rules in 26 ms. Remains 110 /192 variables (removed 82) and now considering 167/434 (removed 267) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 27 ms. Remains : 110/192 places, 167/434 transitions.
[2023-03-19 17:36:40] [INFO ] Flatten gal took : 9 ms
[2023-03-19 17:36:40] [INFO ] Flatten gal took : 10 ms
[2023-03-19 17:36:40] [INFO ] Input system was already deterministic with 167 transitions.
Starting structural reductions in LTL mode, iteration 0 : 192/192 places, 434/434 transitions.
Discarding 32 places :
Symmetric choice reduction at 0 with 32 rule applications. Total rules 32 place count 160 transition count 254
Iterating global reduction 0 with 32 rules applied. Total rules applied 64 place count 160 transition count 254
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 0 with 8 rules applied. Total rules applied 72 place count 160 transition count 246
Discarding 26 places :
Symmetric choice reduction at 1 with 26 rule applications. Total rules 98 place count 134 transition count 220
Iterating global reduction 1 with 26 rules applied. Total rules applied 124 place count 134 transition count 220
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Iterating post reduction 1 with 18 rules applied. Total rules applied 142 place count 134 transition count 202
Discarding 14 places :
Symmetric choice reduction at 2 with 14 rule applications. Total rules 156 place count 120 transition count 185
Iterating global reduction 2 with 14 rules applied. Total rules applied 170 place count 120 transition count 185
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 2 with 15 rules applied. Total rules applied 185 place count 120 transition count 170
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 189 place count 116 transition count 166
Iterating global reduction 3 with 4 rules applied. Total rules applied 193 place count 116 transition count 166
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 196 place count 113 transition count 163
Iterating global reduction 3 with 3 rules applied. Total rules applied 199 place count 113 transition count 163
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 200 place count 112 transition count 162
Iterating global reduction 3 with 1 rules applied. Total rules applied 201 place count 112 transition count 162
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 202 place count 111 transition count 161
Iterating global reduction 3 with 1 rules applied. Total rules applied 203 place count 111 transition count 161
Applied a total of 203 rules in 38 ms. Remains 111 /192 variables (removed 81) and now considering 161/434 (removed 273) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 51 ms. Remains : 111/192 places, 161/434 transitions.
[2023-03-19 17:36:40] [INFO ] Flatten gal took : 8 ms
[2023-03-19 17:36:40] [INFO ] Flatten gal took : 10 ms
[2023-03-19 17:36:40] [INFO ] Input system was already deterministic with 161 transitions.
Starting structural reductions in LTL mode, iteration 0 : 192/192 places, 434/434 transitions.
Discarding 31 places :
Symmetric choice reduction at 0 with 31 rule applications. Total rules 31 place count 161 transition count 229
Iterating global reduction 0 with 31 rules applied. Total rules applied 62 place count 161 transition count 229
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 0 with 7 rules applied. Total rules applied 69 place count 161 transition count 222
Discarding 25 places :
Symmetric choice reduction at 1 with 25 rule applications. Total rules 94 place count 136 transition count 197
Iterating global reduction 1 with 25 rules applied. Total rules applied 119 place count 136 transition count 197
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 1 with 15 rules applied. Total rules applied 134 place count 136 transition count 182
Discarding 13 places :
Symmetric choice reduction at 2 with 13 rule applications. Total rules 147 place count 123 transition count 167
Iterating global reduction 2 with 13 rules applied. Total rules applied 160 place count 123 transition count 167
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 2 with 10 rules applied. Total rules applied 170 place count 123 transition count 157
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 173 place count 120 transition count 154
Iterating global reduction 3 with 3 rules applied. Total rules applied 176 place count 120 transition count 154
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 178 place count 118 transition count 152
Iterating global reduction 3 with 2 rules applied. Total rules applied 180 place count 118 transition count 152
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 181 place count 117 transition count 151
Iterating global reduction 3 with 1 rules applied. Total rules applied 182 place count 117 transition count 151
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 183 place count 116 transition count 150
Iterating global reduction 3 with 1 rules applied. Total rules applied 184 place count 116 transition count 150
Applied a total of 184 rules in 33 ms. Remains 116 /192 variables (removed 76) and now considering 150/434 (removed 284) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 34 ms. Remains : 116/192 places, 150/434 transitions.
[2023-03-19 17:36:40] [INFO ] Flatten gal took : 19 ms
[2023-03-19 17:36:40] [INFO ] Flatten gal took : 8 ms
[2023-03-19 17:36:40] [INFO ] Input system was already deterministic with 150 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 192/192 places, 434/434 transitions.
Discarding 30 places :
Symmetric choice reduction at 0 with 30 rule applications. Total rules 30 place count 162 transition count 268
Iterating global reduction 0 with 30 rules applied. Total rules applied 60 place count 162 transition count 268
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 0 with 9 rules applied. Total rules applied 69 place count 162 transition count 259
Discarding 25 places :
Symmetric choice reduction at 1 with 25 rule applications. Total rules 94 place count 137 transition count 234
Iterating global reduction 1 with 25 rules applied. Total rules applied 119 place count 137 transition count 234
Ensure Unique test removed 17 transitions
Reduce isomorphic transitions removed 17 transitions.
Iterating post reduction 1 with 17 rules applied. Total rules applied 136 place count 137 transition count 217
Discarding 13 places :
Symmetric choice reduction at 2 with 13 rule applications. Total rules 149 place count 124 transition count 202
Iterating global reduction 2 with 13 rules applied. Total rules applied 162 place count 124 transition count 202
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Iterating post reduction 2 with 18 rules applied. Total rules applied 180 place count 124 transition count 184
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 183 place count 121 transition count 181
Iterating global reduction 3 with 3 rules applied. Total rules applied 186 place count 121 transition count 181
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 188 place count 119 transition count 179
Iterating global reduction 3 with 2 rules applied. Total rules applied 190 place count 119 transition count 179
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 192 place count 117 transition count 176
Iterating global reduction 3 with 2 rules applied. Total rules applied 194 place count 117 transition count 176
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 196 place count 115 transition count 174
Iterating global reduction 3 with 2 rules applied. Total rules applied 198 place count 115 transition count 174
Applied a total of 198 rules in 78 ms. Remains 115 /192 variables (removed 77) and now considering 174/434 (removed 260) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 78 ms. Remains : 115/192 places, 174/434 transitions.
[2023-03-19 17:36:40] [INFO ] Flatten gal took : 5 ms
[2023-03-19 17:36:40] [INFO ] Flatten gal took : 5 ms
[2023-03-19 17:36:40] [INFO ] Input system was already deterministic with 174 transitions.
Starting structural reductions in LTL mode, iteration 0 : 192/192 places, 434/434 transitions.
Discarding 36 places :
Symmetric choice reduction at 0 with 36 rule applications. Total rules 36 place count 156 transition count 211
Iterating global reduction 0 with 36 rules applied. Total rules applied 72 place count 156 transition count 211
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 77 place count 156 transition count 206
Discarding 31 places :
Symmetric choice reduction at 1 with 31 rule applications. Total rules 108 place count 125 transition count 175
Iterating global reduction 1 with 31 rules applied. Total rules applied 139 place count 125 transition count 175
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 155 place count 125 transition count 159
Discarding 18 places :
Symmetric choice reduction at 2 with 18 rule applications. Total rules 173 place count 107 transition count 138
Iterating global reduction 2 with 18 rules applied. Total rules applied 191 place count 107 transition count 138
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 2 with 13 rules applied. Total rules applied 204 place count 107 transition count 125
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 210 place count 101 transition count 119
Iterating global reduction 3 with 6 rules applied. Total rules applied 216 place count 101 transition count 119
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 221 place count 96 transition count 114
Iterating global reduction 3 with 5 rules applied. Total rules applied 226 place count 96 transition count 114
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 230 place count 92 transition count 109
Iterating global reduction 3 with 4 rules applied. Total rules applied 234 place count 92 transition count 109
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 236 place count 92 transition count 107
Discarding 4 places :
Symmetric choice reduction at 4 with 4 rule applications. Total rules 240 place count 88 transition count 103
Iterating global reduction 4 with 4 rules applied. Total rules applied 244 place count 88 transition count 103
Discarding 2 places :
Symmetric choice reduction at 4 with 2 rule applications. Total rules 246 place count 86 transition count 100
Iterating global reduction 4 with 2 rules applied. Total rules applied 248 place count 86 transition count 100
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 249 place count 85 transition count 99
Iterating global reduction 4 with 1 rules applied. Total rules applied 250 place count 85 transition count 99
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 251 place count 84 transition count 98
Iterating global reduction 4 with 1 rules applied. Total rules applied 252 place count 84 transition count 98
Applied a total of 252 rules in 37 ms. Remains 84 /192 variables (removed 108) and now considering 98/434 (removed 336) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 37 ms. Remains : 84/192 places, 98/434 transitions.
[2023-03-19 17:36:40] [INFO ] Flatten gal took : 4 ms
[2023-03-19 17:36:40] [INFO ] Flatten gal took : 5 ms
[2023-03-19 17:36:40] [INFO ] Input system was already deterministic with 98 transitions.
Starting structural reductions in LTL mode, iteration 0 : 192/192 places, 434/434 transitions.
Discarding 36 places :
Symmetric choice reduction at 0 with 36 rule applications. Total rules 36 place count 156 transition count 211
Iterating global reduction 0 with 36 rules applied. Total rules applied 72 place count 156 transition count 211
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 77 place count 156 transition count 206
Discarding 31 places :
Symmetric choice reduction at 1 with 31 rule applications. Total rules 108 place count 125 transition count 175
Iterating global reduction 1 with 31 rules applied. Total rules applied 139 place count 125 transition count 175
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 155 place count 125 transition count 159
Discarding 18 places :
Symmetric choice reduction at 2 with 18 rule applications. Total rules 173 place count 107 transition count 138
Iterating global reduction 2 with 18 rules applied. Total rules applied 191 place count 107 transition count 138
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 2 with 13 rules applied. Total rules applied 204 place count 107 transition count 125
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 210 place count 101 transition count 119
Iterating global reduction 3 with 6 rules applied. Total rules applied 216 place count 101 transition count 119
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 221 place count 96 transition count 114
Iterating global reduction 3 with 5 rules applied. Total rules applied 226 place count 96 transition count 114
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 230 place count 92 transition count 109
Iterating global reduction 3 with 4 rules applied. Total rules applied 234 place count 92 transition count 109
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 236 place count 92 transition count 107
Discarding 3 places :
Symmetric choice reduction at 4 with 3 rule applications. Total rules 239 place count 89 transition count 104
Iterating global reduction 4 with 3 rules applied. Total rules applied 242 place count 89 transition count 104
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 243 place count 88 transition count 103
Iterating global reduction 4 with 1 rules applied. Total rules applied 244 place count 88 transition count 103
Applied a total of 244 rules in 32 ms. Remains 88 /192 variables (removed 104) and now considering 103/434 (removed 331) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 32 ms. Remains : 88/192 places, 103/434 transitions.
[2023-03-19 17:36:40] [INFO ] Flatten gal took : 17 ms
[2023-03-19 17:36:40] [INFO ] Flatten gal took : 4 ms
[2023-03-19 17:36:40] [INFO ] Input system was already deterministic with 103 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 192/192 places, 434/434 transitions.
Discarding 35 places :
Symmetric choice reduction at 0 with 35 rule applications. Total rules 35 place count 157 transition count 200
Iterating global reduction 0 with 35 rules applied. Total rules applied 70 place count 157 transition count 200
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 72 place count 157 transition count 198
Discarding 32 places :
Symmetric choice reduction at 1 with 32 rule applications. Total rules 104 place count 125 transition count 166
Iterating global reduction 1 with 32 rules applied. Total rules applied 136 place count 125 transition count 166
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 152 place count 125 transition count 150
Discarding 19 places :
Symmetric choice reduction at 2 with 19 rule applications. Total rules 171 place count 106 transition count 128
Iterating global reduction 2 with 19 rules applied. Total rules applied 190 place count 106 transition count 128
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 2 with 12 rules applied. Total rules applied 202 place count 106 transition count 116
Discarding 7 places :
Symmetric choice reduction at 3 with 7 rule applications. Total rules 209 place count 99 transition count 109
Iterating global reduction 3 with 7 rules applied. Total rules applied 216 place count 99 transition count 109
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 222 place count 93 transition count 103
Iterating global reduction 3 with 6 rules applied. Total rules applied 228 place count 93 transition count 103
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 233 place count 88 transition count 97
Iterating global reduction 3 with 5 rules applied. Total rules applied 238 place count 88 transition count 97
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 240 place count 88 transition count 95
Discarding 5 places :
Symmetric choice reduction at 4 with 5 rule applications. Total rules 245 place count 83 transition count 90
Iterating global reduction 4 with 5 rules applied. Total rules applied 250 place count 83 transition count 90
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 251 place count 82 transition count 88
Iterating global reduction 4 with 1 rules applied. Total rules applied 252 place count 82 transition count 88
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 253 place count 81 transition count 87
Iterating global reduction 4 with 1 rules applied. Total rules applied 254 place count 81 transition count 87
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 255 place count 80 transition count 86
Iterating global reduction 4 with 1 rules applied. Total rules applied 256 place count 80 transition count 86
Applied a total of 256 rules in 51 ms. Remains 80 /192 variables (removed 112) and now considering 86/434 (removed 348) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 51 ms. Remains : 80/192 places, 86/434 transitions.
[2023-03-19 17:36:41] [INFO ] Flatten gal took : 3 ms
[2023-03-19 17:36:41] [INFO ] Flatten gal took : 16 ms
[2023-03-19 17:36:41] [INFO ] Input system was already deterministic with 86 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 192/192 places, 434/434 transitions.
Discarding 35 places :
Symmetric choice reduction at 0 with 35 rule applications. Total rules 35 place count 157 transition count 224
Iterating global reduction 0 with 35 rules applied. Total rules applied 70 place count 157 transition count 224
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 0 with 6 rules applied. Total rules applied 76 place count 157 transition count 218
Discarding 30 places :
Symmetric choice reduction at 1 with 30 rule applications. Total rules 106 place count 127 transition count 188
Iterating global reduction 1 with 30 rules applied. Total rules applied 136 place count 127 transition count 188
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 152 place count 127 transition count 172
Discarding 17 places :
Symmetric choice reduction at 2 with 17 rule applications. Total rules 169 place count 110 transition count 152
Iterating global reduction 2 with 17 rules applied. Total rules applied 186 place count 110 transition count 152
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 2 with 14 rules applied. Total rules applied 200 place count 110 transition count 138
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 205 place count 105 transition count 133
Iterating global reduction 3 with 5 rules applied. Total rules applied 210 place count 105 transition count 133
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 214 place count 101 transition count 129
Iterating global reduction 3 with 4 rules applied. Total rules applied 218 place count 101 transition count 129
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 221 place count 98 transition count 125
Iterating global reduction 3 with 3 rules applied. Total rules applied 224 place count 98 transition count 125
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 227 place count 95 transition count 122
Iterating global reduction 3 with 3 rules applied. Total rules applied 230 place count 95 transition count 122
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 232 place count 93 transition count 119
Iterating global reduction 3 with 2 rules applied. Total rules applied 234 place count 93 transition count 119
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 235 place count 92 transition count 118
Iterating global reduction 3 with 1 rules applied. Total rules applied 236 place count 92 transition count 118
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 237 place count 91 transition count 117
Iterating global reduction 3 with 1 rules applied. Total rules applied 238 place count 91 transition count 117
Applied a total of 238 rules in 39 ms. Remains 91 /192 variables (removed 101) and now considering 117/434 (removed 317) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 40 ms. Remains : 91/192 places, 117/434 transitions.
[2023-03-19 17:36:41] [INFO ] Flatten gal took : 3 ms
[2023-03-19 17:36:41] [INFO ] Flatten gal took : 7 ms
[2023-03-19 17:36:41] [INFO ] Input system was already deterministic with 117 transitions.
Starting structural reductions in LTL mode, iteration 0 : 192/192 places, 434/434 transitions.
Discarding 33 places :
Symmetric choice reduction at 0 with 33 rule applications. Total rules 33 place count 159 transition count 229
Iterating global reduction 0 with 33 rules applied. Total rules applied 66 place count 159 transition count 229
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 0 with 6 rules applied. Total rules applied 72 place count 159 transition count 223
Discarding 28 places :
Symmetric choice reduction at 1 with 28 rule applications. Total rules 100 place count 131 transition count 195
Iterating global reduction 1 with 28 rules applied. Total rules applied 128 place count 131 transition count 195
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Iterating post reduction 1 with 18 rules applied. Total rules applied 146 place count 131 transition count 177
Discarding 16 places :
Symmetric choice reduction at 2 with 16 rule applications. Total rules 162 place count 115 transition count 158
Iterating global reduction 2 with 16 rules applied. Total rules applied 178 place count 115 transition count 158
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 2 with 13 rules applied. Total rules applied 191 place count 115 transition count 145
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 196 place count 110 transition count 140
Iterating global reduction 3 with 5 rules applied. Total rules applied 201 place count 110 transition count 140
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 205 place count 106 transition count 136
Iterating global reduction 3 with 4 rules applied. Total rules applied 209 place count 106 transition count 136
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 211 place count 104 transition count 134
Iterating global reduction 3 with 2 rules applied. Total rules applied 213 place count 104 transition count 134
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 3 with 3 rules applied. Total rules applied 216 place count 104 transition count 131
Discarding 2 places :
Symmetric choice reduction at 4 with 2 rule applications. Total rules 218 place count 102 transition count 129
Iterating global reduction 4 with 2 rules applied. Total rules applied 220 place count 102 transition count 129
Applied a total of 220 rules in 29 ms. Remains 102 /192 variables (removed 90) and now considering 129/434 (removed 305) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 29 ms. Remains : 102/192 places, 129/434 transitions.
[2023-03-19 17:36:41] [INFO ] Flatten gal took : 3 ms
[2023-03-19 17:36:41] [INFO ] Flatten gal took : 4 ms
[2023-03-19 17:36:41] [INFO ] Input system was already deterministic with 129 transitions.
Starting structural reductions in LTL mode, iteration 0 : 192/192 places, 434/434 transitions.
Discarding 32 places :
Symmetric choice reduction at 0 with 32 rule applications. Total rules 32 place count 160 transition count 251
Iterating global reduction 0 with 32 rules applied. Total rules applied 64 place count 160 transition count 251
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 0 with 7 rules applied. Total rules applied 71 place count 160 transition count 244
Discarding 28 places :
Symmetric choice reduction at 1 with 28 rule applications. Total rules 99 place count 132 transition count 216
Iterating global reduction 1 with 28 rules applied. Total rules applied 127 place count 132 transition count 216
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 143 place count 132 transition count 200
Discarding 15 places :
Symmetric choice reduction at 2 with 15 rule applications. Total rules 158 place count 117 transition count 182
Iterating global reduction 2 with 15 rules applied. Total rules applied 173 place count 117 transition count 182
Ensure Unique test removed 17 transitions
Reduce isomorphic transitions removed 17 transitions.
Iterating post reduction 2 with 17 rules applied. Total rules applied 190 place count 117 transition count 165
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 194 place count 113 transition count 161
Iterating global reduction 3 with 4 rules applied. Total rules applied 198 place count 113 transition count 161
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 201 place count 110 transition count 158
Iterating global reduction 3 with 3 rules applied. Total rules applied 204 place count 110 transition count 158
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 207 place count 107 transition count 154
Iterating global reduction 3 with 3 rules applied. Total rules applied 210 place count 107 transition count 154
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 213 place count 104 transition count 151
Iterating global reduction 3 with 3 rules applied. Total rules applied 216 place count 104 transition count 151
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 218 place count 102 transition count 148
Iterating global reduction 3 with 2 rules applied. Total rules applied 220 place count 102 transition count 148
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 221 place count 101 transition count 147
Iterating global reduction 3 with 1 rules applied. Total rules applied 222 place count 101 transition count 147
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 223 place count 100 transition count 146
Iterating global reduction 3 with 1 rules applied. Total rules applied 224 place count 100 transition count 146
Applied a total of 224 rules in 18 ms. Remains 100 /192 variables (removed 92) and now considering 146/434 (removed 288) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 18 ms. Remains : 100/192 places, 146/434 transitions.
[2023-03-19 17:36:41] [INFO ] Flatten gal took : 4 ms
[2023-03-19 17:36:41] [INFO ] Flatten gal took : 4 ms
[2023-03-19 17:36:41] [INFO ] Input system was already deterministic with 146 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 192/192 places, 434/434 transitions.
Discarding 36 places :
Symmetric choice reduction at 0 with 36 rule applications. Total rules 36 place count 156 transition count 211
Iterating global reduction 0 with 36 rules applied. Total rules applied 72 place count 156 transition count 211
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 77 place count 156 transition count 206
Discarding 31 places :
Symmetric choice reduction at 1 with 31 rule applications. Total rules 108 place count 125 transition count 175
Iterating global reduction 1 with 31 rules applied. Total rules applied 139 place count 125 transition count 175
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 155 place count 125 transition count 159
Discarding 18 places :
Symmetric choice reduction at 2 with 18 rule applications. Total rules 173 place count 107 transition count 138
Iterating global reduction 2 with 18 rules applied. Total rules applied 191 place count 107 transition count 138
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 2 with 13 rules applied. Total rules applied 204 place count 107 transition count 125
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 210 place count 101 transition count 119
Iterating global reduction 3 with 6 rules applied. Total rules applied 216 place count 101 transition count 119
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 221 place count 96 transition count 114
Iterating global reduction 3 with 5 rules applied. Total rules applied 226 place count 96 transition count 114
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 230 place count 92 transition count 109
Iterating global reduction 3 with 4 rules applied. Total rules applied 234 place count 92 transition count 109
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 236 place count 92 transition count 107
Discarding 4 places :
Symmetric choice reduction at 4 with 4 rule applications. Total rules 240 place count 88 transition count 103
Iterating global reduction 4 with 4 rules applied. Total rules applied 244 place count 88 transition count 103
Discarding 2 places :
Symmetric choice reduction at 4 with 2 rule applications. Total rules 246 place count 86 transition count 100
Iterating global reduction 4 with 2 rules applied. Total rules applied 248 place count 86 transition count 100
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 249 place count 85 transition count 99
Iterating global reduction 4 with 1 rules applied. Total rules applied 250 place count 85 transition count 99
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 251 place count 84 transition count 98
Iterating global reduction 4 with 1 rules applied. Total rules applied 252 place count 84 transition count 98
Applied a total of 252 rules in 23 ms. Remains 84 /192 variables (removed 108) and now considering 98/434 (removed 336) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 23 ms. Remains : 84/192 places, 98/434 transitions.
[2023-03-19 17:36:41] [INFO ] Flatten gal took : 2 ms
[2023-03-19 17:36:41] [INFO ] Flatten gal took : 3 ms
[2023-03-19 17:36:41] [INFO ] Input system was already deterministic with 98 transitions.
Incomplete random walk after 10000 steps, including 2262 resets, run finished after 12 ms. (steps per millisecond=833 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 475 resets, run finished after 6 ms. (steps per millisecond=1666 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2639819 steps, run timeout after 3001 ms. (steps per millisecond=879 ) properties seen :{}
Probabilistic random walk after 2639819 steps, saw 1104412 distinct states, run finished after 3001 ms. (steps per millisecond=879 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 98 rows 84 cols
[2023-03-19 17:36:44] [INFO ] Computed 5 place invariants in 5 ms
[2023-03-19 17:36:44] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:44] [INFO ] [Real]Absence check using 2 positive and 3 generalized place invariants in 2 ms returned sat
[2023-03-19 17:36:44] [INFO ] After 94ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:44] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:44] [INFO ] [Nat]Absence check using 2 positive and 3 generalized place invariants in 2 ms returned sat
[2023-03-19 17:36:44] [INFO ] After 36ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:44] [INFO ] State equation strengthened by 44 read => feed constraints.
[2023-03-19 17:36:44] [INFO ] After 17ms SMT Verify possible using 44 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:44] [INFO ] After 32ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 18 ms.
[2023-03-19 17:36:44] [INFO ] After 125ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 40 ms.
Support contains 2 out of 84 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 84/84 places, 98/98 transitions.
Graph (complete) has 238 edges and 84 vertex of which 83 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.0 ms
Discarding 1 places :
Also discarding 0 output transitions
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 3 place count 83 transition count 96
Applied a total of 3 rules in 4 ms. Remains 83 /84 variables (removed 1) and now considering 96/98 (removed 2) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 5 ms. Remains : 83/84 places, 96/98 transitions.
Incomplete random walk after 1000000 steps, including 224105 resets, run finished after 1090 ms. (steps per millisecond=917 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 1000000 steps, including 47742 resets, run finished after 392 ms. (steps per millisecond=2551 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 3232594 steps, run timeout after 3001 ms. (steps per millisecond=1077 ) properties seen :{}
Probabilistic random walk after 3232594 steps, saw 1354996 distinct states, run finished after 3002 ms. (steps per millisecond=1076 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 96 rows 83 cols
[2023-03-19 17:36:49] [INFO ] Computed 4 place invariants in 2 ms
[2023-03-19 17:36:49] [INFO ] [Real]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 17:36:49] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:49] [INFO ] After 97ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:49] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:49] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:49] [INFO ] After 33ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:49] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-19 17:36:49] [INFO ] After 15ms SMT Verify possible using 42 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:49] [INFO ] After 28ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 13 ms.
[2023-03-19 17:36:49] [INFO ] After 105ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 28 ms.
Support contains 2 out of 83 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 83/83 places, 96/96 transitions.
Applied a total of 0 rules in 2 ms. Remains 83 /83 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 2 ms. Remains : 83/83 places, 96/96 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 83/83 places, 96/96 transitions.
Applied a total of 0 rules in 2 ms. Remains 83 /83 variables (removed 0) and now considering 96/96 (removed 0) transitions.
[2023-03-19 17:36:49] [INFO ] Invariant cache hit.
[2023-03-19 17:36:49] [INFO ] Implicit Places using invariants in 77 ms returned []
[2023-03-19 17:36:49] [INFO ] Invariant cache hit.
[2023-03-19 17:36:49] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-19 17:36:49] [INFO ] Implicit Places using invariants and state equation in 130 ms returned []
Implicit Place search using SMT with State Equation took 221 ms to find 0 implicit places.
[2023-03-19 17:36:49] [INFO ] Redundant transitions in 12 ms returned []
[2023-03-19 17:36:49] [INFO ] Invariant cache hit.
[2023-03-19 17:36:49] [INFO ] Dead Transitions using invariants and state equation in 46 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 301 ms. Remains : 83/83 places, 96/96 transitions.
Incomplete random walk after 100000 steps, including 22266 resets, run finished after 358 ms. (steps per millisecond=279 ) properties (out of 2) seen :1
Running SMT prover for 1 properties.
[2023-03-19 17:36:49] [INFO ] Invariant cache hit.
[2023-03-19 17:36:49] [INFO ] [Real]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 17:36:49] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:50] [INFO ] After 62ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 17:36:50] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-19 17:36:50] [INFO ] After 26ms SMT Verify possible using 42 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-19 17:36:50] [INFO ] After 36ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:50] [INFO ] After 142ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:50] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:50] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:50] [INFO ] After 24ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:50] [INFO ] After 13ms SMT Verify possible using 42 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:50] [INFO ] After 21ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 2 ms.
[2023-03-19 17:36:50] [INFO ] After 88ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Incomplete random walk after 1000000 steps, including 224170 resets, run finished after 1080 ms. (steps per millisecond=925 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 1000001 steps, including 47421 resets, run finished after 392 ms. (steps per millisecond=2551 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 3293113 steps, run timeout after 3001 ms. (steps per millisecond=1097 ) properties seen :{}
Probabilistic random walk after 3293113 steps, saw 1379716 distinct states, run finished after 3001 ms. (steps per millisecond=1097 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-19 17:36:54] [INFO ] Invariant cache hit.
[2023-03-19 17:36:54] [INFO ] [Real]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-19 17:36:54] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:54] [INFO ] After 93ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:54] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:54] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:54] [INFO ] After 35ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:54] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-19 17:36:54] [INFO ] After 17ms SMT Verify possible using 42 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:54] [INFO ] After 31ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 13 ms.
[2023-03-19 17:36:54] [INFO ] After 110ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 30 ms.
Support contains 2 out of 83 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 83/83 places, 96/96 transitions.
Applied a total of 0 rules in 5 ms. Remains 83 /83 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 6 ms. Remains : 83/83 places, 96/96 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 83/83 places, 96/96 transitions.
Applied a total of 0 rules in 2 ms. Remains 83 /83 variables (removed 0) and now considering 96/96 (removed 0) transitions.
[2023-03-19 17:36:54] [INFO ] Invariant cache hit.
[2023-03-19 17:36:54] [INFO ] Implicit Places using invariants in 48 ms returned []
[2023-03-19 17:36:54] [INFO ] Invariant cache hit.
[2023-03-19 17:36:54] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-19 17:36:55] [INFO ] Implicit Places using invariants and state equation in 95 ms returned []
Implicit Place search using SMT with State Equation took 145 ms to find 0 implicit places.
[2023-03-19 17:36:55] [INFO ] Redundant transitions in 0 ms returned []
[2023-03-19 17:36:55] [INFO ] Invariant cache hit.
[2023-03-19 17:36:55] [INFO ] Dead Transitions using invariants and state equation in 49 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 203 ms. Remains : 83/83 places, 96/96 transitions.
Incomplete random walk after 100000 steps, including 22348 resets, run finished after 103 ms. (steps per millisecond=970 ) properties (out of 2) seen :1
Running SMT prover for 1 properties.
[2023-03-19 17:36:55] [INFO ] Invariant cache hit.
[2023-03-19 17:36:55] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:55] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:55] [INFO ] After 32ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 17:36:55] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-19 17:36:55] [INFO ] After 15ms SMT Verify possible using 42 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-19 17:36:55] [INFO ] After 24ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:55] [INFO ] After 106ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:55] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:55] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:55] [INFO ] After 22ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:55] [INFO ] After 12ms SMT Verify possible using 42 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:55] [INFO ] After 21ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 2 ms.
[2023-03-19 17:36:55] [INFO ] After 80ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Finished random walk after 1 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=1 )
Incomplete random walk after 10000 steps, including 2274 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 1033 resets, run finished after 12 ms. (steps per millisecond=833 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 3110582 steps, run timeout after 3001 ms. (steps per millisecond=1036 ) properties seen :{}
Probabilistic random walk after 3110582 steps, saw 1303309 distinct states, run finished after 3001 ms. (steps per millisecond=1036 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-19 17:36:58] [INFO ] Invariant cache hit.
[2023-03-19 17:36:58] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:58] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:58] [INFO ] After 20ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 17:36:58] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-19 17:36:58] [INFO ] After 12ms SMT Verify possible using 42 Read/Feed constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:58] [INFO ] After 75ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:36:58] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:36:58] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:36:58] [INFO ] After 20ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:58] [INFO ] After 11ms SMT Verify possible using 42 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:36:58] [INFO ] After 19ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 4 ms.
[2023-03-19 17:36:58] [INFO ] After 81ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 0 ms.
Support contains 1 out of 83 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 83/83 places, 96/96 transitions.
Applied a total of 0 rules in 2 ms. Remains 83 /83 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 2 ms. Remains : 83/83 places, 96/96 transitions.
Incomplete random walk after 10000 steps, including 2247 resets, run finished after 12 ms. (steps per millisecond=833 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 982 resets, run finished after 7 ms. (steps per millisecond=1428 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 3198625 steps, run timeout after 3001 ms. (steps per millisecond=1065 ) properties seen :{}
Probabilistic random walk after 3198625 steps, saw 1340675 distinct states, run finished after 3001 ms. (steps per millisecond=1065 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-19 17:37:01] [INFO ] Invariant cache hit.
[2023-03-19 17:37:01] [INFO ] [Real]Absence check using 2 positive place invariants in 0 ms returned sat
[2023-03-19 17:37:01] [INFO ] [Real]Absence check using 2 positive and 2 generalized place invariants in 0 ms returned sat
[2023-03-19 17:37:01] [INFO ] After 20ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 17:37:01] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-19 17:37:01] [INFO ] After 11ms SMT Verify possible using 42 Read/Feed constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:37:01] [INFO ] After 54ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:37:01] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:37:01] [INFO ] [Nat]Absence check using 2 positive and 2 generalized place invariants in 1 ms returned sat
[2023-03-19 17:37:01] [INFO ] After 27ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:37:01] [INFO ] After 11ms SMT Verify possible using 42 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-19 17:37:01] [INFO ] After 17ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 4 ms.
[2023-03-19 17:37:01] [INFO ] After 71ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 1 ms.
Support contains 1 out of 83 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 83/83 places, 96/96 transitions.
Applied a total of 0 rules in 2 ms. Remains 83 /83 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 2 ms. Remains : 83/83 places, 96/96 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 83/83 places, 96/96 transitions.
Applied a total of 0 rules in 1 ms. Remains 83 /83 variables (removed 0) and now considering 96/96 (removed 0) transitions.
[2023-03-19 17:37:01] [INFO ] Invariant cache hit.
[2023-03-19 17:37:01] [INFO ] Implicit Places using invariants in 37 ms returned []
[2023-03-19 17:37:01] [INFO ] Invariant cache hit.
[2023-03-19 17:37:01] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-19 17:37:01] [INFO ] Implicit Places using invariants and state equation in 99 ms returned []
Implicit Place search using SMT with State Equation took 138 ms to find 0 implicit places.
[2023-03-19 17:37:01] [INFO ] Redundant transitions in 1 ms returned []
[2023-03-19 17:37:01] [INFO ] Invariant cache hit.
[2023-03-19 17:37:01] [INFO ] Dead Transitions using invariants and state equation in 41 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 199 ms. Remains : 83/83 places, 96/96 transitions.
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 0 with 7 rules applied. Total rules applied 7 place count 83 transition count 89
Reduce places removed 5 places and 0 transitions.
Iterating post reduction 1 with 5 rules applied. Total rules applied 12 place count 78 transition count 89
Performed 13 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 13 Pre rules applied. Total rules applied 12 place count 78 transition count 76
Deduced a syphon composed of 13 places in 0 ms
Reduce places removed 13 places and 0 transitions.
Iterating global reduction 2 with 26 rules applied. Total rules applied 38 place count 65 transition count 76
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 2 with 14 rules applied. Total rules applied 52 place count 58 transition count 69
Applied a total of 52 rules in 4 ms. Remains 58 /83 variables (removed 25) and now considering 69/96 (removed 27) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 69 rows 58 cols
[2023-03-19 17:37:01] [INFO ] Computed 5 place invariants in 1 ms
[2023-03-19 17:37:01] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-19 17:37:01] [INFO ] [Real]Absence check using 2 positive and 3 generalized place invariants in 1 ms returned sat
[2023-03-19 17:37:01] [INFO ] After 14ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-19 17:37:01] [INFO ] Deduced a trap composed of 32 places in 18 ms of which 0 ms to minimize.
[2023-03-19 17:37:01] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 23 ms
[2023-03-19 17:37:01] [INFO ] After 40ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:37:01] [INFO ] After 85ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:37:02] [INFO ] [Nat]Absence check using 2 positive place invariants in 0 ms returned sat
[2023-03-19 17:37:02] [INFO ] [Nat]Absence check using 2 positive and 3 generalized place invariants in 1 ms returned sat
[2023-03-19 17:37:02] [INFO ] After 14ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:37:02] [INFO ] Deduced a trap composed of 32 places in 17 ms of which 1 ms to minimize.
[2023-03-19 17:37:02] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 22 ms
[2023-03-19 17:37:02] [INFO ] After 38ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 2 ms.
[2023-03-19 17:37:02] [INFO ] After 60ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 0 with 6 rules applied. Total rules applied 6 place count 83 transition count 90
Reduce places removed 5 places and 0 transitions.
Iterating post reduction 1 with 5 rules applied. Total rules applied 11 place count 78 transition count 90
Performed 13 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 13 Pre rules applied. Total rules applied 11 place count 78 transition count 77
Deduced a syphon composed of 13 places in 1 ms
Reduce places removed 13 places and 0 transitions.
Iterating global reduction 2 with 26 rules applied. Total rules applied 37 place count 65 transition count 77
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Deduced a syphon composed of 7 places in 1 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 2 with 14 rules applied. Total rules applied 51 place count 58 transition count 70
Applied a total of 51 rules in 5 ms. Remains 58 /83 variables (removed 25) and now considering 70/96 (removed 26) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 70 rows 58 cols
[2023-03-19 17:37:02] [INFO ] Computed 4 place invariants in 2 ms
[2023-03-19 17:37:02] [INFO ] [Real]Absence check using 3 positive place invariants in 1 ms returned sat
[2023-03-19 17:37:02] [INFO ] [Real]Absence check using 3 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-19 17:37:02] [INFO ] After 44ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-19 17:37:02] [INFO ] [Nat]Absence check using 3 positive place invariants in 1 ms returned sat
[2023-03-19 17:37:02] [INFO ] [Nat]Absence check using 3 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-19 17:37:02] [INFO ] After 17ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-19 17:37:02] [INFO ] After 24ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 5 ms.
[2023-03-19 17:37:02] [INFO ] After 50ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Starting structural reductions in LTL mode, iteration 0 : 192/192 places, 434/434 transitions.
Discarding 28 places :
Symmetric choice reduction at 0 with 28 rule applications. Total rules 28 place count 164 transition count 255
Iterating global reduction 0 with 28 rules applied. Total rules applied 56 place count 164 transition count 255
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 0 with 7 rules applied. Total rules applied 63 place count 164 transition count 248
Discarding 23 places :
Symmetric choice reduction at 1 with 23 rule applications. Total rules 86 place count 141 transition count 225
Iterating global reduction 1 with 23 rules applied. Total rules applied 109 place count 141 transition count 225
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 125 place count 141 transition count 209
Discarding 11 places :
Symmetric choice reduction at 2 with 11 rule applications. Total rules 136 place count 130 transition count 192
Iterating global reduction 2 with 11 rules applied. Total rules applied 147 place count 130 transition count 192
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 2 with 7 rules applied. Total rules applied 154 place count 130 transition count 185
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 158 place count 126 transition count 181
Iterating global reduction 3 with 4 rules applied. Total rules applied 162 place count 126 transition count 181
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 165 place count 123 transition count 178
Iterating global reduction 3 with 3 rules applied. Total rules applied 168 place count 123 transition count 178
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 170 place count 121 transition count 175
Iterating global reduction 3 with 2 rules applied. Total rules applied 172 place count 121 transition count 175
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 174 place count 119 transition count 173
Iterating global reduction 3 with 2 rules applied. Total rules applied 176 place count 119 transition count 173
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 177 place count 118 transition count 172
Iterating global reduction 3 with 1 rules applied. Total rules applied 178 place count 118 transition count 172
Applied a total of 178 rules in 13 ms. Remains 118 /192 variables (removed 74) and now considering 172/434 (removed 262) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 13 ms. Remains : 118/192 places, 172/434 transitions.
[2023-03-19 17:37:02] [INFO ] Flatten gal took : 5 ms
[2023-03-19 17:37:02] [INFO ] Flatten gal took : 5 ms
[2023-03-19 17:37:02] [INFO ] Input system was already deterministic with 172 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 192/192 places, 434/434 transitions.
Discarding 35 places :
Symmetric choice reduction at 0 with 35 rule applications. Total rules 35 place count 157 transition count 215
Iterating global reduction 0 with 35 rules applied. Total rules applied 70 place count 157 transition count 215
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 75 place count 157 transition count 210
Discarding 30 places :
Symmetric choice reduction at 1 with 30 rule applications. Total rules 105 place count 127 transition count 180
Iterating global reduction 1 with 30 rules applied. Total rules applied 135 place count 127 transition count 180
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Iterating post reduction 1 with 18 rules applied. Total rules applied 153 place count 127 transition count 162
Discarding 17 places :
Symmetric choice reduction at 2 with 17 rule applications. Total rules 170 place count 110 transition count 142
Iterating global reduction 2 with 17 rules applied. Total rules applied 187 place count 110 transition count 142
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 2 with 12 rules applied. Total rules applied 199 place count 110 transition count 130
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 205 place count 104 transition count 124
Iterating global reduction 3 with 6 rules applied. Total rules applied 211 place count 104 transition count 124
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 216 place count 99 transition count 119
Iterating global reduction 3 with 5 rules applied. Total rules applied 221 place count 99 transition count 119
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 224 place count 96 transition count 115
Iterating global reduction 3 with 3 rules applied. Total rules applied 227 place count 96 transition count 115
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 229 place count 96 transition count 113
Discarding 3 places :
Symmetric choice reduction at 4 with 3 rule applications. Total rules 232 place count 93 transition count 110
Iterating global reduction 4 with 3 rules applied. Total rules applied 235 place count 93 transition count 110
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 236 place count 92 transition count 109
Iterating global reduction 4 with 1 rules applied. Total rules applied 237 place count 92 transition count 109
Applied a total of 237 rules in 16 ms. Remains 92 /192 variables (removed 100) and now considering 109/434 (removed 325) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 16 ms. Remains : 92/192 places, 109/434 transitions.
[2023-03-19 17:37:02] [INFO ] Flatten gal took : 4 ms
[2023-03-19 17:37:02] [INFO ] Flatten gal took : 3 ms
[2023-03-19 17:37:02] [INFO ] Input system was already deterministic with 109 transitions.
Incomplete random walk after 10000 steps, including 2234 resets, run finished after 12 ms. (steps per millisecond=833 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 459 resets, run finished after 6 ms. (steps per millisecond=1666 ) properties (out of 1) seen :0
Finished probabilistic random walk after 3856 steps, run visited all 1 properties in 7 ms. (steps per millisecond=550 )
Probabilistic random walk after 3856 steps, saw 1737 distinct states, run finished after 8 ms. (steps per millisecond=482 ) properties seen :1
FORMULA SieveSingleMsgMbox-PT-d1m64-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL PROBABILISTIC_WALK
Starting structural reductions in LTL mode, iteration 0 : 192/192 places, 434/434 transitions.
Discarding 36 places :
Symmetric choice reduction at 0 with 36 rule applications. Total rules 36 place count 156 transition count 202
Iterating global reduction 0 with 36 rules applied. Total rules applied 72 place count 156 transition count 202
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 76 place count 156 transition count 198
Discarding 31 places :
Symmetric choice reduction at 1 with 31 rule applications. Total rules 107 place count 125 transition count 167
Iterating global reduction 1 with 31 rules applied. Total rules applied 138 place count 125 transition count 167
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Iterating post reduction 1 with 18 rules applied. Total rules applied 156 place count 125 transition count 149
Discarding 18 places :
Symmetric choice reduction at 2 with 18 rule applications. Total rules 174 place count 107 transition count 128
Iterating global reduction 2 with 18 rules applied. Total rules applied 192 place count 107 transition count 128
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Iterating post reduction 2 with 11 rules applied. Total rules applied 203 place count 107 transition count 117
Discarding 7 places :
Symmetric choice reduction at 3 with 7 rule applications. Total rules 210 place count 100 transition count 110
Iterating global reduction 3 with 7 rules applied. Total rules applied 217 place count 100 transition count 110
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 223 place count 94 transition count 104
Iterating global reduction 3 with 6 rules applied. Total rules applied 229 place count 94 transition count 104
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 233 place count 90 transition count 99
Iterating global reduction 3 with 4 rules applied. Total rules applied 237 place count 90 transition count 99
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 239 place count 90 transition count 97
Discarding 4 places :
Symmetric choice reduction at 4 with 4 rule applications. Total rules 243 place count 86 transition count 93
Iterating global reduction 4 with 4 rules applied. Total rules applied 247 place count 86 transition count 93
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 248 place count 85 transition count 92
Iterating global reduction 4 with 1 rules applied. Total rules applied 249 place count 85 transition count 92
Applied a total of 249 rules in 7 ms. Remains 85 /192 variables (removed 107) and now considering 92/434 (removed 342) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 85/192 places, 92/434 transitions.
[2023-03-19 17:37:02] [INFO ] Flatten gal took : 3 ms
[2023-03-19 17:37:02] [INFO ] Flatten gal took : 3 ms
[2023-03-19 17:37:02] [INFO ] Input system was already deterministic with 92 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 192/192 places, 434/434 transitions.
Discarding 35 places :
Symmetric choice reduction at 0 with 35 rule applications. Total rules 35 place count 157 transition count 224
Iterating global reduction 0 with 35 rules applied. Total rules applied 70 place count 157 transition count 224
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 0 with 6 rules applied. Total rules applied 76 place count 157 transition count 218
Discarding 30 places :
Symmetric choice reduction at 1 with 30 rule applications. Total rules 106 place count 127 transition count 188
Iterating global reduction 1 with 30 rules applied. Total rules applied 136 place count 127 transition count 188
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 152 place count 127 transition count 172
Discarding 17 places :
Symmetric choice reduction at 2 with 17 rule applications. Total rules 169 place count 110 transition count 152
Iterating global reduction 2 with 17 rules applied. Total rules applied 186 place count 110 transition count 152
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 2 with 14 rules applied. Total rules applied 200 place count 110 transition count 138
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 205 place count 105 transition count 133
Iterating global reduction 3 with 5 rules applied. Total rules applied 210 place count 105 transition count 133
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 214 place count 101 transition count 129
Iterating global reduction 3 with 4 rules applied. Total rules applied 218 place count 101 transition count 129
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 221 place count 98 transition count 125
Iterating global reduction 3 with 3 rules applied. Total rules applied 224 place count 98 transition count 125
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 227 place count 95 transition count 122
Iterating global reduction 3 with 3 rules applied. Total rules applied 230 place count 95 transition count 122
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 232 place count 93 transition count 119
Iterating global reduction 3 with 2 rules applied. Total rules applied 234 place count 93 transition count 119
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 235 place count 92 transition count 118
Iterating global reduction 3 with 1 rules applied. Total rules applied 236 place count 92 transition count 118
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 237 place count 91 transition count 117
Iterating global reduction 3 with 1 rules applied. Total rules applied 238 place count 91 transition count 117
Applied a total of 238 rules in 19 ms. Remains 91 /192 variables (removed 101) and now considering 117/434 (removed 317) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 91/192 places, 117/434 transitions.
[2023-03-19 17:37:02] [INFO ] Flatten gal took : 5 ms
[2023-03-19 17:37:02] [INFO ] Flatten gal took : 4 ms
[2023-03-19 17:37:02] [INFO ] Input system was already deterministic with 117 transitions.
[2023-03-19 17:37:02] [INFO ] Flatten gal took : 10 ms
[2023-03-19 17:37:02] [INFO ] Flatten gal took : 15 ms
[2023-03-19 17:37:02] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-19 17:37:02] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 192 places, 434 transitions and 1718 arcs took 4 ms.
Total runtime 62150 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SieveSingleMsgMbox-PT-d1m64
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/378
CTLFireability

FORMULA SieveSingleMsgMbox-PT-d1m64-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d1m64-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d1m64-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d1m64-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d1m64-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d1m64-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d1m64-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d1m64-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d1m64-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393340 kB
MemFree: 13368080 kB
After kill :
MemTotal: 16393340 kB
MemFree: 16233360 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/378/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/378/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/378/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 7 (type EXCL) for 0 SieveSingleMsgMbox-PT-d1m64-CTLFireability-00
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 7 (type EXCL) for SieveSingleMsgMbox-PT-d1m64-CTLFireability-00
lola: result : false
lola: markings : 7
lola: fired transitions : 6
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 57 (type FNDP) for 42 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11
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lola: LAUNCH task # 58 (type EQUN) for 42 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
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lola: LAUNCH task # 63 (type SRCH) for 42 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 63 (type SRCH) for SieveSingleMsgMbox-PT-d1m64-CTLFireability-11
lola: result : unknown
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 64 (type FNDP) for 26 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/378/CTLFireability-58.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-00: DISJ 0 0 1 0 4 0 0 4
SieveSingleMsgMbox-PT-d1m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 CTL EXCL 5/240 5/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-00 741259 m, 148251 m/sec, 964004 t fired, .
57 EF FNDP 5/1800 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 713196 t fired, 98707 attempts, .
58 EF STEQ 5/1800 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 5/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 760437 t fired, 105264 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 CTL EXCL 10/240 11/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-00 1842528 m, 220253 m/sec, 2428037 t fired, .
57 EF FNDP 10/1795 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 1622490 t fired, 224867 attempts, .
58 EF STEQ 10/1795 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 10/3595 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 1675450 t fired, 232100 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 CTL EXCL 15/240 17/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-00 2979446 m, 227383 m/sec, 3939568 t fired, .
57 EF FNDP 15/1790 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 2560409 t fired, 354693 attempts, .
58 EF STEQ 15/1790 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 15/3590 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 2634125 t fired, 365125 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 CTL EXCL 20/240 23/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-00 4039154 m, 211941 m/sec, 5369320 t fired, .
57 EF FNDP 20/1785 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 3445863 t fired, 477073 attempts, .
58 EF STEQ 20/1785 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 20/3585 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 3538895 t fired, 490403 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 CTL EXCL 25/240 29/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-00 5113882 m, 214945 m/sec, 6780650 t fired, .
57 EF FNDP 25/1780 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 4344129 t fired, 601533 attempts, .
58 EF STEQ 25/1780 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 25/3580 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 4481550 t fired, 621081 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 EF FNDP 30/1775 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 5248314 t fired, 726656 attempts, .
58 EF STEQ 30/1775 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 30/3575 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 5414099 t fired, 750251 attempts, .

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lola: time limit : 255 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for SieveSingleMsgMbox-PT-d1m64-CTLFireability-14
lola: result : false
lola: markings : 1462
lola: fired transitions : 1805
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 46 (type EXCL) for 45 SieveSingleMsgMbox-PT-d1m64-CTLFireability-12
lola: time limit : 274 sec
lola: memory limit: 32 pages
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 5/274 3/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-12 551482 m, 110296 m/sec, 1254359 t fired, .
57 EF FNDP 35/1770 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 6154637 t fired, 852102 attempts, .
58 EF STEQ 35/1770 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 35/3570 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 6327340 t fired, 876657 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-00: DISJ 0 0 0 0 4 0 1 4
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 10/274 7/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-12 1136435 m, 116990 m/sec, 2606666 t fired, .
57 EF FNDP 40/1765 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 7087147 t fired, 981257 attempts, .
58 EF STEQ 40/1765 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 40/3565 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 7279505 t fired, 1008653 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-00: DISJ 0 0 0 0 4 0 1 4
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 15/274 10/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-12 1694064 m, 111525 m/sec, 3925722 t fired, .
57 EF FNDP 45/1760 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 7990477 t fired, 1106530 attempts, .
58 EF STEQ 45/1760 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 45/3560 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 8199204 t fired, 1135905 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-00: DISJ 0 0 0 0 4 0 1 4
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 20/274 13/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-12 2277168 m, 116620 m/sec, 5263544 t fired, .
57 EF FNDP 50/1755 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 8927478 t fired, 1236388 attempts, .
58 EF STEQ 50/1755 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 50/3555 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 9117579 t fired, 1262940 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 25/274 16/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-12 2836023 m, 111771 m/sec, 6575205 t fired, .
57 EF FNDP 55/1750 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 9840962 t fired, 1363173 attempts, .
58 EF STEQ 55/1750 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 55/3550 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 10033400 t fired, 1389351 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 30/274 19/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-12 3423595 m, 117514 m/sec, 7990229 t fired, .
57 EF FNDP 60/1745 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 10807773 t fired, 1497118 attempts, .
58 EF STEQ 60/1745 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 60/3545 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 10970996 t fired, 1519567 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-00: DISJ 0 0 0 0 4 0 1 4
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 35/274 23/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-12 4025824 m, 120445 m/sec, 9375552 t fired, .
57 EF FNDP 65/1740 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 11768198 t fired, 1629896 attempts, .
58 EF STEQ 65/1740 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 65/3540 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 11952959 t fired, 1655440 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-00: DISJ 0 0 0 0 4 0 1 4
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 40/274 26/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-12 4620217 m, 118878 m/sec, 10756165 t fired, .
57 EF FNDP 70/1735 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 12725501 t fired, 1762682 attempts, .
58 EF STEQ 70/1735 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 70/3535 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 12941287 t fired, 1791847 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-00: DISJ 0 0 0 0 4 0 1 4
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 45/274 29/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-12 5158857 m, 107728 m/sec, 11999431 t fired, .
57 EF FNDP 75/1730 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 13611366 t fired, 1885099 attempts, .
58 EF STEQ 75/1730 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 75/3530 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 13847015 t fired, 1917567 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-00: DISJ 0 0 0 0 4 0 1 4
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 50/274 32/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-12 5704719 m, 109172 m/sec, 13318795 t fired, .
57 EF FNDP 80/1725 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 14510423 t fired, 2009638 attempts, .
58 EF STEQ 80/1725 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 80/3525 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 14772102 t fired, 2045365 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 EF FNDP 85/1720 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 15469462 t fired, 2142455 attempts, .
58 EF STEQ 85/1720 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 85/3520 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 15717023 t fired, 2176165 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/292 7/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-10 1133201 m, 226640 m/sec, 1466172 t fired, .
57 EF FNDP 90/1715 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 16429801 t fired, 2275189 attempts, .
58 EF STEQ 90/1715 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 90/3515 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 16686479 t fired, 2310428 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-14: CTL false CTL model checker

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-00: DISJ 0 0 0 0 4 0 1 4
SieveSingleMsgMbox-PT-d1m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 10/292 13/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-10 2305814 m, 234522 m/sec, 3024416 t fired, .
57 EF FNDP 95/1710 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 17385950 t fired, 2407689 attempts, .
58 EF STEQ 95/1710 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 95/3510 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 17679782 t fired, 2447868 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m64-CTLFireability-00: DISJ 0 0 0 0 4 0 1 4
SieveSingleMsgMbox-PT-d1m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 15/292 20/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-10 3450155 m, 228868 m/sec, 4603356 t fired, .
57 EF FNDP 100/1705 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 18313754 t fired, 2535929 attempts, .
58 EF STEQ 100/1705 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 100/3505 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 18655543 t fired, 2582948 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m64-CTLFireability-00: DISJ 0 0 0 0 4 0 1 4
SieveSingleMsgMbox-PT-d1m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 20/292 26/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-10 4623485 m, 234666 m/sec, 6139986 t fired, .
57 EF FNDP 105/1700 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 19277450 t fired, 2669545 attempts, .
58 EF STEQ 105/1700 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 105/3500 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 19646328 t fired, 2719907 attempts, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m64-CTLFireability-00: DISJ 0 0 0 0 4 0 1 4
SieveSingleMsgMbox-PT-d1m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 25/292 32/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-10 5762310 m, 227765 m/sec, 7701120 t fired, .
57 EF FNDP 110/1695 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 20235987 t fired, 2802142 attempts, .
58 EF STEQ 110/1695 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 110/3495 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 20633442 t fired, 2856281 attempts, .

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lola: CANCELED task # 40 (type EXCL) for SieveSingleMsgMbox-PT-d1m64-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m64-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m64-CTLFireability-00: DISJ 0 0 0 0 4 0 1 4
SieveSingleMsgMbox-PT-d1m64-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 4 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 1 2 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 EF FNDP 115/1690 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 21194076 t fired, 2934908 attempts, .
58 EF STEQ 115/1690 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
64 EF FNDP 115/3490 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 21625597 t fired, 2993580 attempts, .

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lola: LAUNCH task # 37 (type EXCL) for 36 SieveSingleMsgMbox-PT-d1m64-CTLFireability-09
lola: time limit : 316 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for SieveSingleMsgMbox-PT-d1m64-CTLFireability-09
lola: result : false
lola: markings : 32
lola: fired transitions : 39
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 23 SieveSingleMsgMbox-PT-d1m64-CTLFireability-06
lola: time limit : 348 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for SieveSingleMsgMbox-PT-d1m64-CTLFireability-06
lola: result : true
lola: markings : 8
lola: fired transitions : 15
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 21 (type EXCL) for 20 SieveSingleMsgMbox-PT-d1m64-CTLFireability-05
lola: time limit : 387 sec
lola: memory limit: 32 pages
lola: FINISHED task # 21 (type EXCL) for SieveSingleMsgMbox-PT-d1m64-CTLFireability-05
lola: result : true
lola: markings : 1462
lola: fired transitions : 2749
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 15 (type EXCL) for 14 SieveSingleMsgMbox-PT-d1m64-CTLFireability-03
lola: time limit : 435 sec
lola: memory limit: 32 pages
lola: FINISHED task # 15 (type EXCL) for SieveSingleMsgMbox-PT-d1m64-CTLFireability-03
lola: result : false
lola: markings : 8
lola: fired transitions : 30
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 12 (type EXCL) for 11 SieveSingleMsgMbox-PT-d1m64-CTLFireability-01
lola: time limit : 497 sec
lola: memory limit: 32 pages
lola: FINISHED task # 12 (type EXCL) for SieveSingleMsgMbox-PT-d1m64-CTLFireability-01
lola: result : true
lola: markings : 8
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 66 (type EXCL) for 26 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07
lola: time limit : 580 sec
lola: memory limit: 32 pages
lola: FINISHED task # 66 (type EXCL) for SieveSingleMsgMbox-PT-d1m64-CTLFireability-07
lola: result : true
lola: markings : 109
lola: fired transitions : 108
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 64 (type FNDP) for SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 (obsolete)
lola: LAUNCH task # 59 (type EXCL) for 42 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11
lola: time limit : 697 sec
lola: memory limit: 32 pages
lola: FINISHED task # 64 (type FNDP) for SieveSingleMsgMbox-PT-d1m64-CTLFireability-07
lola: result : unknown
lola: fired transitions : 21631747
lola: tried executions : 2994423
lola: time used : 115.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SieveSingleMsgMbox-PT-d1m64-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-06: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m64-CTLFireability-00: DISJ 0 0 0 0 4 0 1 4
SieveSingleMsgMbox-PT-d1m64-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 1 0 0 4 0 0 2
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 0 3 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 EF FNDP 120/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 22268128 t fired, 3083610 attempts, .
58 EF STEQ 120/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
59 EF EXCL 5/697 5/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 1026795 m, 205359 m/sec, 1248615 t fired, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-06: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m64-CTLFireability-00: DISJ 0 0 0 0 4 0 1 4
SieveSingleMsgMbox-PT-d1m64-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 1 0 0 4 0 0 2
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 0 3 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 EF FNDP 125/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 23346714 t fired, 3232504 attempts, .
58 EF STEQ 125/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
59 EF EXCL 10/697 10/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 2018983 m, 198437 m/sec, 2463707 t fired, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-06: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m64-CTLFireability-00: DISJ 0 0 0 0 4 0 1 4
SieveSingleMsgMbox-PT-d1m64-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 1 0 0 4 0 0 2
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 0 3 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 EF FNDP 130/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 24336665 t fired, 3369353 attempts, .
58 EF STEQ 130/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
59 EF EXCL 15/697 15/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 2956895 m, 187582 m/sec, 3625982 t fired, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-06: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m64-CTLFireability-00: DISJ 0 0 0 0 4 0 1 4
SieveSingleMsgMbox-PT-d1m64-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 1 0 0 4 0 0 2
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 0 3 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 EF FNDP 135/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 25374774 t fired, 3512900 attempts, .
58 EF STEQ 135/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
59 EF EXCL 20/697 19/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 3855112 m, 179643 m/sec, 4725973 t fired, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-05: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-06: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SieveSingleMsgMbox-PT-d1m64-CTLFireability-00: DISJ 0 0 0 0 4 0 1 4
SieveSingleMsgMbox-PT-d1m64-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-07: DISJ 0 1 0 0 4 0 0 2
SieveSingleMsgMbox-PT-d1m64-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-11: EF 0 0 3 0 2 0 0 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d1m64-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 EF FNDP 140/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 26419624 t fired, 3657357 attempts, .
58 EF STEQ 140/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
59 EF EXCL 25/697 24/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 4843409 m, 197659 m/sec, 5941509 t fired, .

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-01: CTL true CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-03: CTL false CTL model checker
SieveSingleMsgMbox-PT-d1m64-CTLFireability-05: CTL true CTL model checker
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57 EF FNDP 145/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 27490798 t fired, 3805775 attempts, .
58 EF STEQ 145/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.
59 EF EXCL 30/697 28/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 5817578 m, 194833 m/sec, 7145143 t fired, .

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57 EF FNDP 150/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 28512802 t fired, 3947502 attempts, .
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29 AGEF EXCL 25/862 27/32 SieveSingleMsgMbox-PT-d1m64-CTLFireability-07 5200029 m, 209300 m/sec, 6795381 t fired, .
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57 EF FNDP 801/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 164227898 t fired, 22732389 attempts, .
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57 EF FNDP 1926/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 402771728 t fired, 55755817 attempts, .
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57 EF FNDP 1931/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 403855631 t fired, 55906130 attempts, .
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57 EF FNDP 1936/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 404941602 t fired, 56056678 attempts, .
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57 EF FNDP 1941/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 406028177 t fired, 56207243 attempts, .
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57 EF FNDP 1951/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 408196883 t fired, 56507487 attempts, .
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57 EF FNDP 1956/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 409279029 t fired, 56657292 attempts, .
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57 EF FNDP 1961/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 410362504 t fired, 56807146 attempts, .
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57 EF FNDP 1966/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 411448130 t fired, 56957513 attempts, .
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57 EF FNDP 1971/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 412531929 t fired, 57107516 attempts, .
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57 EF FNDP 1991/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 416585174 t fired, 57668423 attempts, .
58 EF STEQ 1991/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.

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57 EF FNDP 1996/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 417569554 t fired, 57804730 attempts, .
58 EF STEQ 1996/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.

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57 EF FNDP 2001/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 418531070 t fired, 57937642 attempts, .
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57 EF FNDP 2006/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 419515409 t fired, 58074181 attempts, .
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57 EF FNDP 2016/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 421553843 t fired, 58356488 attempts, .
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57 EF FNDP 2327/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 487490485 t fired, 67484476 attempts, .
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57 EF FNDP 2332/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 488565395 t fired, 67633234 attempts, .
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57 EF FNDP 2452/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 514136053 t fired, 71174863 attempts, .
58 EF STEQ 2452/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.

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SieveSingleMsgMbox-PT-d1m64-CTLFireability-04: CTL true CTL model checker
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SieveSingleMsgMbox-PT-d1m64-CTLFireability-09: CTL false CTL model checker
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57 EF FNDP 2457/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 515099072 t fired, 71307880 attempts, .
58 EF STEQ 2457/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.

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57 EF FNDP 2462/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 516082542 t fired, 71444118 attempts, .
58 EF STEQ 2462/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.

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57 EF FNDP 2467/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 517088942 t fired, 71583667 attempts, .
58 EF STEQ 2467/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.

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57 EF FNDP 2472/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 518083941 t fired, 71721549 attempts, .
58 EF STEQ 2472/3600 0/5 SieveSingleMsgMbox-PT-d1m64-CTLFireability-11 sara is running.

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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SieveSingleMsgMbox-PT-d1m64"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SieveSingleMsgMbox-PT-d1m64, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r423-tajo-167905976700434"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SieveSingleMsgMbox-PT-d1m64.tgz
mv SieveSingleMsgMbox-PT-d1m64 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;