fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r422-tajo-167905976000474
Last Updated
May 14, 2023

About the Execution of LoLA for SieveSingleMsgMbox-PT-d2m36

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
4915.859 3600000.00 1786067.00 1587.60 TFF?TT?FTF?T??F? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/mnt/tpsp/fkordon/mcc2023-input.r422-tajo-167905976000474.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2023-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
........................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is SieveSingleMsgMbox-PT-d2m36, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r422-tajo-167905976000474
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.5M
-rw-r--r-- 1 mcc users 8.6K Feb 26 10:27 CTLCardinality.txt
-rw-r--r-- 1 mcc users 95K Feb 26 10:27 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K Feb 26 10:26 CTLFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 26 10:26 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 17:06 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 17:06 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 17:06 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 17:06 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.2K Feb 26 10:29 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 62K Feb 26 10:29 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.4K Feb 26 10:28 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 59K Feb 26 10:28 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 17:06 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 17:06 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 1.1M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SieveSingleMsgMbox-PT-d2m36-CTLFireability-00
FORMULA_NAME SieveSingleMsgMbox-PT-d2m36-CTLFireability-01
FORMULA_NAME SieveSingleMsgMbox-PT-d2m36-CTLFireability-02
FORMULA_NAME SieveSingleMsgMbox-PT-d2m36-CTLFireability-03
FORMULA_NAME SieveSingleMsgMbox-PT-d2m36-CTLFireability-04
FORMULA_NAME SieveSingleMsgMbox-PT-d2m36-CTLFireability-05
FORMULA_NAME SieveSingleMsgMbox-PT-d2m36-CTLFireability-06
FORMULA_NAME SieveSingleMsgMbox-PT-d2m36-CTLFireability-07
FORMULA_NAME SieveSingleMsgMbox-PT-d2m36-CTLFireability-08
FORMULA_NAME SieveSingleMsgMbox-PT-d2m36-CTLFireability-09
FORMULA_NAME SieveSingleMsgMbox-PT-d2m36-CTLFireability-10
FORMULA_NAME SieveSingleMsgMbox-PT-d2m36-CTLFireability-11
FORMULA_NAME SieveSingleMsgMbox-PT-d2m36-CTLFireability-12
FORMULA_NAME SieveSingleMsgMbox-PT-d2m36-CTLFireability-13
FORMULA_NAME SieveSingleMsgMbox-PT-d2m36-CTLFireability-14
FORMULA_NAME SieveSingleMsgMbox-PT-d2m36-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679225452121

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SieveSingleMsgMbox-PT-d2m36
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT SieveSingleMsgMbox-PT-d2m36
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA SieveSingleMsgMbox-PT-d2m36-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d2m36-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d2m36-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d2m36-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d2m36-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d2m36-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d2m36-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d2m36-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SieveSingleMsgMbox-PT-d2m36-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393356 kB
MemFree: 13379184 kB
After kill :
MemTotal: 16393356 kB
MemFree: 16161816 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:182
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,1984 places removed
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH INITIAL
lola: LAUNCH task # 1 (type CNST) for 0 SieveSingleMsgMbox-PT-d2m36-CTLFireability-00
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 1 (type CNST) for SieveSingleMsgMbox-PT-d2m36-CTLFireability-00
lola: result : true
lola: LAUNCH task # 72 (type SKEL/SRCH) for 10 SieveSingleMsgMbox-PT-d2m36-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 72 (type SKEL/SRCH) for SieveSingleMsgMbox-PT-d2m36-CTLFireability-02
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: planning for (null) stopped (result already fixed).
lola: LAUNCH task # 73 (type SKEL/SRCH) for 10 SieveSingleMsgMbox-PT-d2m36-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 48 (type CNST) for 47 SieveSingleMsgMbox-PT-d2m36-CTLFireability-09
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 73 (type SKEL/SRCH) for SieveSingleMsgMbox-PT-d2m36-CTLFireability-02
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 48 (type CNST) for SieveSingleMsgMbox-PT-d2m36-CTLFireability-09
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 42 (type CNST) for 41 SieveSingleMsgMbox-PT-d2m36-CTLFireability-07
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 42 (type CNST) for SieveSingleMsgMbox-PT-d2m36-CTLFireability-07
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 25 (type EXCL) for 10 SieveSingleMsgMbox-PT-d2m36-CTLFireability-02
lola: time limit : 124 sec
lola: memory limit: 32 pages
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:754
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
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sara: try reading problem file /home/mcc/execution/CTLFireability-81.sara.
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
SieveSingleMsgMbox-PT-d2m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 50/211 26/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-02 4023311 m, 56560 m/sec, 5009121 t fired, .
80 EF FNDP 49/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 3438585 t fired, 474057 attempts, .
81 EF STEQ 49/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-00: INITIAL true preprocessing
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-09: INITIAL false preprocessing

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-02: CONJ 0 2 1 0 7 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
SieveSingleMsgMbox-PT-d2m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 55/211 27/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-02 4298531 m, 55044 m/sec, 5353759 t fired, .
80 EF FNDP 54/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 3807556 t fired, 524946 attempts, .
81 EF STEQ 54/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-00: INITIAL true preprocessing
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
SieveSingleMsgMbox-PT-d2m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 60/211 29/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-02 4581890 m, 56671 m/sec, 5688188 t fired, .
80 EF FNDP 59/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 4174707 t fired, 575693 attempts, .
81 EF STEQ 59/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
SieveSingleMsgMbox-PT-d2m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 65/211 30/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-02 4847642 m, 53150 m/sec, 6047661 t fired, .
80 EF FNDP 64/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 4517066 t fired, 622987 attempts, .
81 EF STEQ 64/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
SieveSingleMsgMbox-PT-d2m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 70/211 32/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-02 5112292 m, 52930 m/sec, 6417837 t fired, .
80 EF FNDP 69/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 4861516 t fired, 670545 attempts, .
81 EF STEQ 69/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-02: CONJ 0 2 0 0 7 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
SieveSingleMsgMbox-PT-d2m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
80 EF FNDP 74/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 5229606 t fired, 721383 attempts, .
81 EF STEQ 74/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
SieveSingleMsgMbox-PT-d2m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 CTL EXCL 5/251 2/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-15 287319 m, 57463 m/sec, 355164 t fired, .
80 EF FNDP 79/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 5596860 t fired, 772087 attempts, .
81 EF STEQ 79/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-07: INITIAL false preprocessing
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
SieveSingleMsgMbox-PT-d2m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 CTL EXCL 10/251 4/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-15 574274 m, 57391 m/sec, 701664 t fired, .
80 EF FNDP 84/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 5965054 t fired, 823010 attempts, .
81 EF STEQ 84/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 CTL EXCL 15/251 7/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-15 1070024 m, 99150 m/sec, 1320848 t fired, .
80 EF FNDP 89/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 6332898 t fired, 873604 attempts, .
81 EF STEQ 89/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 CTL EXCL 20/251 9/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-15 1348408 m, 55676 m/sec, 1668229 t fired, .
80 EF FNDP 94/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 6700481 t fired, 924357 attempts, .
81 EF STEQ 94/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

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70 CTL EXCL 25/251 11/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-15 1620461 m, 54410 m/sec, 2041554 t fired, .
80 EF FNDP 99/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 7067121 t fired, 975015 attempts, .
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70 CTL EXCL 30/251 13/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-15 1913859 m, 58679 m/sec, 2376709 t fired, .
80 EF FNDP 104/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 7435172 t fired, 1025793 attempts, .
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70 CTL EXCL 35/251 14/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-15 2196152 m, 56458 m/sec, 2721616 t fired, .
80 EF FNDP 109/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 7803049 t fired, 1076515 attempts, .
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70 CTL EXCL 40/251 16/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-15 2474439 m, 55657 m/sec, 3060886 t fired, .
80 EF FNDP 114/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 8171372 t fired, 1127632 attempts, .
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70 CTL EXCL 45/251 17/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-15 2742211 m, 53554 m/sec, 3425811 t fired, .
80 EF FNDP 119/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 8539217 t fired, 1178112 attempts, .
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70 CTL EXCL 50/251 19/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-15 2989753 m, 49508 m/sec, 3765925 t fired, .
80 EF FNDP 124/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 8869812 t fired, 1223750 attempts, .
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70 CTL EXCL 55/251 21/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-15 3248849 m, 51819 m/sec, 4081905 t fired, .
80 EF FNDP 129/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 9192202 t fired, 1268314 attempts, .
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70 CTL EXCL 60/251 23/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-15 3506881 m, 51606 m/sec, 4382257 t fired, .
80 EF FNDP 134/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 9554314 t fired, 1318345 attempts, .
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80 EF FNDP 139/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 9917824 t fired, 1368646 attempts, .
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70 CTL EXCL 80/251 30/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-15 4710398 m, 67730 m/sec, 5864151 t fired, .
80 EF FNDP 154/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 10961416 t fired, 1512693 attempts, .
81 EF STEQ 154/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
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70 CTL EXCL 85/251 31/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-15 4994076 m, 56735 m/sec, 6260979 t fired, .
80 EF FNDP 159/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 11319551 t fired, 1562205 attempts, .
81 EF STEQ 159/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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80 EF FNDP 164/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 11666654 t fired, 1610004 attempts, .
81 EF STEQ 164/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
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64 CTL EXCL 5/264 2/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 271792 m, 54358 m/sec, 1149905 t fired, .
80 EF FNDP 169/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 12000568 t fired, 1655868 attempts, .
81 EF STEQ 169/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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64 CTL EXCL 10/264 4/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 493306 m, 44302 m/sec, 2083277 t fired, .
80 EF FNDP 174/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 12368989 t fired, 1706841 attempts, .
81 EF STEQ 174/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 15/264 5/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 656103 m, 32559 m/sec, 2781814 t fired, .
80 EF FNDP 179/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 12737275 t fired, 1757476 attempts, .
81 EF STEQ 179/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 20/264 6/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 811122 m, 31003 m/sec, 3443842 t fired, .
80 EF FNDP 184/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 13105163 t fired, 1808051 attempts, .
81 EF STEQ 184/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 25/264 7/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 961614 m, 30098 m/sec, 4073607 t fired, .
80 EF FNDP 189/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 13472469 t fired, 1858747 attempts, .
81 EF STEQ 189/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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64 CTL EXCL 30/264 8/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 1109900 m, 29657 m/sec, 4697222 t fired, .
80 EF FNDP 194/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 13839730 t fired, 1909468 attempts, .
81 EF STEQ 194/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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64 CTL EXCL 35/264 8/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 1256373 m, 29294 m/sec, 5314873 t fired, .
80 EF FNDP 199/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 14208074 t fired, 1960322 attempts, .
81 EF STEQ 199/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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64 CTL EXCL 40/264 9/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 1400052 m, 28735 m/sec, 5941181 t fired, .
80 EF FNDP 204/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 14575915 t fired, 2011169 attempts, .
81 EF STEQ 204/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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64 CTL EXCL 45/264 10/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 1544515 m, 28892 m/sec, 6574221 t fired, .
80 EF FNDP 209/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 14944117 t fired, 2061928 attempts, .
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64 CTL EXCL 50/264 11/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 1694297 m, 29956 m/sec, 7204924 t fired, .
80 EF FNDP 214/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 15311844 t fired, 2112729 attempts, .
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64 CTL EXCL 55/264 12/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 1844789 m, 30098 m/sec, 7831090 t fired, .
80 EF FNDP 219/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 15679812 t fired, 2163489 attempts, .
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64 CTL EXCL 60/264 13/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 2020691 m, 35180 m/sec, 8578909 t fired, .
80 EF FNDP 224/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 16048246 t fired, 2214493 attempts, .
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64 CTL EXCL 65/264 14/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 2168943 m, 29650 m/sec, 9196854 t fired, .
80 EF FNDP 229/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 16416685 t fired, 2265540 attempts, .
81 EF STEQ 229/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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64 CTL EXCL 70/264 15/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 2313863 m, 28984 m/sec, 9814783 t fired, .
80 EF FNDP 234/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 16784927 t fired, 2316378 attempts, .
81 EF STEQ 234/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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64 CTL EXCL 75/264 16/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 2461124 m, 29452 m/sec, 10428613 t fired, .
80 EF FNDP 239/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 17152641 t fired, 2367254 attempts, .
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64 CTL EXCL 80/264 17/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 2615481 m, 30871 m/sec, 11094824 t fired, .
80 EF FNDP 244/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 17396741 t fired, 2400957 attempts, .
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64 CTL EXCL 85/264 17/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 2756992 m, 28302 m/sec, 11718907 t fired, .
80 EF FNDP 249/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 17579812 t fired, 2426271 attempts, .
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64 CTL EXCL 90/264 18/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 2901611 m, 28923 m/sec, 12348388 t fired, .
80 EF FNDP 254/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 17763319 t fired, 2451601 attempts, .
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64 CTL EXCL 95/264 19/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 3047375 m, 29152 m/sec, 12981262 t fired, .
80 EF FNDP 259/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 17946887 t fired, 2477052 attempts, .
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64 CTL EXCL 100/264 20/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 3190413 m, 28607 m/sec, 13588775 t fired, .
80 EF FNDP 264/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 18123517 t fired, 2501607 attempts, .
81 EF STEQ 264/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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64 CTL EXCL 105/264 21/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 3320632 m, 26043 m/sec, 14125781 t fired, .
80 EF FNDP 269/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 18282333 t fired, 2523559 attempts, .
81 EF STEQ 269/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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64 CTL EXCL 110/264 22/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 3457147 m, 27303 m/sec, 14694399 t fired, .
80 EF FNDP 274/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 18448912 t fired, 2546698 attempts, .
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64 CTL EXCL 115/264 23/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 3597334 m, 28037 m/sec, 15278618 t fired, .
80 EF FNDP 279/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 18620914 t fired, 2570321 attempts, .
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64 CTL EXCL 120/264 25/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 3844537 m, 49440 m/sec, 16333582 t fired, .
80 EF FNDP 284/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 18928773 t fired, 2613080 attempts, .
81 EF STEQ 284/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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64 CTL EXCL 125/264 26/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 4113297 m, 53752 m/sec, 17457319 t fired, .
80 EF FNDP 289/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 19260549 t fired, 2658875 attempts, .
81 EF STEQ 289/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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64 CTL EXCL 130/264 28/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 4380831 m, 53506 m/sec, 18592631 t fired, .
80 EF FNDP 294/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 19581032 t fired, 2703220 attempts, .
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64 CTL EXCL 135/264 29/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 4527228 m, 29279 m/sec, 19203089 t fired, .
80 EF FNDP 299/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 19764799 t fired, 2728591 attempts, .
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64 CTL EXCL 140/264 30/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 4692401 m, 33034 m/sec, 19917858 t fired, .
80 EF FNDP 304/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 19959003 t fired, 2755398 attempts, .
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64 CTL EXCL 145/264 30/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 4842308 m, 29981 m/sec, 20567681 t fired, .
80 EF FNDP 309/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 20143471 t fired, 2780881 attempts, .
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64 CTL EXCL 150/264 31/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 4964112 m, 24360 m/sec, 21108020 t fired, .
80 EF FNDP 314/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 20302420 t fired, 2802843 attempts, .
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 155/264 32/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-13 5177833 m, 42744 m/sec, 22038686 t fired, .
80 EF FNDP 319/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 20568679 t fired, 2839411 attempts, .
81 EF STEQ 319/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
80 EF FNDP 324/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 20921165 t fired, 2888056 attempts, .
81 EF STEQ 324/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 5/297 2/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-10 282511 m, 56502 m/sec, 348890 t fired, .
80 EF FNDP 329/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 21093250 t fired, 2911914 attempts, .
81 EF STEQ 329/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 10/297 4/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-10 586468 m, 60791 m/sec, 716076 t fired, .
80 EF FNDP 334/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 21276348 t fired, 2937302 attempts, .
81 EF STEQ 334/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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53 CTL EXCL 15/297 6/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-10 883536 m, 59413 m/sec, 1094235 t fired, .
80 EF FNDP 339/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 21459677 t fired, 2962566 attempts, .
81 EF STEQ 339/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 20/297 9/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-10 1418641 m, 107021 m/sec, 1768289 t fired, .
80 EF FNDP 344/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 21768789 t fired, 3005364 attempts, .
81 EF STEQ 344/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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53 CTL EXCL 25/297 13/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-10 2020721 m, 120416 m/sec, 2516870 t fired, .
80 EF FNDP 349/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 22135689 t fired, 3055921 attempts, .
81 EF STEQ 349/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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53 CTL EXCL 30/297 17/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-10 2608921 m, 117640 m/sec, 3239112 t fired, .
80 EF FNDP 354/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 22502777 t fired, 3106713 attempts, .
81 EF STEQ 354/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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53 CTL EXCL 35/297 20/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-10 3146236 m, 107463 m/sec, 3969116 t fired, .
80 EF FNDP 359/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 22846471 t fired, 3154313 attempts, .
81 EF STEQ 359/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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53 CTL EXCL 40/297 22/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-10 3453807 m, 61514 m/sec, 4319085 t fired, .
80 EF FNDP 364/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 23030087 t fired, 3179624 attempts, .
81 EF STEQ 364/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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53 CTL EXCL 45/297 24/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-10 3748727 m, 58984 m/sec, 4688016 t fired, .
80 EF FNDP 369/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 23212017 t fired, 3204793 attempts, .
81 EF STEQ 369/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
SieveSingleMsgMbox-PT-d2m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 1 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 50/297 26/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-10 4045185 m, 59291 m/sec, 5034252 t fired, .
80 EF FNDP 374/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 23394978 t fired, 3230130 attempts, .
81 EF STEQ 374/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-00: INITIAL true preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-02: CONJ false state space /EXEG
SieveSingleMsgMbox-PT-d2m36-CTLFireability-07: INITIAL false preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-09: INITIAL false preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL true CTL model checker

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
SieveSingleMsgMbox-PT-d2m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 1 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 55/297 28/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-10 4389195 m, 68802 m/sec, 5459751 t fired, .
80 EF FNDP 379/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 23590328 t fired, 3257085 attempts, .
81 EF STEQ 379/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-07: INITIAL false preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-09: INITIAL false preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL true CTL model checker

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
SieveSingleMsgMbox-PT-d2m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 1 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 60/297 29/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-10 4675525 m, 57266 m/sec, 5818486 t fired, .
80 EF FNDP 384/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 23773106 t fired, 3282304 attempts, .
81 EF STEQ 384/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-07: INITIAL false preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-09: INITIAL false preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL true CTL model checker

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 1 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 65/297 31/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-10 4952491 m, 55393 m/sec, 6196583 t fired, .
80 EF FNDP 389/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 23954959 t fired, 3307413 attempts, .
81 EF STEQ 389/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-09: INITIAL false preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL true CTL model checker

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 1 1 0 2 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 70/297 32/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-10 5229601 m, 55422 m/sec, 6578527 t fired, .
80 EF FNDP 394/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 24138226 t fired, 3332766 attempts, .
81 EF STEQ 394/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-09: INITIAL false preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL true CTL model checker

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 1 0 0 2 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
80 EF FNDP 399/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 24494352 t fired, 3382097 attempts, .
81 EF STEQ 399/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-07: INITIAL false preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-09: INITIAL false preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL true CTL model checker

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 1 0 0 2 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 5/319 4/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-06 557248 m, 111449 m/sec, 681957 t fired, .
80 EF FNDP 404/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 24725009 t fired, 3414032 attempts, .
81 EF STEQ 404/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-00: INITIAL true preprocessing
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-07: INITIAL false preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-09: INITIAL false preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL true CTL model checker

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 1 0 0 2 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 10/319 8/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-06 1136583 m, 115867 m/sec, 1404215 t fired, .
80 EF FNDP 409/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 25038390 t fired, 3457376 attempts, .
81 EF STEQ 409/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-09: INITIAL false preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL true CTL model checker

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 1 0 0 2 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 15/319 11/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-06 1698358 m, 112355 m/sec, 2126735 t fired, .
80 EF FNDP 414/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 25380905 t fired, 3504464 attempts, .
81 EF STEQ 414/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL true CTL model checker

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 1 0 0 2 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 20/319 14/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-06 2044743 m, 69277 m/sec, 2544871 t fired, .
80 EF FNDP 419/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 25658016 t fired, 3542617 attempts, .
81 EF STEQ 419/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL true CTL model checker

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 1 0 0 2 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 25/319 15/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-06 2333902 m, 57831 m/sec, 2896744 t fired, .
80 EF FNDP 424/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 26022131 t fired, 3592990 attempts, .
81 EF STEQ 424/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF 0 1 2 0 4 0 0 1
SieveSingleMsgMbox-PT-d2m36-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 1 0 0 2 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 30/319 17/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-06 2620155 m, 57250 m/sec, 3254502 t fired, .
80 EF FNDP 429/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 26384915 t fired, 3643286 attempts, .
81 EF STEQ 429/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-07: INITIAL false preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-09: INITIAL false preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL true CTL model checker

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 1 0 0 2 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 35/319 20/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-06 3083582 m, 92685 m/sec, 3888580 t fired, .
80 EF FNDP 434/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 26573063 t fired, 3669243 attempts, .
81 EF STEQ 434/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-09: INITIAL false preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL true CTL model checker

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 1 0 0 2 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 40/319 24/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-06 3673404 m, 117964 m/sec, 4585433 t fired, .
80 EF FNDP 439/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 26756507 t fired, 3694581 attempts, .
81 EF STEQ 439/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-09: INITIAL false preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL true CTL model checker

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 1 0 0 2 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 45/319 27/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-06 4221522 m, 109623 m/sec, 5264278 t fired, .
80 EF FNDP 444/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 26939582 t fired, 3719859 attempts, .
81 EF STEQ 444/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-09: INITIAL false preprocessing
SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL true CTL model checker

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 1 0 0 2 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 50/319 30/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-06 4762944 m, 108284 m/sec, 5935095 t fired, .
80 EF FNDP 449/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 27120765 t fired, 3744993 attempts, .
81 EF STEQ 449/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-09: INITIAL false preprocessing
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-10: DISJ 0 1 0 0 2 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
80 EF FNDP 454/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 27304204 t fired, 3770254 attempts, .
81 EF STEQ 454/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-05: CTL true CTL model checker
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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8 CTL EXCL 5/392 4/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-01 540748 m, 108149 m/sec, 662812 t fired, .
80 EF FNDP 459/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 27487283 t fired, 3795465 attempts, .
81 EF STEQ 459/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-05: CTL true CTL model checker
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-09: INITIAL false preprocessing
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-08: EG 0 1 0 0 1 0 0 0
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8 CTL EXCL 10/392 7/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-01 1077001 m, 107250 m/sec, 1328807 t fired, .
80 EF FNDP 464/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 27670359 t fired, 3820590 attempts, .
81 EF STEQ 464/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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8 CTL EXCL 15/392 10/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-01 1530829 m, 90765 m/sec, 1923225 t fired, .
80 EF FNDP 469/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 27878926 t fired, 3849331 attempts, .
81 EF STEQ 469/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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8 CTL EXCL 20/392 12/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-01 1807778 m, 55389 m/sec, 2253271 t fired, .
80 EF FNDP 474/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 28195541 t fired, 3893088 attempts, .
81 EF STEQ 474/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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8 CTL EXCL 25/392 14/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-01 2081804 m, 54805 m/sec, 2588437 t fired, .
80 EF FNDP 479/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 28523481 t fired, 3938292 attempts, .
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8 CTL EXCL 30/392 15/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-01 2351941 m, 54027 m/sec, 2918232 t fired, .
80 EF FNDP 484/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 28890848 t fired, 3989066 attempts, .
81 EF STEQ 484/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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8 CTL EXCL 35/392 17/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-01 2591752 m, 47962 m/sec, 3215918 t fired, .
80 EF FNDP 489/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 29187579 t fired, 4030119 attempts, .
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8 CTL EXCL 40/392 19/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-01 2974321 m, 76513 m/sec, 3746371 t fired, .
80 EF FNDP 494/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 29393629 t fired, 4058691 attempts, .
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8 CTL EXCL 45/392 23/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-01 3502091 m, 105554 m/sec, 4376384 t fired, .
80 EF FNDP 499/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 29557319 t fired, 4081228 attempts, .
81 EF STEQ 499/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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8 CTL EXCL 50/392 26/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-01 3991734 m, 97928 m/sec, 4972567 t fired, .
80 EF FNDP 504/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 29729942 t fired, 4105109 attempts, .
81 EF STEQ 504/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 sara is running.

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8 CTL EXCL 55/392 28/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-01 4474231 m, 96499 m/sec, 5560013 t fired, .
80 EF FNDP 509/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 30079298 t fired, 4153315 attempts, .
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8 CTL EXCL 60/392 30/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-01 4919198 m, 88993 m/sec, 6144953 t fired, .
80 EF FNDP 514/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 30437959 t fired, 4202787 attempts, .
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80 EF FNDP 519/3596 0/5 SieveSingleMsgMbox-PT-d2m36-CTLFireability-04 30799989 t fired, 4252755 attempts, .
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30 CTL EXCL 9/615 5/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-03 717560 m, 73740 m/sec, 1704433 t fired, .

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30 CTL EXCL 14/615 8/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-03 1109553 m, 78398 m/sec, 2609385 t fired, .

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SieveSingleMsgMbox-PT-d2m36-CTLFireability-04: EF true state space
SieveSingleMsgMbox-PT-d2m36-CTLFireability-05: CTL true CTL model checker
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SieveSingleMsgMbox-PT-d2m36-CTLFireability-11: CTL true CTL model checker

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30 CTL EXCL 20/615 10/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-03 1490460 m, 76181 m/sec, 3533510 t fired, .

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30 CTL EXCL 25/615 13/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-03 1915271 m, 84962 m/sec, 4516577 t fired, .

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30 CTL EXCL 30/615 15/32 SieveSingleMsgMbox-PT-d2m36-CTLFireability-03 2287107 m, 74367 m/sec, 5396085 t fired, .

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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SieveSingleMsgMbox-PT-d2m36"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is SieveSingleMsgMbox-PT-d2m36, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r422-tajo-167905976000474"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SieveSingleMsgMbox-PT-d2m36.tgz
mv SieveSingleMsgMbox-PT-d2m36 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;