About the Execution of LTSMin+red for RwMutex-PT-r0010w0010
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
246.359 | 8174.00 | 17222.00 | 480.80 | TFFTTFTTTTTTFTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r361-smll-167891810900106.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool ltsminxred
Input is RwMutex-PT-r0010w0010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r361-smll-167891810900106
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 440K
-rw-r--r-- 1 mcc users 4.9K Feb 25 22:40 CTLCardinality.txt
-rw-r--r-- 1 mcc users 45K Feb 25 22:40 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.8K Feb 25 22:39 CTLFireability.txt
-rw-r--r-- 1 mcc users 55K Feb 25 22:39 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:48 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 25 16:48 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:48 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:48 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 22:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 128K Feb 25 22:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.8K Feb 25 22:40 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 25 22:40 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:48 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:48 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 11 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 27K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RwMutex-PT-r0010w0010-CTLFireability-00
FORMULA_NAME RwMutex-PT-r0010w0010-CTLFireability-01
FORMULA_NAME RwMutex-PT-r0010w0010-CTLFireability-02
FORMULA_NAME RwMutex-PT-r0010w0010-CTLFireability-03
FORMULA_NAME RwMutex-PT-r0010w0010-CTLFireability-04
FORMULA_NAME RwMutex-PT-r0010w0010-CTLFireability-05
FORMULA_NAME RwMutex-PT-r0010w0010-CTLFireability-06
FORMULA_NAME RwMutex-PT-r0010w0010-CTLFireability-07
FORMULA_NAME RwMutex-PT-r0010w0010-CTLFireability-08
FORMULA_NAME RwMutex-PT-r0010w0010-CTLFireability-09
FORMULA_NAME RwMutex-PT-r0010w0010-CTLFireability-10
FORMULA_NAME RwMutex-PT-r0010w0010-CTLFireability-11
FORMULA_NAME RwMutex-PT-r0010w0010-CTLFireability-12
FORMULA_NAME RwMutex-PT-r0010w0010-CTLFireability-13
FORMULA_NAME RwMutex-PT-r0010w0010-CTLFireability-14
FORMULA_NAME RwMutex-PT-r0010w0010-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679046385262
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RwMutex-PT-r0010w0010
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202303021504
[2023-03-17 09:46:28] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 09:46:28] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 09:46:28] [INFO ] Load time of PNML (sax parser for PT used): 53 ms
[2023-03-17 09:46:28] [INFO ] Transformed 50 places.
[2023-03-17 09:46:28] [INFO ] Transformed 40 transitions.
[2023-03-17 09:46:28] [INFO ] Found NUPN structural information;
[2023-03-17 09:46:28] [INFO ] Parsed PT model containing 50 places and 40 transitions and 300 arcs in 148 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 15 ms.
Initial state reduction rules removed 4 formulas.
FORMULA RwMutex-PT-r0010w0010-CTLFireability-00 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RwMutex-PT-r0010w0010-CTLFireability-04 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RwMutex-PT-r0010w0010-CTLFireability-10 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RwMutex-PT-r0010w0010-CTLFireability-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 46 out of 50 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 50/50 places, 40/40 transitions.
Applied a total of 0 rules in 15 ms. Remains 50 /50 variables (removed 0) and now considering 40/40 (removed 0) transitions.
// Phase 1: matrix 40 rows 50 cols
[2023-03-17 09:46:28] [INFO ] Computed 30 place invariants in 11 ms
[2023-03-17 09:46:28] [INFO ] Implicit Places using invariants in 251 ms returned [1, 7, 47]
Discarding 3 places :
Implicit Place search using SMT only with invariants took 295 ms to find 3 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 47/50 places, 40/40 transitions.
Applied a total of 0 rules in 2 ms. Remains 47 /47 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in LTL mode , in 2 iterations and 313 ms. Remains : 47/50 places, 40/40 transitions.
Support contains 46 out of 47 places after structural reductions.
[2023-03-17 09:46:29] [INFO ] Flatten gal took : 39 ms
[2023-03-17 09:46:29] [INFO ] Flatten gal took : 17 ms
[2023-03-17 09:46:29] [INFO ] Input system was already deterministic with 40 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1020 ms. (steps per millisecond=9 ) properties (out of 45) seen :38
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 7) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 74 ms. (steps per millisecond=135 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 35 ms. (steps per millisecond=285 ) properties (out of 6) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 5) seen :0
Running SMT prover for 5 properties.
// Phase 1: matrix 40 rows 47 cols
[2023-03-17 09:46:30] [INFO ] Computed 27 place invariants in 6 ms
[2023-03-17 09:46:30] [INFO ] [Real]Absence check using 27 positive place invariants in 20 ms returned sat
[2023-03-17 09:46:30] [INFO ] After 123ms SMT Verify possible using all constraints in real domain returned unsat :4 sat :0 real:1
[2023-03-17 09:46:30] [INFO ] [Nat]Absence check using 27 positive place invariants in 16 ms returned sat
[2023-03-17 09:46:30] [INFO ] After 74ms SMT Verify possible using all constraints in natural domain returned unsat :5 sat :0
Fused 5 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 5 atomic propositions for a total of 12 simplifications.
[2023-03-17 09:46:30] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-17 09:46:30] [INFO ] Flatten gal took : 13 ms
FORMULA RwMutex-PT-r0010w0010-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-17 09:46:30] [INFO ] Flatten gal took : 11 ms
[2023-03-17 09:46:30] [INFO ] Input system was already deterministic with 40 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 40/40 transitions.
Applied a total of 0 rules in 3 ms. Remains 47 /47 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 47/47 places, 40/40 transitions.
[2023-03-17 09:46:30] [INFO ] Flatten gal took : 8 ms
[2023-03-17 09:46:30] [INFO ] Flatten gal took : 8 ms
[2023-03-17 09:46:30] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 40/40 transitions.
Applied a total of 0 rules in 1 ms. Remains 47 /47 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 47/47 places, 40/40 transitions.
[2023-03-17 09:46:30] [INFO ] Flatten gal took : 7 ms
[2023-03-17 09:46:30] [INFO ] Flatten gal took : 7 ms
[2023-03-17 09:46:31] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 40/40 transitions.
Applied a total of 0 rules in 1 ms. Remains 47 /47 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 47/47 places, 40/40 transitions.
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:46:31] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 47/47 places, 40/40 transitions.
Graph (trivial) has 4 edges and 47 vertex of which 4 / 47 are part of one of the 2 SCC in 4 ms
Free SCC test removed 2 places
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 17 transitions
Trivial Post-agglo rules discarded 17 transitions
Performed 17 trivial Post agglomeration. Transition count delta: 17
Iterating post reduction 0 with 17 rules applied. Total rules applied 18 place count 45 transition count 21
Reduce places removed 42 places and 0 transitions.
Ensure Unique test removed 17 transitions
Reduce isomorphic transitions removed 17 transitions.
Iterating post reduction 1 with 59 rules applied. Total rules applied 77 place count 3 transition count 4
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 78 place count 3 transition count 3
Ensure Unique test removed 1 places
Iterating post reduction 2 with 1 rules applied. Total rules applied 79 place count 2 transition count 3
Applied a total of 79 rules in 13 ms. Remains 2 /47 variables (removed 45) and now considering 3/40 (removed 37) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 2/47 places, 3/40 transitions.
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 1 ms
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 1 ms
[2023-03-17 09:46:31] [INFO ] Input system was already deterministic with 3 transitions.
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 40/40 transitions.
Applied a total of 0 rules in 1 ms. Remains 47 /47 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 47/47 places, 40/40 transitions.
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 5 ms
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:46:31] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 47/47 places, 40/40 transitions.
Applied a total of 0 rules in 5 ms. Remains 47 /47 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 47/47 places, 40/40 transitions.
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:46:31] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 40/40 transitions.
Applied a total of 0 rules in 2 ms. Remains 47 /47 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 47/47 places, 40/40 transitions.
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 5 ms
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:46:31] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 40/40 transitions.
Applied a total of 0 rules in 1 ms. Remains 47 /47 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 47/47 places, 40/40 transitions.
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:46:31] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 47/47 places, 40/40 transitions.
Applied a total of 0 rules in 4 ms. Remains 47 /47 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 47/47 places, 40/40 transitions.
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:46:31] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 47/47 places, 40/40 transitions.
Applied a total of 0 rules in 5 ms. Remains 47 /47 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 47/47 places, 40/40 transitions.
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 5 ms
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 13 ms
[2023-03-17 09:46:31] [INFO ] Input system was already deterministic with 40 transitions.
Starting structural reductions in LTL mode, iteration 0 : 47/47 places, 40/40 transitions.
Applied a total of 0 rules in 2 ms. Remains 47 /47 variables (removed 0) and now considering 40/40 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 47/47 places, 40/40 transitions.
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 5 ms
[2023-03-17 09:46:31] [INFO ] Input system was already deterministic with 40 transitions.
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:46:31] [INFO ] Flatten gal took : 6 ms
[2023-03-17 09:46:31] [INFO ] Export to MCC of 11 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-17 09:46:31] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 47 places, 40 transitions and 294 arcs took 1 ms.
Total runtime 3179 ms.
There are residual formulas that ITS could not solve within timeout
pnml2lts-sym model.pnml --lace-workers=4 --vset=lddmc --saturation=sat -rbs,w2W,ru,hf --sylvan-sizes=20,28,20,28 --ctl=/tmp/461/ctl_0_ --ctl=/tmp/461/ctl_1_ --ctl=/tmp/461/ctl_2_ --ctl=/tmp/461/ctl_3_ --ctl=/tmp/461/ctl_4_ --ctl=/tmp/461/ctl_5_ --ctl=/tmp/461/ctl_6_ --ctl=/tmp/461/ctl_7_ --ctl=/tmp/461/ctl_8_ --ctl=/tmp/461/ctl_9_ --ctl=/tmp/461/ctl_10_ --mu-par --mu-opt
FORMULA RwMutex-PT-r0010w0010-CTLFireability-01 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA RwMutex-PT-r0010w0010-CTLFireability-02 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA RwMutex-PT-r0010w0010-CTLFireability-03 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA RwMutex-PT-r0010w0010-CTLFireability-05 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA RwMutex-PT-r0010w0010-CTLFireability-06 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA RwMutex-PT-r0010w0010-CTLFireability-07 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA RwMutex-PT-r0010w0010-CTLFireability-08 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA RwMutex-PT-r0010w0010-CTLFireability-09 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA RwMutex-PT-r0010w0010-CTLFireability-11 TRUE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA RwMutex-PT-r0010w0010-CTLFireability-12 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
FORMULA RwMutex-PT-r0010w0010-CTLFireability-15 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
BK_STOP 1679046393436
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
mcc2023
ctl formula name RwMutex-PT-r0010w0010-CTLFireability-01
ctl formula formula --ctl=/tmp/461/ctl_0_
ctl formula name RwMutex-PT-r0010w0010-CTLFireability-02
ctl formula formula --ctl=/tmp/461/ctl_1_
ctl formula name RwMutex-PT-r0010w0010-CTLFireability-03
ctl formula formula --ctl=/tmp/461/ctl_2_
ctl formula name RwMutex-PT-r0010w0010-CTLFireability-05
ctl formula formula --ctl=/tmp/461/ctl_3_
ctl formula name RwMutex-PT-r0010w0010-CTLFireability-06
ctl formula formula --ctl=/tmp/461/ctl_4_
ctl formula name RwMutex-PT-r0010w0010-CTLFireability-07
ctl formula formula --ctl=/tmp/461/ctl_5_
ctl formula name RwMutex-PT-r0010w0010-CTLFireability-08
ctl formula formula --ctl=/tmp/461/ctl_6_
ctl formula name RwMutex-PT-r0010w0010-CTLFireability-09
ctl formula formula --ctl=/tmp/461/ctl_7_
ctl formula name RwMutex-PT-r0010w0010-CTLFireability-11
ctl formula formula --ctl=/tmp/461/ctl_8_
ctl formula name RwMutex-PT-r0010w0010-CTLFireability-12
ctl formula formula --ctl=/tmp/461/ctl_9_
ctl formula name RwMutex-PT-r0010w0010-CTLFireability-15
ctl formula formula --ctl=/tmp/461/ctl_10_
pnml2lts-sym: Exploration order is bfs-prev
pnml2lts-sym: Saturation strategy is sat
pnml2lts-sym: Guided search strategy is unguided
pnml2lts-sym: Attractor strategy is default
pnml2lts-sym: opening model.pnml
pnml2lts-sym: Edge label is id
Warning: program compiled against libxml 210 using older 209
pnml2lts-sym: Petri net has 47 places, 40 transitions and 294 arcs
pnml2lts-sym: Petri net Petri analyzed
pnml2lts-sym: There are no safe places
pnml2lts-sym: Loading Petri net took 0.000 real 0.000 user 0.000 sys
pnml2lts-sym: Initializing regrouping layer
pnml2lts-sym: Regroup specification: bs,w2W,ru,hf
pnml2lts-sym: Regroup Boost's Sloan
pnml2lts-sym: Regroup over-approximate must-write to may-write
pnml2lts-sym: Regroup Row sUbsume
pnml2lts-sym: Reqroup Horizontal Flip
pnml2lts-sym: Regrouping: 40->20 groups
pnml2lts-sym: Regrouping took 0.010 real 0.000 user 0.000 sys
pnml2lts-sym: state vector length is 47; there are 20 groups
pnml2lts-sym: Creating a multi-core ListDD domain.
pnml2lts-sym: Sylvan allocates 15.000 GB virtual memory for nodes table and operation cache.
pnml2lts-sym: Initial nodes table and operation cache requires 60.00 MB.
pnml2lts-sym: Using GBgetTransitionsShortR2W as next-state function
pnml2lts-sym: got initial state
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: Exploration took 5180 group checks and 0 next state calls
pnml2lts-sym: reachability took 0.130 real 0.460 user 0.060 sys
pnml2lts-sym: counting visited states...
pnml2lts-sym: counting took 0.000 real 0.000 user 0.000 sys
pnml2lts-sym: state space has 1034 states, 11326 nodes
pnml2lts-sym: Formula /tmp/461/ctl_0_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_3_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_10_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_4_ holds for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_6_ holds for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_1_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_9_ does not hold for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_8_ holds for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_7_ holds for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_5_ holds for the initial state
pnml2lts-sym: Formula /tmp/461/ctl_2_ holds for the initial state
pnml2lts-sym: group_next: 628 nodes total
pnml2lts-sym: group_explored: 404 nodes, 10280 short vectors total
pnml2lts-sym: max token count: 1
*** segmentation fault ***
Please send information on how to reproduce this problem to:
ltsmin-support@lists.utwente.nl
along with all output preceding this message.
In addition, include the following information:
Package: ltsmin 3.1.0
Stack trace:
0: pnml2lts-sym(+0x9b684) [0x56297b203684]
1: pnml2lts-sym(+0x9b726) [0x56297b203726]
2: /lib/x86_64-linux-gnu/libpthread.so.0(+0x13140) [0x7f4016eb1140]
3: /lib/x86_64-linux-gnu/libc.so.6(+0x87870) [0x7f4016bf1870]
4: /lib/x86_64-linux-gnu/libpthread.so.0(+0x7ebf) [0x7f4016ea5ebf]
5: /lib/x86_64-linux-gnu/libc.so.6(clone+0x3f) [0x7f4016c66a2f]
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RwMutex-PT-r0010w0010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool ltsminxred"
echo " Input is RwMutex-PT-r0010w0010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r361-smll-167891810900106"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RwMutex-PT-r0010w0010.tgz
mv RwMutex-PT-r0010w0010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;