About the Execution of LoLa+red for SharedMemory-PT-000100
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16202.224 | 3600000.00 | 3705467.00 | 35796.50 | [undef] | Time out reached |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r359-smll-167891809400690.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SharedMemory-PT-000100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-167891809400690
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 151M
-rw-r--r-- 1 mcc users 3.9M Feb 26 00:39 CTLCardinality.txt
-rw-r--r-- 1 mcc users 15M Feb 26 00:39 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.2M Feb 25 22:09 CTLFireability.txt
-rw-r--r-- 1 mcc users 12M Feb 25 22:09 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 849K Feb 25 16:53 LTLCardinality.txt
-rw-r--r-- 1 mcc users 2.3M Feb 25 16:53 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.2M Feb 25 16:53 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.3M Feb 25 16:53 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.0M Feb 26 08:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 33M Feb 26 08:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11M Feb 26 04:36 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 41M Feb 26 04:36 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 16:53 UpperBounds.txt
-rw-r--r-- 1 mcc users 30K Feb 25 16:53 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 11M Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SharedMemory-PT-000100-CTLFireability-00
FORMULA_NAME SharedMemory-PT-000100-CTLFireability-01
FORMULA_NAME SharedMemory-PT-000100-CTLFireability-02
FORMULA_NAME SharedMemory-PT-000100-CTLFireability-03
FORMULA_NAME SharedMemory-PT-000100-CTLFireability-04
FORMULA_NAME SharedMemory-PT-000100-CTLFireability-05
FORMULA_NAME SharedMemory-PT-000100-CTLFireability-06
FORMULA_NAME SharedMemory-PT-000100-CTLFireability-07
FORMULA_NAME SharedMemory-PT-000100-CTLFireability-08
FORMULA_NAME SharedMemory-PT-000100-CTLFireability-09
FORMULA_NAME SharedMemory-PT-000100-CTLFireability-10
FORMULA_NAME SharedMemory-PT-000100-CTLFireability-11
FORMULA_NAME SharedMemory-PT-000100-CTLFireability-12
FORMULA_NAME SharedMemory-PT-000100-CTLFireability-13
FORMULA_NAME SharedMemory-PT-000100-CTLFireability-14
FORMULA_NAME SharedMemory-PT-000100-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679280992530
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SharedMemory-PT-000100
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-20 02:56:35] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-20 02:56:35] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-20 02:56:36] [INFO ] Load time of PNML (sax parser for PT used): 863 ms
[2023-03-20 02:56:36] [INFO ] Transformed 10301 places.
[2023-03-20 02:56:36] [INFO ] Transformed 20100 transitions.
[2023-03-20 02:56:36] [INFO ] Found NUPN structural information;
[2023-03-20 02:56:36] [INFO ] Completing missing partition info from NUPN : creating a component with [Ext_Mem_Acc_57_1, Ext_Mem_Acc_56_1, Ext_Mem_Acc_19_2, Ext_Mem_Acc_18_2, Ext_Mem_Acc_72_2, Ext_Mem_Acc_63_2, Ext_Mem_Acc_11_3, Ext_Mem_Acc_12_3, Ext_Mem_Acc_64_3, Ext_Mem_Acc_61_3, Ext_Mem_Acc_49_4, Ext_Mem_Acc_48_4, Ext_Mem_Acc_12_5, Ext_Mem_Acc_17_5, Ext_Mem_Acc_22_5, Ext_Mem_Acc_21_5, Ext_Mem_Acc_95_5, Ext_Mem_Acc_98_5, Ext_Mem_Acc_28_6, Ext_Mem_Acc_29_6, Ext_Mem_Acc_41_7, Ext_Mem_Acc_80_6, Ext_Mem_Acc_2_8, Ext_Mem_Acc_99_7, Ext_Mem_Acc_47_8, Ext_Mem_Acc_46_8, Ext_Mem_Acc_23_9, Ext_Mem_Acc_26_9, Ext_Mem_Acc_84_8, Ext_Mem_Acc_85_8, Ext_Mem_Acc_39_9, Ext_Mem_Acc_40_9, Ext_Mem_Acc_28_10, Ext_Mem_Acc_29_10, Ext_Mem_Acc_3_11, Ext_Mem_Acc_2_11, Ext_Mem_Acc_99_11, Ext_Mem_Acc_100_11, Ext_Mem_Acc_42_11, Ext_Mem_Acc_43_11, Ext_Mem_Acc_95_11, Ext_Mem_Acc_94_11, Ext_Mem_Acc_73_13, Ext_Mem_Acc_72_13, Ext_Mem_Acc_91_12, Ext_Mem_Acc_92_12, Ext_Mem_Acc_71_14, Ext_Mem_Acc_68_14, Ext_Mem_Acc_22_14, Ext_Mem_Acc_21_14, Ext_Mem_Acc_25_14, Ext_Mem_Acc_26_14, Ext_Mem_Acc_43_16, Ext_Mem_Acc_44_16, Ext_Mem_Acc_69_15, Ext_Mem_Acc_70_15, Ext_Mem_Acc_71_17, Ext_Mem_Acc_78_17, Ext_Mem_Acc_90_16, Ext_Mem_Acc_91_16, Ext_Mem_Acc_73_16, Ext_Mem_Acc_72_16, Ext_Mem_Acc_59_18, Ext_Mem_Acc_58_18, Ext_Mem_Acc_86_17, Ext_Mem_Acc_85_17, Ext_Mem_Acc_19_20, Ext_Mem_Acc_21_20, Ext_Mem_Acc_64_19, Ext_Mem_Acc_63_19, Ext_Mem_Acc_8_19, Ext_Mem_Acc_9_19, Ext_Mem_Acc_3_21, Ext_Mem_Acc_2_21, Ext_Mem_Acc_54_20, Ext_Mem_Acc_55_20, Ext_Mem_Acc_99_22, Ext_Mem_Acc_98_22, Ext_Mem_Acc_79_23, Ext_Mem_Acc_80_23, Ext_Mem_Acc_86_21, Ext_Mem_Acc_85_21, Ext_Mem_Acc_3_22, Ext_Mem_Acc_4_22, Ext_Mem_Acc_93_22, Ext_Mem_Acc_92_22, Ext_Mem_Acc_75_25, Ext_Mem_Acc_76_25, Ext_Mem_Acc_48_26, Ext_Mem_Acc_49_26, Ext_Mem_Acc_30_24, Ext_Mem_Acc_31_24, Ext_Mem_Acc_85_24, Ext_Mem_Acc_84_24, Ext_Mem_Acc_33_25, Ext_Mem_Acc_34_25, Ext_Mem_Acc_43_28, Ext_Mem_Acc_44_28, Ext_Mem_Acc_25_29, Ext_Mem_Acc_24_29, Ext_Mem_Acc_48_27, Ext_Mem_Acc_47_27, Ext_Mem_Acc_92_26, Ext_Mem_Acc_93_26, Ext_Mem_Acc_49_27, Ext_Mem_Acc_50_27, Ext_Mem_Acc_83_30, Ext_Mem_Acc_82_30, Ext_Mem_Acc_85_31, Ext_Mem_Acc_86_31, Ext_Mem_Acc_83_29, Ext_Mem_Acc_84_29, Ext_Mem_Acc_40_30, Ext_Mem_Acc_41_30, Ext_Mem_Acc_31_30, Ext_Mem_Acc_29_30, Ext_Mem_Acc_58_34, Ext_Mem_Acc_59_34, Ext_Mem_Acc_41_33, Ext_Mem_Acc_44_33, Ext_Mem_Acc_85_32, Ext_Mem_Acc_84_32, Ext_Mem_Acc_28_32, Ext_Mem_Acc_27_32, Ext_Mem_Acc_46_32, Ext_Mem_Acc_47_32, Ext_Mem_Acc_98_36, Ext_Mem_Acc_1_37, Ext_Mem_Acc_20_36, Ext_Mem_Acc_17_36, Ext_Mem_Acc_56_35, Ext_Mem_Acc_55_35, Ext_Mem_Acc_74_34, Ext_Mem_Acc_75_34, Ext_Mem_Acc_9_35, Ext_Mem_Acc_8_35, Ext_Mem_Acc_41_39, Ext_Mem_Acc_42_39, Ext_Mem_Acc_68_38, Ext_Mem_Acc_69_38, Ext_Mem_Acc_29_38, Ext_Mem_Acc_30_38, Ext_Mem_Acc_74_37, Ext_Mem_Acc_73_37, Ext_Mem_Acc_18_37, Ext_Mem_Acc_19_37, Ext_Mem_Acc_89_41, Ext_Mem_Acc_90_41, Ext_Mem_Acc_9_41, Ext_Mem_Acc_8_41, Ext_Mem_Acc_91_40, Ext_Mem_Acc_90_40, Ext_Mem_Acc_9_40, Ext_Mem_Acc_10_40, Ext_Mem_Acc_42_45, Ext_Mem_Acc_43_45, Ext_Mem_Acc_94_44, Ext_Mem_Acc_1_45, Ext_Mem_Acc_76_45, Ext_Mem_Acc_89_45, Ext_Mem_Acc_59_46, Ext_Mem_Acc_60_46, Ext_Mem_Acc_38_47, Ext_Mem_Acc_32_47, Ext_Mem_Acc_68_42, Ext_Mem_Acc_75_42, Ext_Mem_Acc_59_42, Ext_Mem_Acc_60_42, Ext_Mem_Acc_14_43, Ext_Mem_Acc_9_43, Ext_Mem_Acc_17_44, Ext_Mem_Acc_73_43, Ext_Mem_Acc_90_44, Ext_Mem_Acc_89_44, Ext_Mem_Acc_28_50, Ext_Mem_Acc_41_50, Ext_Mem_Acc_58_50, Ext_Mem_Acc_53_50, Ext_Mem_Acc_39_51, Ext_Mem_Acc_9_51, Ext_Mem_Acc_3_52, Ext_Mem_Acc_98_51, Ext_Mem_Acc_18_52, Ext_Mem_Acc_7_52, Ext_Mem_Acc_67_47, Ext_Mem_Acc_62_47, Ext_Mem_Acc_10_48, Ext_Mem_Acc_18_48, Ext_Mem_Acc_66_48, Ext_Mem_Acc_67_48, Ext_Mem_Acc_22_49, Ext_Mem_Acc_23_49, Ext_Mem_Acc_66_49, Ext_Mem_Acc_65_49, Ext_Mem_Acc_43_56, Ext_Mem_Acc_44_56, Ext_Mem_Acc_87_55, Ext_Mem_Acc_88_55, Ext_Mem_Acc_42_55, Ext_Mem_Acc_41_55, Ext_Mem_Acc_53_57, Ext_Mem_Acc_52_57, Ext_Mem_Acc_2_57, Ext_Mem_Acc_3_57, Ext_Mem_Acc_97_53, Ext_Mem_Acc_98_53, Ext_Mem_Acc_17_53, Ext_Mem_Acc_16_53, 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[2023-03-20 02:56:36] [INFO ] Parsed PT model containing 10301 places and 20100 transitions and 80000 arcs in 1084 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 385 ms.
Support contains 10301 out of 10301 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 10301/10301 places, 20100/20100 transitions.
Applied a total of 0 rules in 95 ms. Remains 10301 /10301 variables (removed 0) and now considering 20100/20100 (removed 0) transitions.
// Phase 1: matrix 20100 rows 10301 cols
[2023-03-20 02:57:32] [INFO ] Computed 201 place invariants in 3555 ms
[2023-03-20 02:57:34] [INFO ] Implicit Places using invariants in 6378 ms returned []
Implicit Place search using SMT only with invariants took 6423 ms to find 0 implicit places.
[2023-03-20 02:57:34] [INFO ] Invariant cache hit.
[2023-03-20 02:57:37] [INFO ] Dead Transitions using invariants and state equation in 2426 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8954 ms. Remains : 10301/10301 places, 20100/20100 transitions.
Support contains 10301 out of 10301 places after structural reductions.
[2023-03-20 02:57:40] [INFO ] Flatten gal took : 1536 ms
[2023-03-20 02:57:48] [INFO ] Flatten gal took : 1614 ms
[2023-03-20 02:57:56] [INFO ] Input system was already deterministic with 20100 transitions.
Interrupted random walk after 5249 steps, including 1 resets, run timeout after 30001 ms. (steps per millisecond=0 ) properties seen 43
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 19) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 19) seen :0
Running SMT prover for 19 properties.
[2023-03-20 02:58:27] [INFO ] Invariant cache hit.
[2023-03-20 02:58:35] [INFO ] [Real]Absence check using 201 positive place invariants in 682 ms returned sat
[2023-03-20 02:58:38] [INFO ] After 10380ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:18
[2023-03-20 02:58:45] [INFO ] [Nat]Absence check using 201 positive place invariants in 987 ms returned sat
[2023-03-20 02:59:03] [INFO ] After 14662ms SMT Verify possible using state equation in natural domain returned unsat :2 sat :13
[2023-03-20 02:59:03] [INFO ] After 14709ms SMT Verify possible using trap constraints in natural domain returned unsat :2 sat :13
Attempting to minimize the solution found.
Minimization took 7 ms.
[2023-03-20 02:59:03] [INFO ] After 25071ms SMT Verify possible using all constraints in natural domain returned unsat :2 sat :13
Fused 19 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 1 ms.
Support contains 19 out of 10301 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 10301/10301 places, 20100/20100 transitions.
Drop transitions removed 9881 transitions
Trivial Post-agglo rules discarded 9881 transitions
Performed 9881 trivial Post agglomeration. Transition count delta: 9881
Iterating post reduction 0 with 9881 rules applied. Total rules applied 9881 place count 10301 transition count 10219
Discarding 249 places :
Also discarding 235 output transitions
Drop transitions removed 235 transitions
Remove reverse transitions (loop back) rule discarded transition t18460 and 249 places that fell out of Prefix Of Interest.
Drop transitions removed 8231 transitions
Ensure Unique test removed 1364 transitions
Reduce isomorphic transitions removed 9595 transitions.
Graph (trivial) has 47 edges and 89 vertex of which 26 / 89 are part of one of the 13 SCC in 4 ms
Free SCC test removed 13 places
Iterating post reduction 1 with 9597 rules applied. Total rules applied 19478 place count 76 transition count 389
Drop transitions removed 26 transitions
Reduce isomorphic transitions removed 26 transitions.
Iterating post reduction 2 with 26 rules applied. Total rules applied 19504 place count 76 transition count 363
Performed 13 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 13 Pre rules applied. Total rules applied 19504 place count 76 transition count 350
Deduced a syphon composed of 13 places in 1 ms
Reduce places removed 13 places and 0 transitions.
Iterating global reduction 3 with 26 rules applied. Total rules applied 19530 place count 63 transition count 350
Drop transitions removed 233 transitions
Reduce isomorphic transitions removed 233 transitions.
Iterating post reduction 3 with 233 rules applied. Total rules applied 19763 place count 63 transition count 117
Drop transitions removed 63 transitions
Redundant transition composition rules discarded 63 transitions
Iterating global reduction 4 with 63 rules applied. Total rules applied 19826 place count 63 transition count 54
Ensure Unique test removed 8 places
Iterating post reduction 4 with 8 rules applied. Total rules applied 19834 place count 55 transition count 54
Free-agglomeration rule applied 8 times.
Iterating global reduction 5 with 8 rules applied. Total rules applied 19842 place count 55 transition count 46
Reduce places removed 8 places and 0 transitions.
Drop transitions removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 5 with 16 rules applied. Total rules applied 19858 place count 47 transition count 38
Ensure Unique test removed 6 places
Iterating post reduction 6 with 6 rules applied. Total rules applied 19864 place count 41 transition count 38
Applied a total of 19864 rules in 545 ms. Remains 41 /10301 variables (removed 10260) and now considering 38/20100 (removed 20062) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 545 ms. Remains : 41/10301 places, 38/20100 transitions.
Finished random walk after 133 steps, including 0 resets, run visited all 17 properties in 10 ms. (steps per millisecond=13 )
Successfully simplified 2 atomic propositions for a total of 16 simplifications.
[2023-03-20 02:59:19] [INFO ] Flatten gal took : 1233 ms
[2023-03-20 02:59:28] [INFO ] Flatten gal took : 1571 ms
[2023-03-20 02:59:36] [INFO ] Input system was already deterministic with 20100 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 10301/10301 places, 20100/20100 transitions.
Applied a total of 0 rules in 41 ms. Remains 10301 /10301 variables (removed 0) and now considering 20100/20100 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 50 ms. Remains : 10301/10301 places, 20100/20100 transitions.
[2023-03-20 02:59:49] [INFO ] Flatten gal took : 682 ms
[2023-03-20 02:59:50] [INFO ] Flatten gal took : 797 ms
[2023-03-20 02:59:51] [INFO ] Input system was already deterministic with 20100 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 10301/10301 places, 20100/20100 transitions.
Applied a total of 0 rules in 4953 ms. Remains 10301 /10301 variables (removed 0) and now considering 20100/20100 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4955 ms. Remains : 10301/10301 places, 20100/20100 transitions.
[2023-03-20 02:59:57] [INFO ] Flatten gal took : 652 ms
[2023-03-20 02:59:58] [INFO ] Flatten gal took : 767 ms
[2023-03-20 03:00:00] [INFO ] Input system was already deterministic with 20100 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 10301/10301 places, 20100/20100 transitions.
Applied a total of 0 rules in 5174 ms. Remains 10301 /10301 variables (removed 0) and now considering 20100/20100 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5177 ms. Remains : 10301/10301 places, 20100/20100 transitions.
[2023-03-20 03:00:06] [INFO ] Flatten gal took : 641 ms
[2023-03-20 03:00:06] [INFO ] Flatten gal took : 681 ms
[2023-03-20 03:00:07] [INFO ] Input system was already deterministic with 20100 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 10301/10301 places, 20100/20100 transitions.
Applied a total of 0 rules in 4316 ms. Remains 10301 /10301 variables (removed 0) and now considering 20100/20100 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4321 ms. Remains : 10301/10301 places, 20100/20100 transitions.
[2023-03-20 03:00:13] [INFO ] Flatten gal took : 624 ms
[2023-03-20 03:00:14] [INFO ] Flatten gal took : 742 ms
[2023-03-20 03:00:15] [INFO ] Input system was already deterministic with 20100 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 10301/10301 places, 20100/20100 transitions.
Applied a total of 0 rules in 131 ms. Remains 10301 /10301 variables (removed 0) and now considering 20100/20100 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 133 ms. Remains : 10301/10301 places, 20100/20100 transitions.
[2023-03-20 03:00:16] [INFO ] Flatten gal took : 565 ms
[2023-03-20 03:00:17] [INFO ] Flatten gal took : 637 ms
[2023-03-20 03:00:18] [INFO ] Input system was already deterministic with 20100 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 10301/10301 places, 20100/20100 transitions.
Applied a total of 0 rules in 132 ms. Remains 10301 /10301 variables (removed 0) and now considering 20100/20100 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 133 ms. Remains : 10301/10301 places, 20100/20100 transitions.
[2023-03-20 03:00:19] [INFO ] Flatten gal took : 582 ms
[2023-03-20 03:00:19] [INFO ] Flatten gal took : 678 ms
[2023-03-20 03:00:21] [INFO ] Input system was already deterministic with 20100 transitions.
Starting structural reductions in LTL mode, iteration 0 : 10301/10301 places, 20100/20100 transitions.
Applied a total of 0 rules in 41 ms. Remains 10301 /10301 variables (removed 0) and now considering 20100/20100 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 43 ms. Remains : 10301/10301 places, 20100/20100 transitions.
[2023-03-20 03:00:21] [INFO ] Flatten gal took : 598 ms
[2023-03-20 03:00:22] [INFO ] Flatten gal took : 824 ms
[2023-03-20 03:00:24] [INFO ] Input system was already deterministic with 20100 transitions.
Starting structural reductions in LTL mode, iteration 0 : 10301/10301 places, 20100/20100 transitions.
Applied a total of 0 rules in 28 ms. Remains 10301 /10301 variables (removed 0) and now considering 20100/20100 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 10301/10301 places, 20100/20100 transitions.
[2023-03-20 03:00:31] [INFO ] Flatten gal took : 777 ms
[2023-03-20 03:00:32] [INFO ] Flatten gal took : 1004 ms
[2023-03-20 03:00:34] [INFO ] Input system was already deterministic with 20100 transitions.
Starting structural reductions in LTL mode, iteration 0 : 10301/10301 places, 20100/20100 transitions.
Applied a total of 0 rules in 3537 ms. Remains 10301 /10301 variables (removed 0) and now considering 20100/20100 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3543 ms. Remains : 10301/10301 places, 20100/20100 transitions.
[2023-03-20 03:00:39] [INFO ] Flatten gal took : 675 ms
[2023-03-20 03:00:40] [INFO ] Flatten gal took : 859 ms
[2023-03-20 03:00:41] [INFO ] Input system was already deterministic with 20100 transitions.
Starting structural reductions in LTL mode, iteration 0 : 10301/10301 places, 20100/20100 transitions.
Applied a total of 0 rules in 3718 ms. Remains 10301 /10301 variables (removed 0) and now considering 20100/20100 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3723 ms. Remains : 10301/10301 places, 20100/20100 transitions.
[2023-03-20 03:00:45] [INFO ] Flatten gal took : 544 ms
[2023-03-20 03:00:46] [INFO ] Flatten gal took : 601 ms
[2023-03-20 03:00:47] [INFO ] Input system was already deterministic with 20100 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 10301/10301 places, 20100/20100 transitions.
Drop transitions removed 9801 transitions
Trivial Post-agglo rules discarded 9801 transitions
Performed 9801 trivial Post agglomeration. Transition count delta: 9801
Iterating post reduction 0 with 9801 rules applied. Total rules applied 9801 place count 10301 transition count 10299
Reduce places removed 9802 places and 0 transitions.
Iterating post reduction 1 with 9802 rules applied. Total rules applied 19603 place count 499 transition count 10299
Drop transitions removed 9702 transitions
Redundant transition composition rules discarded 9702 transitions
Iterating global reduction 2 with 9702 rules applied. Total rules applied 29305 place count 499 transition count 597
Applied a total of 29305 rules in 1237 ms. Remains 499 /10301 variables (removed 9802) and now considering 597/20100 (removed 19503) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1237 ms. Remains : 499/10301 places, 597/20100 transitions.
[2023-03-20 03:00:49] [INFO ] Flatten gal took : 12 ms
[2023-03-20 03:00:49] [INFO ] Flatten gal took : 13 ms
[2023-03-20 03:00:49] [INFO ] Input system was already deterministic with 597 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 10301/10301 places, 20100/20100 transitions.
Drop transitions removed 9899 transitions
Trivial Post-agglo rules discarded 9899 transitions
Performed 9899 trivial Post agglomeration. Transition count delta: 9899
Iterating post reduction 0 with 9899 rules applied. Total rules applied 9899 place count 10301 transition count 10201
Reduce places removed 9998 places and 0 transitions.
Ensure Unique test removed 9701 transitions
Reduce isomorphic transitions removed 9701 transitions.
Graph (trivial) has 299 edges and 303 vertex of which 198 / 303 are part of one of the 99 SCC in 0 ms
Free SCC test removed 99 places
Iterating post reduction 1 with 19700 rules applied. Total rules applied 29599 place count 204 transition count 500
Ensure Unique test removed 99 transitions
Reduce isomorphic transitions removed 99 transitions.
Iterating post reduction 2 with 99 rules applied. Total rules applied 29698 place count 204 transition count 401
Drop transitions removed 98 transitions
Redundant transition composition rules discarded 98 transitions
Iterating global reduction 3 with 98 rules applied. Total rules applied 29796 place count 204 transition count 303
Applied a total of 29796 rules in 332 ms. Remains 204 /10301 variables (removed 10097) and now considering 303/20100 (removed 19797) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 332 ms. Remains : 204/10301 places, 303/20100 transitions.
[2023-03-20 03:00:49] [INFO ] Flatten gal took : 4 ms
[2023-03-20 03:00:49] [INFO ] Flatten gal took : 4 ms
[2023-03-20 03:00:49] [INFO ] Input system was already deterministic with 303 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 10301/10301 places, 20100/20100 transitions.
Applied a total of 0 rules in 4114 ms. Remains 10301 /10301 variables (removed 0) and now considering 20100/20100 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4118 ms. Remains : 10301/10301 places, 20100/20100 transitions.
[2023-03-20 03:00:54] [INFO ] Flatten gal took : 555 ms
[2023-03-20 03:00:54] [INFO ] Flatten gal took : 605 ms
[2023-03-20 03:00:56] [INFO ] Input system was already deterministic with 20100 transitions.
Starting structural reductions in LTL mode, iteration 0 : 10301/10301 places, 20100/20100 transitions.
Applied a total of 0 rules in 3578 ms. Remains 10301 /10301 variables (removed 0) and now considering 20100/20100 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3579 ms. Remains : 10301/10301 places, 20100/20100 transitions.
[2023-03-20 03:01:00] [INFO ] Flatten gal took : 546 ms
[2023-03-20 03:01:00] [INFO ] Flatten gal took : 605 ms
[2023-03-20 03:01:01] [INFO ] Input system was already deterministic with 20100 transitions.
Starting structural reductions in LTL mode, iteration 0 : 10301/10301 places, 20100/20100 transitions.
Applied a total of 0 rules in 3736 ms. Remains 10301 /10301 variables (removed 0) and now considering 20100/20100 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3736 ms. Remains : 10301/10301 places, 20100/20100 transitions.
[2023-03-20 03:01:06] [INFO ] Flatten gal took : 547 ms
[2023-03-20 03:01:06] [INFO ] Flatten gal took : 606 ms
[2023-03-20 03:01:08] [INFO ] Input system was already deterministic with 20100 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 10301/10301 places, 20100/20100 transitions.
Applied a total of 0 rules in 3894 ms. Remains 10301 /10301 variables (removed 0) and now considering 20100/20100 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3895 ms. Remains : 10301/10301 places, 20100/20100 transitions.
[2023-03-20 03:01:12] [INFO ] Flatten gal took : 771 ms
[2023-03-20 03:01:13] [INFO ] Flatten gal took : 615 ms
[2023-03-20 03:01:14] [INFO ] Input system was already deterministic with 20100 transitions.
[2023-03-20 03:01:16] [INFO ] Flatten gal took : 1411 ms
[2023-03-20 03:01:24] [INFO ] Flatten gal took : 1451 ms
[2023-03-20 03:01:31] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 468 ms.
[2023-03-20 03:01:31] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 10301 places, 20100 transitions and 80000 arcs took 86 ms.
Total runtime 296532 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SharedMemory-PT-000100
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 154276 kB
After kill :
MemTotal: 16393216 kB
MemFree: 10583608 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: caught signal Terminated - aborting LoLA
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Time elapsed: 3299 secs. Pages in use: 0
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SharedMemory-PT-000100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SharedMemory-PT-000100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891809400690"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SharedMemory-PT-000100.tgz
mv SharedMemory-PT-000100 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;