Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r359-smll-167891808800322.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is SatelliteMemory-PT-X03000Y0094, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-167891808800322
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 484K
-rw-r--r-- 1 mcc users 6.5K Feb 26 12:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 67K Feb 26 12:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K Feb 26 12:50 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 12:50 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.2K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:50 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:50 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:50 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:50 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 13:02 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 153K Feb 26 13:02 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Feb 26 13:00 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 70K Feb 26 13:00 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:50 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:50 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 12 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rwxr-xr-x 1 mcc users 5.5K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-CTLFireability-00
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-CTLFireability-01
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-CTLFireability-02
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-CTLFireability-03
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-CTLFireability-04
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-CTLFireability-05
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-CTLFireability-06
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-CTLFireability-07
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-CTLFireability-08
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-CTLFireability-09
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-CTLFireability-10
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-CTLFireability-11
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-CTLFireability-12
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-CTLFireability-13
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-CTLFireability-14
FORMULA_NAME SatelliteMemory-PT-X03000Y0094-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679071024921

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SatelliteMemory-PT-X03000Y0094
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-17 16:37:08] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 16:37:08] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 16:37:08] [INFO ] Load time of PNML (sax parser for PT used): 76 ms
[2023-03-17 16:37:08] [INFO ] Transformed 13 places.
[2023-03-17 16:37:08] [INFO ] Transformed 10 transitions.
[2023-03-17 16:37:08] [INFO ] Parsed PT model containing 13 places and 10 transitions and 40 arcs in 281 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 25 ms.
Reduce places removed 1 places and 0 transitions.
Support contains 12 out of 12 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 23 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
// Phase 1: matrix 10 rows 12 cols
[2023-03-17 16:37:08] [INFO ] Computed 6 place invariants in 6 ms
[2023-03-17 16:37:09] [INFO ] Dead Transitions using invariants and state equation in 317 ms found 0 transitions.
[2023-03-17 16:37:09] [INFO ] Invariant cache hit.
[2023-03-17 16:37:09] [INFO ] Implicit Places using invariants in 42 ms returned []
[2023-03-17 16:37:09] [INFO ] Invariant cache hit.
[2023-03-17 16:37:09] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-17 16:37:09] [INFO ] Implicit Places using invariants and state equation in 61 ms returned []
Implicit Place search using SMT with State Equation took 106 ms to find 0 implicit places.
[2023-03-17 16:37:09] [INFO ] Invariant cache hit.
[2023-03-17 16:37:09] [INFO ] Dead Transitions using invariants and state equation in 39 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 560 ms. Remains : 12/12 places, 10/10 transitions.
Support contains 12 out of 12 places after structural reductions.
[2023-03-17 16:37:09] [INFO ] Flatten gal took : 33 ms
[2023-03-17 16:37:09] [INFO ] Flatten gal took : 14 ms
[2023-03-17 16:37:09] [INFO ] Input system was already deterministic with 10 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1048 ms. (steps per millisecond=9 ) properties (out of 29) seen :21
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 131 ms. (steps per millisecond=76 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 68 ms. (steps per millisecond=147 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 70 ms. (steps per millisecond=142 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 77 ms. (steps per millisecond=129 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 68 ms. (steps per millisecond=147 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 8) seen :0
Running SMT prover for 8 properties.
[2023-03-17 16:37:11] [INFO ] Invariant cache hit.
[2023-03-17 16:37:11] [INFO ] [Real]Absence check using 6 positive place invariants in 4 ms returned sat
[2023-03-17 16:37:11] [INFO ] After 179ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:7
[2023-03-17 16:37:11] [INFO ] [Nat]Absence check using 6 positive place invariants in 2 ms returned sat
[2023-03-17 16:37:11] [INFO ] After 60ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :7
[2023-03-17 16:37:11] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-17 16:37:11] [INFO ] After 39ms SMT Verify possible using 1 Read/Feed constraints in natural domain returned unsat :1 sat :7
[2023-03-17 16:37:11] [INFO ] After 179ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :7
Attempting to minimize the solution found.
Minimization took 38 ms.
[2023-03-17 16:37:11] [INFO ] After 348ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :7
Fused 8 Parikh solutions to 7 different solutions.
Finished Parikh walk after 6002 steps, including 0 resets, run visited all 1 properties in 17 ms. (steps per millisecond=353 )
Parikh walk visited 7 properties in 601 ms.
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 5 ms
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 4 ms
[2023-03-17 16:37:12] [INFO ] Input system was already deterministic with 10 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:37:12] [INFO ] Invariant cache hit.
[2023-03-17 16:37:12] [INFO ] Dead Transitions using invariants and state equation in 53 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 56 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:37:12] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:37:12] [INFO ] Invariant cache hit.
[2023-03-17 16:37:12] [INFO ] Dead Transitions using invariants and state equation in 28 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 29 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:37:12] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 3 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:37:12] [INFO ] Invariant cache hit.
[2023-03-17 16:37:12] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 32 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:37:12] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:37:12] [INFO ] Invariant cache hit.
[2023-03-17 16:37:12] [INFO ] Dead Transitions using invariants and state equation in 38 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 42 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 8 ms
[2023-03-17 16:37:12] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:37:12] [INFO ] Invariant cache hit.
[2023-03-17 16:37:12] [INFO ] Dead Transitions using invariants and state equation in 40 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 42 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 3 ms
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 4 ms
[2023-03-17 16:37:12] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:37:12] [INFO ] Invariant cache hit.
[2023-03-17 16:37:12] [INFO ] Dead Transitions using invariants and state equation in 29 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 31 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:37:12] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:37:12] [INFO ] Invariant cache hit.
[2023-03-17 16:37:12] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 29 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:37:12] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:37:12] [INFO ] Invariant cache hit.
[2023-03-17 16:37:12] [INFO ] Dead Transitions using invariants and state equation in 43 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 45 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 7 ms
[2023-03-17 16:37:12] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:37:12] [INFO ] Invariant cache hit.
[2023-03-17 16:37:12] [INFO ] Dead Transitions using invariants and state equation in 33 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 34 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:37:12] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:37:12] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:37:12] [INFO ] Invariant cache hit.
[2023-03-17 16:37:12] [INFO ] Dead Transitions using invariants and state equation in 30 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 30 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:37:13] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:37:13] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:37:13] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:37:13] [INFO ] Invariant cache hit.
[2023-03-17 16:37:13] [INFO ] Dead Transitions using invariants and state equation in 36 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 38 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:37:13] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:37:13] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:37:13] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:37:13] [INFO ] Invariant cache hit.
[2023-03-17 16:37:13] [INFO ] Dead Transitions using invariants and state equation in 30 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 32 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:37:13] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:37:13] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:37:13] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:37:13] [INFO ] Invariant cache hit.
[2023-03-17 16:37:13] [INFO ] Dead Transitions using invariants and state equation in 30 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 32 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:37:13] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:37:13] [INFO ] Flatten gal took : 15 ms
[2023-03-17 16:37:13] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:37:13] [INFO ] Invariant cache hit.
[2023-03-17 16:37:13] [INFO ] Dead Transitions using invariants and state equation in 136 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 141 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:37:13] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:37:13] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:37:13] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:37:13] [INFO ] Invariant cache hit.
[2023-03-17 16:37:13] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 29 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:37:13] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:37:13] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:37:13] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 10/10 transitions.
Applied a total of 0 rules in 2 ms. Remains 12 /12 variables (removed 0) and now considering 10/10 (removed 0) transitions.
[2023-03-17 16:37:13] [INFO ] Invariant cache hit.
[2023-03-17 16:37:13] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 12/12 places, 10/10 transitions.
[2023-03-17 16:37:13] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:37:13] [INFO ] Flatten gal took : 1 ms
[2023-03-17 16:37:13] [INFO ] Input system was already deterministic with 10 transitions.
[2023-03-17 16:37:13] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:37:13] [INFO ] Flatten gal took : 2 ms
[2023-03-17 16:37:13] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 8 ms.
[2023-03-17 16:37:13] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 12 places, 10 transitions and 38 arcs took 0 ms.
Total runtime 5290 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT SatelliteMemory-PT-X03000Y0094
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA SatelliteMemory-PT-X03000Y0094-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X03000Y0094-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X03000Y0094-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679071315416

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
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lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 10 (type EXCL) for 9 SatelliteMemory-PT-X03000Y0094-CTLFireability-03
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 10 (type EXCL) for SatelliteMemory-PT-X03000Y0094-CTLFireability-03
lola: result : false
lola: markings : 11249
lola: fired transitions : 11249
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 50 (type EXCL) for 45 SatelliteMemory-PT-X03000Y0094-CTLFireability-15
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for SatelliteMemory-PT-X03000Y0094-CTLFireability-15
lola: result : true
lola: markings : 23998
lola: fired transitions : 35995
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 42 SatelliteMemory-PT-X03000Y0094-CTLFireability-14
lola: time limit : 257 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X03000Y0094-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 5/257 20/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-14 4655066 m, 931013 m/sec, 4663684 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SatelliteMemory-PT-X03000Y0094-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X03000Y0094-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/276 12/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-13 2669006 m, 533801 m/sec, 4331954 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X03000Y0094-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 10/276 23/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-13 5318816 m, 529962 m/sec, 8639314 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X03000Y0094-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
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34 CTL EXCL 5/297 3/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-11 575772 m, 115154 m/sec, 3235533 t fired, .

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34 CTL EXCL 10/297 5/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-11 1167550 m, 118355 m/sec, 6562305 t fired, .

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34 CTL EXCL 15/297 8/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-11 1858396 m, 138169 m/sec, 10448283 t fired, .

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34 CTL EXCL 20/297 11/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-11 2592742 m, 146869 m/sec, 14580474 t fired, .

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34 CTL EXCL 25/297 14/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-11 3316964 m, 144844 m/sec, 18653677 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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34 CTL EXCL 30/297 17/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-11 4035166 m, 143640 m/sec, 22693645 t fired, .

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34 CTL EXCL 35/297 20/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-11 4742009 m, 141368 m/sec, 26668304 t fired, .

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34 CTL EXCL 40/297 23/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-11 5445190 m, 140636 m/sec, 30622517 t fired, .

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34 CTL EXCL 45/297 26/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-11 6140010 m, 138964 m/sec, 34532445 t fired, .

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34 CTL EXCL 50/297 29/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-11 6848788 m, 141755 m/sec, 38517734 t fired, .

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34 CTL EXCL 55/297 32/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-11 7532210 m, 136684 m/sec, 42363237 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/319 12/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-10 2632151 m, 526430 m/sec, 6906261 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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31 CTL EXCL 10/319 22/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-10 5082817 m, 490133 m/sec, 13340383 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 15/319 32/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-10 7401370 m, 463710 m/sec, 19427349 t fired, .

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28 CTL EXCL 5/349 11/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-09 2616566 m, 523313 m/sec, 4246292 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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28 CTL EXCL 10/349 21/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-09 4929820 m, 462650 m/sec, 8006544 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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28 CTL EXCL 15/349 31/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-09 7185558 m, 451147 m/sec, 11672252 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

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SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
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25 CTL EXCL 5/386 11/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-08 2561155 m, 512231 m/sec, 6721258 t fired, .

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25 CTL EXCL 10/386 20/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-08 4726571 m, 433083 m/sec, 12405116 t fired, .

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25 CTL EXCL 15/386 29/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-08 6773333 m, 409352 m/sec, 17780319 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/431 19/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-06 4321498 m, 864299 m/sec, 7019748 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

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SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/492 19/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-05 4387573 m, 877514 m/sec, 7672252 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SatelliteMemory-PT-X03000Y0094-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/572 24/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-04 5485208 m, 1097041 m/sec, 5489769 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SatelliteMemory-PT-X03000Y0094-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SatelliteMemory-PT-X03000Y0094-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/685 11/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-01 2459069 m, 491813 m/sec, 6451794 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SatelliteMemory-PT-X03000Y0094-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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4 CTL EXCL 10/685 20/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-01 4739698 m, 456125 m/sec, 12438990 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SatelliteMemory-PT-X03000Y0094-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/685 30/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-01 6996549 m, 451370 m/sec, 18364198 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SatelliteMemory-PT-X03000Y0094-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: time limit : 851 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/851 16/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-00 3693027 m, 738605 m/sec, 5990711 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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1 CTL EXCL 10/851 29/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-00 6744002 m, 610195 m/sec, 10950045 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SatelliteMemory-PT-X03000Y0094-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

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SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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7 CTL EXCL 5/1130 4/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-02 861150 m, 172230 m/sec, 5050315 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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7 CTL EXCL 10/1130 8/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-02 1702929 m, 168355 m/sec, 9995834 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/1130 11/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-02 2495588 m, 158531 m/sec, 14652771 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

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SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/1130 15/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-02 3463313 m, 193545 m/sec, 20338229 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/1130 19/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-02 4429014 m, 193140 m/sec, 26011800 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/1130 23/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-02 5384399 m, 191077 m/sec, 31624759 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

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SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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7 CTL EXCL 35/1130 27/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-02 6290185 m, 181157 m/sec, 36946323 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

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SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 40/1130 31/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-02 7239668 m, 189896 m/sec, 42524607 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

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SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: result : false
lola: markings : 24760
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-07: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

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SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 5/3345 9/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-12 1916440 m, 383288 m/sec, 7663302 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
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SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

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SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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37 CTL EXCL 10/3345 15/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-12 3564486 m, 329609 m/sec, 14255951 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

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SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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37 CTL EXCL 15/3345 22/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-12 5181576 m, 323418 m/sec, 20724776 t fired, .

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SatelliteMemory-PT-X03000Y0094-CTLFireability-07: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X03000Y0094-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 20/3345 29/32 SatelliteMemory-PT-X03000Y0094-CTLFireability-12 6782940 m, 320272 m/sec, 27130688 t fired, .

Time elapsed: 275 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 37 (type EXCL) for SatelliteMemory-PT-X03000Y0094-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-07: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X03000Y0094-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 280 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X03000Y0094-CTLFireability-00: CTL unknown AGGR
SatelliteMemory-PT-X03000Y0094-CTLFireability-01: CTL unknown AGGR
SatelliteMemory-PT-X03000Y0094-CTLFireability-02: CTL unknown AGGR
SatelliteMemory-PT-X03000Y0094-CTLFireability-03: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-04: CTL unknown AGGR
SatelliteMemory-PT-X03000Y0094-CTLFireability-05: CTL unknown AGGR
SatelliteMemory-PT-X03000Y0094-CTLFireability-06: CTL unknown AGGR
SatelliteMemory-PT-X03000Y0094-CTLFireability-07: CTL false CTL model checker
SatelliteMemory-PT-X03000Y0094-CTLFireability-08: CTL unknown AGGR
SatelliteMemory-PT-X03000Y0094-CTLFireability-09: CTL unknown AGGR
SatelliteMemory-PT-X03000Y0094-CTLFireability-10: CTL unknown AGGR
SatelliteMemory-PT-X03000Y0094-CTLFireability-11: CTL unknown AGGR
SatelliteMemory-PT-X03000Y0094-CTLFireability-12: CTL unknown AGGR
SatelliteMemory-PT-X03000Y0094-CTLFireability-13: CTL unknown AGGR
SatelliteMemory-PT-X03000Y0094-CTLFireability-14: CTL unknown AGGR
SatelliteMemory-PT-X03000Y0094-CTLFireability-15: DISJ true CTL model checker


Time elapsed: 280 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SatelliteMemory-PT-X03000Y0094"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is SatelliteMemory-PT-X03000Y0094, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891808800322"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SatelliteMemory-PT-X03000Y0094.tgz
mv SatelliteMemory-PT-X03000Y0094 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;