fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r359-smll-167891808500159
Last Updated
May 14, 2023

About the Execution of LoLa+red for RwMutex-PT-r0010w2000

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
3243.548 325229.00 492500.00 942.20 FTFTTFTFFFTFFFTF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r359-smll-167891808500159.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RwMutex-PT-r0010w2000, examination is ReachabilityFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-167891808500159
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.1M
-rw-r--r-- 1 mcc users 5.8K Feb 25 23:47 CTLCardinality.txt
-rw-r--r-- 1 mcc users 56K Feb 25 23:47 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K Feb 25 23:00 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K Feb 25 23:00 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:48 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:48 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:48 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:48 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 01:18 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 143K Feb 26 01:18 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.3K Feb 26 00:39 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 80K Feb 26 00:39 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:48 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:48 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 11 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 3.6M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RwMutex-PT-r0010w2000-ReachabilityFireability-00
FORMULA_NAME RwMutex-PT-r0010w2000-ReachabilityFireability-01
FORMULA_NAME RwMutex-PT-r0010w2000-ReachabilityFireability-02
FORMULA_NAME RwMutex-PT-r0010w2000-ReachabilityFireability-03
FORMULA_NAME RwMutex-PT-r0010w2000-ReachabilityFireability-04
FORMULA_NAME RwMutex-PT-r0010w2000-ReachabilityFireability-05
FORMULA_NAME RwMutex-PT-r0010w2000-ReachabilityFireability-06
FORMULA_NAME RwMutex-PT-r0010w2000-ReachabilityFireability-07
FORMULA_NAME RwMutex-PT-r0010w2000-ReachabilityFireability-08
FORMULA_NAME RwMutex-PT-r0010w2000-ReachabilityFireability-09
FORMULA_NAME RwMutex-PT-r0010w2000-ReachabilityFireability-10
FORMULA_NAME RwMutex-PT-r0010w2000-ReachabilityFireability-11
FORMULA_NAME RwMutex-PT-r0010w2000-ReachabilityFireability-12
FORMULA_NAME RwMutex-PT-r0010w2000-ReachabilityFireability-13
FORMULA_NAME RwMutex-PT-r0010w2000-ReachabilityFireability-14
FORMULA_NAME RwMutex-PT-r0010w2000-ReachabilityFireability-15

=== Now, execution of the tool begins

BK_START 1678998814417

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=ReachabilityFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RwMutex-PT-r0010w2000
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 20:33:36] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityFireability, -timeout, 360, -rebuildPNML]
[2023-03-16 20:33:37] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 20:33:37] [INFO ] Load time of PNML (sax parser for PT used): 774 ms
[2023-03-16 20:33:37] [INFO ] Transformed 4030 places.
[2023-03-16 20:33:38] [INFO ] Transformed 4020 transitions.
[2023-03-16 20:33:38] [INFO ] Found NUPN structural information;
[2023-03-16 20:33:38] [INFO ] Parsed PT model containing 4030 places and 4020 transitions and 48060 arcs in 1010 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityFireability.xml in 21 ms.
Working with output stream class java.io.PrintStream
Initial state reduction rules removed 7 formulas.
FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-10 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-13 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10000 steps, including 2 resets, run finished after 5292 ms. (steps per millisecond=1 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 491 ms. (steps per millisecond=20 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 521 ms. (steps per millisecond=19 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 447 ms. (steps per millisecond=22 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 441 ms. (steps per millisecond=22 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 399 ms. (steps per millisecond=25 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 424 ms. (steps per millisecond=23 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 433 ms. (steps per millisecond=23 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 624 ms. (steps per millisecond=16 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 724 ms. (steps per millisecond=13 ) properties (out of 9) seen :0
Probably explored full state space saw : 3024 states, properties seen :0
Probabilistic random walk after 17264 steps, saw 3024 distinct states, run finished after 1858 ms. (steps per millisecond=9 ) properties seen :0
Explored full state space saw : 3024 states, properties seen :0
Exhaustive walk after 17264 steps, saw 3024 distinct states, run finished after 1721 ms. (steps per millisecond=10 ) properties seen :0
FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-15 FALSE TECHNIQUES TOPOLOGICAL EXHAUSTIVE_WALK
FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-07 FALSE TECHNIQUES TOPOLOGICAL EXHAUSTIVE_WALK
FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-06 TRUE TECHNIQUES TOPOLOGICAL EXHAUSTIVE_WALK
FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-05 FALSE TECHNIQUES TOPOLOGICAL EXHAUSTIVE_WALK
FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-04 TRUE TECHNIQUES TOPOLOGICAL EXHAUSTIVE_WALK
FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-03 TRUE TECHNIQUES TOPOLOGICAL EXHAUSTIVE_WALK
FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-02 FALSE TECHNIQUES TOPOLOGICAL EXHAUSTIVE_WALK
FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-01 TRUE TECHNIQUES TOPOLOGICAL EXHAUSTIVE_WALK
FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-00 FALSE TECHNIQUES TOPOLOGICAL EXHAUSTIVE_WALK
All properties solved without resorting to model-checking.
Total runtime 14761 ms.
starting LoLA
BK_INPUT RwMutex-PT-r0010w2000
BK_EXAMINATION: ReachabilityFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityFireability

FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-ReachabilityFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678999139646

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 50 (type SKEL/FNDP) for 18 RwMutex-PT-r0010w2000-ReachabilityFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type SKEL/EQUN) for 18 RwMutex-PT-r0010w2000-ReachabilityFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 53 (type SKEL/SRCH) for 18 RwMutex-PT-r0010w2000-ReachabilityFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type SKEL/SRCH) for 18 RwMutex-PT-r0010w2000-ReachabilityFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 53 (type SKEL/SRCH) for RwMutex-PT-r0010w2000-ReachabilityFireability-06
lola: result : false
lola: markings : 6
lola: fired transitions : 10
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 50 (type FNDP) for RwMutex-PT-r0010w2000-ReachabilityFireability-06 (obsolete)
lola: CANCELED task # 51 (type EQUN) for RwMutex-PT-r0010w2000-ReachabilityFireability-06 (obsolete)
lola: CANCELED task # 54 (type SRCH) for RwMutex-PT-r0010w2000-ReachabilityFireability-06 (obsolete)
lola: FINISHED task # 50 (type SKEL/FNDP) for RwMutex-PT-r0010w2000-ReachabilityFireability-06
lola: result : unknown
lola: fired transitions : 71588
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-51.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 51 (type SKEL/EQUN) for RwMutex-PT-r0010w2000-ReachabilityFireability-06
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 58 (type SKEL/FNDP) for 12 RwMutex-PT-r0010w2000-ReachabilityFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type SKEL/EQUN) for 12 RwMutex-PT-r0010w2000-ReachabilityFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type SKEL/SRCH) for 12 RwMutex-PT-r0010w2000-ReachabilityFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type SKEL/SRCH) for 12 RwMutex-PT-r0010w2000-ReachabilityFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 61 (type SKEL/SRCH) for RwMutex-PT-r0010w2000-ReachabilityFireability-04
lola: result : false
lola: markings : 5
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 58 (type FNDP) for RwMutex-PT-r0010w2000-ReachabilityFireability-04 (obsolete)
lola: CANCELED task # 59 (type EQUN) for RwMutex-PT-r0010w2000-ReachabilityFireability-04 (obsolete)
lola: CANCELED task # 62 (type SRCH) for RwMutex-PT-r0010w2000-ReachabilityFireability-04 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-59.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 62 (type SKEL/SRCH) for RwMutex-PT-r0010w2000-ReachabilityFireability-04
lola: result : false
lola: markings : 5
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 59 (type SKEL/EQUN) for RwMutex-PT-r0010w2000-ReachabilityFireability-04
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 16 (type CNST) for 15 RwMutex-PT-r0010w2000-ReachabilityFireability-05
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 25 (type CNST) for 24 RwMutex-PT-r0010w2000-ReachabilityFireability-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 1 (type CNST) for 0 RwMutex-PT-r0010w2000-ReachabilityFireability-00
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 16 (type CNST) for RwMutex-PT-r0010w2000-ReachabilityFireability-05
lola: result : false
lola: FINISHED task # 25 (type CNST) for RwMutex-PT-r0010w2000-ReachabilityFireability-08
lola: result : false
lola: FINISHED task # 1 (type CNST) for RwMutex-PT-r0010w2000-ReachabilityFireability-00
lola: result : false
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 46 (type CNST) for 45 RwMutex-PT-r0010w2000-ReachabilityFireability-15
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: planning for RwMutex-PT-r0010w2000-ReachabilityFireability-06 stopped (result already fixed).
lola: planning for RwMutex-PT-r0010w2000-ReachabilityFireability-04 stopped (result already fixed).
lola: FINISHED task # 46 (type CNST) for RwMutex-PT-r0010w2000-ReachabilityFireability-15
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 66 (type SKEL/FNDP) for 33 RwMutex-PT-r0010w2000-ReachabilityFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type SKEL/EQUN) for 33 RwMutex-PT-r0010w2000-ReachabilityFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 69 (type SKEL/SRCH) for 33 RwMutex-PT-r0010w2000-ReachabilityFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 70 (type SKEL/SRCH) for 33 RwMutex-PT-r0010w2000-ReachabilityFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 66 (type SKEL/FNDP) for RwMutex-PT-r0010w2000-ReachabilityFireability-11
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 67 (type EQUN) for RwMutex-PT-r0010w2000-ReachabilityFireability-11 (obsolete)
lola: CANCELED task # 69 (type SRCH) for RwMutex-PT-r0010w2000-ReachabilityFireability-11 (obsolete)
lola: CANCELED task # 70 (type SRCH) for RwMutex-PT-r0010w2000-ReachabilityFireability-11 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 73 (type SKEL/FNDP) for 21 RwMutex-PT-r0010w2000-ReachabilityFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 74 (type SKEL/EQUN) for 21 RwMutex-PT-r0010w2000-ReachabilityFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 76 (type SKEL/SRCH) for 21 RwMutex-PT-r0010w2000-ReachabilityFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type SKEL/SRCH) for 21 RwMutex-PT-r0010w2000-ReachabilityFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-67.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 76 (type SKEL/SRCH) for RwMutex-PT-r0010w2000-ReachabilityFireability-07
lola: result : false
lola: markings : 5
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 73 (type FNDP) for RwMutex-PT-r0010w2000-ReachabilityFireability-07 (obsolete)
lola: CANCELED task # 74 (type EQUN) for RwMutex-PT-r0010w2000-ReachabilityFireability-07 (obsolete)
lola: CANCELED task # 77 (type SRCH) for RwMutex-PT-r0010w2000-ReachabilityFireability-07 (obsolete)
lola: FINISHED task # 73 (type SKEL/FNDP) for RwMutex-PT-r0010w2000-ReachabilityFireability-07
lola: result : unknown
lola: fired transitions : 2721
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-74.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 67 (type SKEL/EQUN) for RwMutex-PT-r0010w2000-ReachabilityFireability-11
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 74 (type SKEL/EQUN) for RwMutex-PT-r0010w2000-ReachabilityFireability-07
lola: result : false
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 80 (type SKEL/FNDP) for 42 RwMutex-PT-r0010w2000-ReachabilityFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type SKEL/EQUN) for 42 RwMutex-PT-r0010w2000-ReachabilityFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 83 (type SKEL/SRCH) for 42 RwMutex-PT-r0010w2000-ReachabilityFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 84 (type SKEL/SRCH) for 42 RwMutex-PT-r0010w2000-ReachabilityFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 80 (type SKEL/FNDP) for RwMutex-PT-r0010w2000-ReachabilityFireability-14
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 81 (type EQUN) for RwMutex-PT-r0010w2000-ReachabilityFireability-14 (obsolete)
lola: CANCELED task # 83 (type SRCH) for RwMutex-PT-r0010w2000-ReachabilityFireability-14 (obsolete)
lola: CANCELED task # 84 (type SRCH) for RwMutex-PT-r0010w2000-ReachabilityFireability-14 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-81.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 81 (type SKEL/EQUN) for RwMutex-PT-r0010w2000-ReachabilityFireability-14
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0010w2000-ReachabilityFireability-00: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-04: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-05: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-06: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-07: EF false skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-08: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-ReachabilityFireability-01: AG 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-ReachabilityFireability-02: EF 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-ReachabilityFireability-03: AG 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-ReachabilityFireability-09: AG 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-ReachabilityFireability-10: EF 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-ReachabilityFireability-11: AG 0 0 0 0 2 0 0 3
RwMutex-PT-r0010w2000-ReachabilityFireability-12: AG 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-ReachabilityFireability-13: AG 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-ReachabilityFireability-14: EF 0 0 0 0 2 0 0 3

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 259 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 91 (type EXCL) for 36 RwMutex-PT-r0010w2000-ReachabilityFireability-12
lola: time limit : 371 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 87 (type FNDP) for 36 RwMutex-PT-r0010w2000-ReachabilityFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 88 (type EQUN) for 36 RwMutex-PT-r0010w2000-ReachabilityFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 90 (type SRCH) for 36 RwMutex-PT-r0010w2000-ReachabilityFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 90 (type SRCH) for RwMutex-PT-r0010w2000-ReachabilityFireability-12
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 87 (type FNDP) for RwMutex-PT-r0010w2000-ReachabilityFireability-12 (obsolete)
lola: CANCELED task # 88 (type EQUN) for RwMutex-PT-r0010w2000-ReachabilityFireability-12 (obsolete)
lola: CANCELED task # 91 (type EXCL) for RwMutex-PT-r0010w2000-ReachabilityFireability-12 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 98 (type EXCL) for 9 RwMutex-PT-r0010w2000-ReachabilityFireability-03
lola: time limit : 417 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 94 (type FNDP) for 9 RwMutex-PT-r0010w2000-ReachabilityFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 95 (type EQUN) for 9 RwMutex-PT-r0010w2000-ReachabilityFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 97 (type SRCH) for 9 RwMutex-PT-r0010w2000-ReachabilityFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 87 (type FNDP) for RwMutex-PT-r0010w2000-ReachabilityFireability-12
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 98 (type EXCL) for RwMutex-PT-r0010w2000-ReachabilityFireability-03
lola: result : false
lola: markings : 2011
lola: fired transitions : 4020
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 94 (type FNDP) for RwMutex-PT-r0010w2000-ReachabilityFireability-03 (obsolete)
lola: CANCELED task # 95 (type EQUN) for RwMutex-PT-r0010w2000-ReachabilityFireability-03 (obsolete)
lola: CANCELED task # 97 (type SRCH) for RwMutex-PT-r0010w2000-ReachabilityFireability-03 (obsolete)
lola: LAUNCH task # 117 (type EXCL) for 42 RwMutex-PT-r0010w2000-ReachabilityFireability-14
lola: time limit : 476 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 107 (type FNDP) for 3 RwMutex-PT-r0010w2000-ReachabilityFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 108 (type EQUN) for 3 RwMutex-PT-r0010w2000-ReachabilityFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 110 (type SRCH) for 3 RwMutex-PT-r0010w2000-ReachabilityFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 94 (type FNDP) for RwMutex-PT-r0010w2000-ReachabilityFireability-03
lola: result : unknown
lola: fired transitions : 53
lola: tried executions : 2
lola: time used : 1.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 117 (type EXCL) for RwMutex-PT-r0010w2000-ReachabilityFireability-14
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 123 (type EXCL) for 30 RwMutex-PT-r0010w2000-ReachabilityFireability-10
lola: time limit : 556 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-95.sara.
lola: FINISHED task # 123 (type EXCL) for RwMutex-PT-r0010w2000-ReachabilityFireability-10
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 104 (type EXCL) for 6 RwMutex-PT-r0010w2000-ReachabilityFireability-02
lola: time limit : 667 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0010w2000-ReachabilityFireability-00: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-03: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-04: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-05: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-06: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-07: EF false skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-08: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-10: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-12: AG false tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-14: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-ReachabilityFireability-01: AG 0 2 3 0 1 0 0 0
RwMutex-PT-r0010w2000-ReachabilityFireability-02: EF 0 4 1 0 1 0 0 0
RwMutex-PT-r0010w2000-ReachabilityFireability-09: AG 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-ReachabilityFireability-11: AG 0 5 0 0 2 0 0 3
RwMutex-PT-r0010w2000-ReachabilityFireability-13: AG 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
104 EF EXCL 1/667 1/32 RwMutex-PT-r0010w2000-ReachabilityFireability-02 1666 m, 333 m/sec, 3330 t fired, .
107 EF FNDP 2/833 0/5 RwMutex-PT-r0010w2000-ReachabilityFireability-01 71 t fired, 1 attempts, .
108 EF STEQ 2/833 0/5 RwMutex-PT-r0010w2000-ReachabilityFireability-01 sara not yet started (preprocessing).
110 EF SRCH 2/833 1/5 RwMutex-PT-r0010w2000-ReachabilityFireability-01 58 m, 11 m/sec, 113 t fired, .

Time elapsed: 264 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 104 (type EXCL) for RwMutex-PT-r0010w2000-ReachabilityFireability-02
lola: result : false
lola: markings : 2011
lola: fired transitions : 4020
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 130 (type EXCL) for 33 RwMutex-PT-r0010w2000-ReachabilityFireability-11
lola: time limit : 834 sec
lola: memory limit: 32 pages
lola: FINISHED task # 130 (type EXCL) for RwMutex-PT-r0010w2000-ReachabilityFireability-11
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 111 (type EXCL) for 3 RwMutex-PT-r0010w2000-ReachabilityFireability-01
lola: time limit : 1112 sec
lola: memory limit: 32 pages
lola: FINISHED task # 111 (type EXCL) for RwMutex-PT-r0010w2000-ReachabilityFireability-01
lola: result : false
lola: markings : 2011
lola: fired transitions : 4020
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 107 (type FNDP) for RwMutex-PT-r0010w2000-ReachabilityFireability-01 (obsolete)
lola: CANCELED task # 108 (type EQUN) for RwMutex-PT-r0010w2000-ReachabilityFireability-01 (obsolete)
lola: CANCELED task # 110 (type SRCH) for RwMutex-PT-r0010w2000-ReachabilityFireability-01 (obsolete)
lola: FINISHED task # 107 (type FNDP) for RwMutex-PT-r0010w2000-ReachabilityFireability-01
lola: result : unknown
lola: fired transitions : 155
lola: tried executions : 2
lola: time used : 3.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-88.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0010w2000-ReachabilityFireability-00: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-01: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-02: EF false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-03: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-04: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-05: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-06: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-07: EF false skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-08: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-10: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-11: AG false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-12: AG false tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-14: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-ReachabilityFireability-09: AG 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-ReachabilityFireability-13: AG 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 269 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0010w2000-ReachabilityFireability-00: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-01: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-02: EF false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-03: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-04: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-05: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-06: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-07: EF false skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-08: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-10: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-11: AG false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-12: AG false tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-14: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-ReachabilityFireability-09: AG 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-ReachabilityFireability-13: AG 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 274 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 137 (type EXCL) for 39 RwMutex-PT-r0010w2000-ReachabilityFireability-13
lola: time limit : 1661 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 133 (type FNDP) for 39 RwMutex-PT-r0010w2000-ReachabilityFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 134 (type EQUN) for 39 RwMutex-PT-r0010w2000-ReachabilityFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 136 (type SRCH) for 39 RwMutex-PT-r0010w2000-ReachabilityFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 137 (type EXCL) for RwMutex-PT-r0010w2000-ReachabilityFireability-13
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 133 (type FNDP) for RwMutex-PT-r0010w2000-ReachabilityFireability-13 (obsolete)
lola: CANCELED task # 134 (type EQUN) for RwMutex-PT-r0010w2000-ReachabilityFireability-13 (obsolete)
lola: CANCELED task # 136 (type SRCH) for RwMutex-PT-r0010w2000-ReachabilityFireability-13 (obsolete)
lola: FINISHED task # 133 (type FNDP) for RwMutex-PT-r0010w2000-ReachabilityFireability-13
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-134.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 134 (type EQUN) for RwMutex-PT-r0010w2000-ReachabilityFireability-13
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0010w2000-ReachabilityFireability-00: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-01: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-02: EF false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-03: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-04: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-05: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-06: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-07: EF false skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-08: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-10: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-11: AG false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-12: AG false tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-13: AG false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-14: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-ReachabilityFireability-09: AG 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 279 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0010w2000-ReachabilityFireability-00: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-01: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-02: EF false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-03: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-04: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-05: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-06: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-07: EF false skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-08: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-10: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-11: AG false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-12: AG false tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-13: AG false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-14: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-ReachabilityFireability-09: AG 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 284 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: planning for RwMutex-PT-r0010w2000-ReachabilityFireability-07 stopped (result already fixed).
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0010w2000-ReachabilityFireability-00: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-01: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-02: EF false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-03: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-04: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-05: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-06: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-07: EF false skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-08: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-10: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-11: AG false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-12: AG false tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-13: AG false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-14: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-ReachabilityFireability-09: AG 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 289 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0010w2000-ReachabilityFireability-00: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-01: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-02: EF false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-03: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-04: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-05: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-06: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-07: EF false skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-08: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-10: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-11: AG false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-12: AG false tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-13: AG false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-14: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-ReachabilityFireability-09: AG 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 294 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0010w2000-ReachabilityFireability-00: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-01: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-02: EF false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-03: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-04: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-05: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-06: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-07: EF false skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-08: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-10: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-11: AG false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-12: AG false tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-13: AG false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-14: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-ReachabilityFireability-09: AG 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 299 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-108.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0010w2000-ReachabilityFireability-00: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-01: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-02: EF false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-03: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-04: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-05: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-06: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-07: EF false skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-08: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-10: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-11: AG false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-12: AG false tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-13: AG false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-14: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-ReachabilityFireability-09: AG 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 304 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 144 (type EXCL) for 27 RwMutex-PT-r0010w2000-ReachabilityFireability-09
lola: time limit : 3293 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 140 (type FNDP) for 27 RwMutex-PT-r0010w2000-ReachabilityFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 141 (type EQUN) for 27 RwMutex-PT-r0010w2000-ReachabilityFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 143 (type SRCH) for 27 RwMutex-PT-r0010w2000-ReachabilityFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 144 (type EXCL) for RwMutex-PT-r0010w2000-ReachabilityFireability-09
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 140 (type FNDP) for RwMutex-PT-r0010w2000-ReachabilityFireability-09 (obsolete)
lola: CANCELED task # 141 (type EQUN) for RwMutex-PT-r0010w2000-ReachabilityFireability-09 (obsolete)
lola: CANCELED task # 143 (type SRCH) for RwMutex-PT-r0010w2000-ReachabilityFireability-09 (obsolete)
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0010w2000-ReachabilityFireability-00: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-01: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-02: EF false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-03: AG true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-04: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-05: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-06: AG true skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-07: EF false skeleton: tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-08: INITIAL false preprocessing
RwMutex-PT-r0010w2000-ReachabilityFireability-09: AG false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-10: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-11: AG false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-12: AG false tandem / insertion
RwMutex-PT-r0010w2000-ReachabilityFireability-13: AG false tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-14: EF true tandem / relaxed
RwMutex-PT-r0010w2000-ReachabilityFireability-15: INITIAL false preprocessing


Time elapsed: 307 secs. Pages in use: 2

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RwMutex-PT-r0010w2000"
export BK_EXAMINATION="ReachabilityFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RwMutex-PT-r0010w2000, examination is ReachabilityFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891808500159"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RwMutex-PT-r0010w2000.tgz
mv RwMutex-PT-r0010w2000 execution
cd execution
if [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "UpperBounds" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] || [ "ReachabilityFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;