Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r359-smll-167891808500154.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RwMutex-PT-r0010w2000, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r359-smll-167891808500154
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.1M
-rw-r--r-- 1 mcc users 5.8K Feb 25 23:47 CTLCardinality.txt
-rw-r--r-- 1 mcc users 56K Feb 25 23:47 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K Feb 25 23:00 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K Feb 25 23:00 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:48 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:48 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:48 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:48 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 01:18 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 143K Feb 26 01:18 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.3K Feb 26 00:39 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 80K Feb 26 00:39 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:48 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:48 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 11 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 3.6M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-00
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-01
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-02
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-03
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-04
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-05
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-06
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-07
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-08
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-09
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-10
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-11
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-12
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-13
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-14
FORMULA_NAME RwMutex-PT-r0010w2000-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678998251751

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RwMutex-PT-r0010w2000
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 20:24:15] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-16 20:24:15] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 20:24:15] [INFO ] Load time of PNML (sax parser for PT used): 657 ms
[2023-03-16 20:24:15] [INFO ] Transformed 4030 places.
[2023-03-16 20:24:15] [INFO ] Transformed 4020 transitions.
[2023-03-16 20:24:15] [INFO ] Found NUPN structural information;
[2023-03-16 20:24:15] [INFO ] Parsed PT model containing 4030 places and 4020 transitions and 48060 arcs in 859 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 19 ms.
Support contains 138 out of 4030 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 4030/4030 places, 4020/4020 transitions.
Applied a total of 0 rules in 862 ms. Remains 4030 /4030 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
// Phase 1: matrix 4020 rows 4030 cols
[2023-03-16 20:24:18] [INFO ] Computed 2020 place invariants in 1715 ms
[2023-03-16 20:24:20] [INFO ] Implicit Places using invariants in 3383 ms returned []
[2023-03-16 20:24:20] [INFO ] Invariant cache hit.
[2023-03-16 20:24:21] [INFO ] Implicit Places using invariants and state equation in 1090 ms returned []
Implicit Place search using SMT with State Equation took 4538 ms to find 0 implicit places.
[2023-03-16 20:24:21] [INFO ] Invariant cache hit.
[2023-03-16 20:24:22] [INFO ] Dead Transitions using invariants and state equation in 1206 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6612 ms. Remains : 4030/4030 places, 4020/4020 transitions.
Support contains 138 out of 4030 places after structural reductions.
[2023-03-16 20:24:24] [INFO ] Flatten gal took : 962 ms
[2023-03-16 20:24:24] [INFO ] Flatten gal took : 438 ms
[2023-03-16 20:24:26] [INFO ] Input system was already deterministic with 4020 transitions.
Support contains 136 out of 4030 places (down from 138) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 5469 ms. (steps per millisecond=1 ) properties (out of 95) seen :66
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 45 ms. (steps per millisecond=22 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 41 ms. (steps per millisecond=24 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 41 ms. (steps per millisecond=24 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 41 ms. (steps per millisecond=24 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 41 ms. (steps per millisecond=24 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 41 ms. (steps per millisecond=24 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 41 ms. (steps per millisecond=24 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 41 ms. (steps per millisecond=24 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 48 ms. (steps per millisecond=20 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 54 ms. (steps per millisecond=18 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 66 ms. (steps per millisecond=15 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 67 ms. (steps per millisecond=14 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 65 ms. (steps per millisecond=15 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 91 ms. (steps per millisecond=11 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 66 ms. (steps per millisecond=15 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 67 ms. (steps per millisecond=14 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 57 ms. (steps per millisecond=17 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 39 ms. (steps per millisecond=25 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 41 ms. (steps per millisecond=24 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 39 ms. (steps per millisecond=25 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 0 resets, run finished after 39 ms. (steps per millisecond=25 ) properties (out of 29) seen :0
Running SMT prover for 29 properties.
[2023-03-16 20:24:32] [INFO ] Invariant cache hit.
[2023-03-16 20:24:38] [INFO ] [Real]Absence check using 2020 positive place invariants in 1078 ms returned sat
[2023-03-16 20:24:47] [INFO ] After 7771ms SMT Verify possible using state equation in real domain returned unsat :4 sat :5 real:20
[2023-03-16 20:24:48] [INFO ] After 9643ms SMT Verify possible using trap constraints in real domain returned unsat :4 sat :3 real:22
Attempting to minimize the solution found.
Minimization took 655 ms.
[2023-03-16 20:24:49] [INFO ] After 16135ms SMT Verify possible using all constraints in real domain returned unsat :4 sat :0 real:25
[2023-03-16 20:24:53] [INFO ] [Nat]Absence check using 2020 positive place invariants in 1135 ms returned sat
[2023-03-16 20:25:06] [INFO ] After 11117ms SMT Verify possible using state equation in natural domain returned unsat :11 sat :18
[2023-03-16 20:25:14] [INFO ] After 18918ms SMT Verify possible using trap constraints in natural domain returned unsat :11 sat :18
Attempting to minimize the solution found.
Minimization took 26 ms.
[2023-03-16 20:25:14] [INFO ] After 25041ms SMT Verify possible using all constraints in natural domain returned unsat :11 sat :18
Fused 29 Parikh solutions to 18 different solutions.
Finished Parikh walk after 1 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=0 )
Parikh walk visited 18 properties in 59 ms.
Successfully simplified 11 atomic propositions for a total of 16 simplifications.
FORMULA RwMutex-PT-r0010w2000-CTLFireability-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA RwMutex-PT-r0010w2000-CTLFireability-13 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-16 20:25:15] [INFO ] Flatten gal took : 537 ms
[2023-03-16 20:25:15] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA RwMutex-PT-r0010w2000-CTLFireability-01 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-16 20:25:15] [INFO ] Flatten gal took : 378 ms
[2023-03-16 20:25:16] [INFO ] Input system was already deterministic with 4020 transitions.
Support contains 80 out of 4030 places (down from 89) after GAL structural reductions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 4030/4030 places, 4020/4020 transitions.
Applied a total of 0 rules in 713 ms. Remains 4030 /4030 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 715 ms. Remains : 4030/4030 places, 4020/4020 transitions.
[2023-03-16 20:25:17] [INFO ] Flatten gal took : 323 ms
[2023-03-16 20:25:17] [INFO ] Flatten gal took : 347 ms
[2023-03-16 20:25:18] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4030/4030 places, 4020/4020 transitions.
Applied a total of 0 rules in 726 ms. Remains 4030 /4030 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 728 ms. Remains : 4030/4030 places, 4020/4020 transitions.
[2023-03-16 20:25:19] [INFO ] Flatten gal took : 319 ms
[2023-03-16 20:25:20] [INFO ] Flatten gal took : 366 ms
[2023-03-16 20:25:20] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 4030/4030 places, 4020/4020 transitions.
Applied a total of 0 rules in 1915 ms. Remains 4030 /4030 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1916 ms. Remains : 4030/4030 places, 4020/4020 transitions.
[2023-03-16 20:25:22] [INFO ] Flatten gal took : 308 ms
[2023-03-16 20:25:23] [INFO ] Flatten gal took : 322 ms
[2023-03-16 20:25:23] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4030/4030 places, 4020/4020 transitions.
Applied a total of 0 rules in 481 ms. Remains 4030 /4030 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 482 ms. Remains : 4030/4030 places, 4020/4020 transitions.
[2023-03-16 20:25:24] [INFO ] Flatten gal took : 374 ms
[2023-03-16 20:25:25] [INFO ] Flatten gal took : 439 ms
[2023-03-16 20:25:25] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4030/4030 places, 4020/4020 transitions.
Applied a total of 0 rules in 454 ms. Remains 4030 /4030 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 455 ms. Remains : 4030/4030 places, 4020/4020 transitions.
[2023-03-16 20:25:26] [INFO ] Flatten gal took : 313 ms
[2023-03-16 20:25:26] [INFO ] Flatten gal took : 322 ms
[2023-03-16 20:25:27] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4030/4030 places, 4020/4020 transitions.
Applied a total of 0 rules in 467 ms. Remains 4030 /4030 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 469 ms. Remains : 4030/4030 places, 4020/4020 transitions.
[2023-03-16 20:25:28] [INFO ] Flatten gal took : 314 ms
[2023-03-16 20:25:28] [INFO ] Flatten gal took : 321 ms
[2023-03-16 20:25:29] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4030/4030 places, 4020/4020 transitions.
Applied a total of 0 rules in 476 ms. Remains 4030 /4030 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 476 ms. Remains : 4030/4030 places, 4020/4020 transitions.
[2023-03-16 20:25:30] [INFO ] Flatten gal took : 313 ms
[2023-03-16 20:25:30] [INFO ] Flatten gal took : 321 ms
[2023-03-16 20:25:31] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4030/4030 places, 4020/4020 transitions.
Applied a total of 0 rules in 455 ms. Remains 4030 /4030 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 456 ms. Remains : 4030/4030 places, 4020/4020 transitions.
[2023-03-16 20:25:31] [INFO ] Flatten gal took : 302 ms
[2023-03-16 20:25:32] [INFO ] Flatten gal took : 320 ms
[2023-03-16 20:25:32] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4030/4030 places, 4020/4020 transitions.
Applied a total of 0 rules in 455 ms. Remains 4030 /4030 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 457 ms. Remains : 4030/4030 places, 4020/4020 transitions.
[2023-03-16 20:25:33] [INFO ] Flatten gal took : 302 ms
[2023-03-16 20:25:33] [INFO ] Flatten gal took : 318 ms
[2023-03-16 20:25:34] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4030/4030 places, 4020/4020 transitions.
Applied a total of 0 rules in 450 ms. Remains 4030 /4030 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 451 ms. Remains : 4030/4030 places, 4020/4020 transitions.
[2023-03-16 20:25:35] [INFO ] Flatten gal took : 303 ms
[2023-03-16 20:25:35] [INFO ] Flatten gal took : 317 ms
[2023-03-16 20:25:36] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4030/4030 places, 4020/4020 transitions.
Applied a total of 0 rules in 456 ms. Remains 4030 /4030 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 456 ms. Remains : 4030/4030 places, 4020/4020 transitions.
[2023-03-16 20:25:36] [INFO ] Flatten gal took : 297 ms
[2023-03-16 20:25:37] [INFO ] Flatten gal took : 318 ms
[2023-03-16 20:25:37] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4030/4030 places, 4020/4020 transitions.
Applied a total of 0 rules in 579 ms. Remains 4030 /4030 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 583 ms. Remains : 4030/4030 places, 4020/4020 transitions.
[2023-03-16 20:25:38] [INFO ] Flatten gal took : 300 ms
[2023-03-16 20:25:39] [INFO ] Flatten gal took : 317 ms
[2023-03-16 20:25:39] [INFO ] Input system was already deterministic with 4020 transitions.
Starting structural reductions in LTL mode, iteration 0 : 4030/4030 places, 4020/4020 transitions.
Applied a total of 0 rules in 453 ms. Remains 4030 /4030 variables (removed 0) and now considering 4020/4020 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 454 ms. Remains : 4030/4030 places, 4020/4020 transitions.
[2023-03-16 20:25:40] [INFO ] Flatten gal took : 318 ms
[2023-03-16 20:25:40] [INFO ] Flatten gal took : 317 ms
[2023-03-16 20:25:41] [INFO ] Input system was already deterministic with 4020 transitions.
[2023-03-16 20:25:41] [INFO ] Flatten gal took : 313 ms
[2023-03-16 20:25:42] [INFO ] Flatten gal took : 317 ms
[2023-03-16 20:25:42] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 9 ms.
[2023-03-16 20:25:42] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 4030 places, 4020 transitions and 48060 arcs took 65 ms.
Total runtime 87160 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RwMutex-PT-r0010w2000
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/370
CTLFireability

FORMULA RwMutex-PT-r0010w2000-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RwMutex-PT-r0010w2000-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678998802160

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/370/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/370/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/370/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 37 (type EXCL) for 36 RwMutex-PT-r0010w2000-CTLFireability-15
lola: time limit : 267 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 37 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-15
lola: result : true
lola: markings : 2
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
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lola: time limit : 289 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 22 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-09
lola: result : true
lola: markings : 2011
lola: fired transitions : 4897
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 RwMutex-PT-r0010w2000-CTLFireability-14
lola: time limit : 315 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-14
lola: result : true
lola: markings : 2
lola: fired transitions : 10
lola: time used : 0.000000
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lola: time limit : 347 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 31 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-12
lola: result : true
lola: markings : 2010
lola: fired transitions : 2009
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 RwMutex-PT-r0010w2000-CTLFireability-08
lola: time limit : 386 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 1 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 0/386 1/32 RwMutex-PT-r0010w2000-CTLFireability-08 .

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lola: FINISHED task # 19 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-08
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 RwMutex-PT-r0010w2000-CTLFireability-10
lola: time limit : 434 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0010w2000-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 30 m, 6 m/sec, 57 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 10/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 58 m, 5 m/sec, 113 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 15/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 89 m, 6 m/sec, 175 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 20/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 119 m, 6 m/sec, 235 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 25/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 150 m, 6 m/sec, 297 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 30/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 179 m, 5 m/sec, 355 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
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25 CTL EXCL 35/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 1231 m, 210 m/sec, 10644 t fired, .

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25 CTL EXCL 40/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 1259 m, 5 m/sec, 10700 t fired, .

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25 CTL EXCL 45/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 1289 m, 6 m/sec, 10760 t fired, .

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25 CTL EXCL 50/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 1318 m, 5 m/sec, 10818 t fired, .

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25 CTL EXCL 55/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 1347 m, 5 m/sec, 10876 t fired, .

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25 CTL EXCL 70/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 1436 m, 6 m/sec, 11054 t fired, .

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25 CTL EXCL 85/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 1529 m, 6 m/sec, 11242 t fired, .

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25 CTL EXCL 190/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2181 m, 6 m/sec, 12548 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
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25 CTL EXCL 195/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2212 m, 6 m/sec, 12610 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
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25 CTL EXCL 200/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2243 m, 6 m/sec, 12672 t fired, .

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25 CTL EXCL 205/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2274 m, 6 m/sec, 12734 t fired, .

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25 CTL EXCL 210/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2305 m, 6 m/sec, 12796 t fired, .

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25 CTL EXCL 220/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2366 m, 6 m/sec, 12918 t fired, .

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25 CTL EXCL 225/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2397 m, 6 m/sec, 12980 t fired, .

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25 CTL EXCL 230/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2428 m, 6 m/sec, 13042 t fired, .

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25 CTL EXCL 235/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2458 m, 6 m/sec, 13103 t fired, .

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25 CTL EXCL 240/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2489 m, 6 m/sec, 13167 t fired, .

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25 CTL EXCL 245/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2520 m, 6 m/sec, 13229 t fired, .

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25 CTL EXCL 250/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2551 m, 6 m/sec, 13291 t fired, .

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25 CTL EXCL 260/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2612 m, 6 m/sec, 13413 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 265/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2641 m, 5 m/sec, 13471 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 270/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2671 m, 6 m/sec, 13531 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 275/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2702 m, 6 m/sec, 13593 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 280/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2733 m, 6 m/sec, 13655 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 285/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2763 m, 6 m/sec, 13715 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 290/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2794 m, 6 m/sec, 13777 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 295/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2824 m, 6 m/sec, 13837 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 300/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2855 m, 6 m/sec, 13899 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 305/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2886 m, 6 m/sec, 13961 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 310/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2916 m, 6 m/sec, 14022 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 315/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2947 m, 6 m/sec, 14085 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 320/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 2977 m, 6 m/sec, 14145 t fired, .

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RwMutex-PT-r0010w2000-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 325/434 1/32 RwMutex-PT-r0010w2000-CTLFireability-10 3008 m, 6 m/sec, 14207 t fired, .

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lola: FINISHED task # 25 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-10
lola: result : false
lola: markings : 3024
lola: fired transitions : 14240
lola: time used : 328.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 RwMutex-PT-r0010w2000-CTLFireability-11
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-11
lola: result : false
lola: markings : 2011
lola: fired transitions : 11352
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 RwMutex-PT-r0010w2000-CTLFireability-06
lola: time limit : 524 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-06
lola: result : true
lola: markings : 3024
lola: fired transitions : 26609
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 RwMutex-PT-r0010w2000-CTLFireability-05
lola: time limit : 628 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-05
lola: result : false
lola: markings : 2011
lola: fired transitions : 3381
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 RwMutex-PT-r0010w2000-CTLFireability-04
lola: time limit : 786 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0010w2000-CTLFireability-05: CTL false CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-10: CTL false CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-11: CTL false CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0010w2000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0010w2000-CTLFireability-04: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 0/786 1/32 RwMutex-PT-r0010w2000-CTLFireability-04 11 m, 2 m/sec, 21 t fired, .

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lola: FINISHED task # 10 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-04
lola: result : false
lola: markings : 2011
lola: fired transitions : 7184
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 RwMutex-PT-r0010w2000-CTLFireability-02
lola: time limit : 1047 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-02
lola: result : false
lola: markings : 3024
lola: fired transitions : 14240
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 RwMutex-PT-r0010w2000-CTLFireability-00
lola: time limit : 1571 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-00
lola: result : false
lola: markings : 2011
lola: fired transitions : 6032
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 RwMutex-PT-r0010w2000-CTLFireability-03
lola: time limit : 3142 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for RwMutex-PT-r0010w2000-CTLFireability-03
lola: result : true
lola: markings : 2
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0010w2000-CTLFireability-00: CTL false CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-03: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-04: CTL false CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-05: CTL false CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-08: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-10: CTL false CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-11: CTL false CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-12: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-14: CTL true CTL model checker
RwMutex-PT-r0010w2000-CTLFireability-15: CTL true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RwMutex-PT-r0010w2000"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RwMutex-PT-r0010w2000, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r359-smll-167891808500154"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RwMutex-PT-r0010w2000.tgz
mv RwMutex-PT-r0010w2000 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;