fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r358-smll-167891807600314
Last Updated
May 14, 2023

About the Execution of LoLA for SatelliteMemory-PT-X01500Y0046

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
4976.195 180411.00 163756.00 649.90 T?T???T?FF?FFT?? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r358-smll-167891807600314.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is SatelliteMemory-PT-X01500Y0046, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r358-smll-167891807600314
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 484K
-rw-r--r-- 1 mcc users 7.7K Feb 26 12:50 CTLCardinality.txt
-rw-r--r-- 1 mcc users 83K Feb 26 12:50 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K Feb 26 12:43 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K Feb 26 12:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.2K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:50 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:50 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:50 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:50 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 12:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 156K Feb 26 12:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Feb 26 12:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 57K Feb 26 12:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:50 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:50 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 12 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rwxr-xr-x 1 mcc users 5.5K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-00
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-01
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-02
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-03
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-04
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-05
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-06
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-07
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-08
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-09
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-10
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-11
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-12
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-13
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-14
FORMULA_NAME SatelliteMemory-PT-X01500Y0046-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679061915615

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=SatelliteMemory-PT-X01500Y0046
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT SatelliteMemory-PT-X01500Y0046
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA SatelliteMemory-PT-X01500Y0046-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X01500Y0046-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X01500Y0046-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X01500Y0046-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X01500Y0046-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X01500Y0046-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X01500Y0046-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SatelliteMemory-PT-X01500Y0046-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679062096026

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 9 (type EXCL) for 6 SatelliteMemory-PT-X01500Y0046-CTLFireability-02
lola: time limit : 124 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 9 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-02
lola: result : true
lola: markings : 11998
lola: fired transitions : 17997
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 58 (type EXCL) for 57 SatelliteMemory-PT-X01500Y0046-CTLFireability-15
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:662
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 65 (type FNDP) for 0 SatelliteMemory-PT-X01500Y0046-CTLFireability-00
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lola: LAUNCH task # 68 (type SRCH) for 0 SatelliteMemory-PT-X01500Y0046-CTLFireability-00
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 68 (type SRCH) for SatelliteMemory-PT-X01500Y0046-CTLFireability-00
lola: result : unknown
lola: markings : 5
lola: fired transitions : 4
lola: time used : 0.000000
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lola: FINISHED task # 65 (type FNDP) for SatelliteMemory-PT-X01500Y0046-CTLFireability-00
lola: result : true
lola: fired transitions : 2815
lola: tried executions : 1
lola: time used : 0.000000
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lola: CANCELED task # 66 (type EQUN) for SatelliteMemory-PT-X01500Y0046-CTLFireability-00 (obsolete)
lola: FINISHED task # 66 (type EQUN) for SatelliteMemory-PT-X01500Y0046-CTLFireability-00
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 5/225 9/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-15 1906916 m, 381383 m/sec, 3096427 t fired, .

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SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

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58 CTL EXCL 10/225 17/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-15 3893202 m, 397257 m/sec, 6325438 t fired, .

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SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

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58 CTL EXCL 15/225 25/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-15 5934562 m, 408272 m/sec, 9643073 t fired, .

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SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
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SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: FINISHED task # 55 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-14
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
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lola: time limit : 255 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 1 0 3 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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53 CTL EXCL 5/255 23/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-14 5439829 m, 1087965 m/sec, 5456228 t fired, .

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SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker

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SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
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SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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lola: result : true
lola: markings : 5634
lola: fired transitions : 8452
lola: time used : 0.000000
lola: memory pages used : 1
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

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SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
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39 CTL EXCL 5/324 11/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-10 2639804 m, 527960 m/sec, 8248282 t fired, .

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SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
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SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
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SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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39 CTL EXCL 10/324 21/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-10 5201692 m, 512377 m/sec, 16253284 t fired, .

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SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

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SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 15/324 31/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-10 7699647 m, 499591 m/sec, 24059507 t fired, .

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lola: CANCELED task # 39 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 36 (type EXCL) for 35 SatelliteMemory-PT-X01500Y0046-CTLFireability-09
lola: time limit : 355 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-09
lola: result : false
lola: markings : 12003
lola: fired transitions : 12009
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 19 SatelliteMemory-PT-X01500Y0046-CTLFireability-05
lola: time limit : 394 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 5/394 5/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-05 1121041 m, 224208 m/sec, 5747814 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 10/394 10/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-05 2289428 m, 233677 m/sec, 11737331 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 15/394 14/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-05 3452145 m, 232543 m/sec, 17692002 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 20/394 19/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-05 4585525 m, 226676 m/sec, 23499116 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 25/394 23/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-05 5662822 m, 215459 m/sec, 29019316 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 30/394 27/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-05 6720105 m, 211456 m/sec, 34436879 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 35/394 32/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-05 7796947 m, 215368 m/sec, 39957169 t fired, .

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lola: CANCELED task # 20 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 17 (type EXCL) for 16 SatelliteMemory-PT-X01500Y0046-CTLFireability-04
lola: time limit : 438 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 5/438 4/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 737680 m, 147536 m/sec, 5388598 t fired, .

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SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
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SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 10/438 7/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 1454288 m, 143321 m/sec, 10674313 t fired, .

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SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

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SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
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SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 15/438 10/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 2157511 m, 140644 m/sec, 15859691 t fired, .

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SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 20/438 12/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 2859039 m, 140305 m/sec, 21034491 t fired, .

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SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 25/438 15/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 3557707 m, 139733 m/sec, 26187489 t fired, .

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SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 30/438 18/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 4253737 m, 139206 m/sec, 31320368 t fired, .

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SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 35/438 21/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 4947167 m, 138686 m/sec, 36433426 t fired, .

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SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 40/438 24/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 5636682 m, 137903 m/sec, 41517363 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 45/438 27/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 6324030 m, 137469 m/sec, 46588411 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 50/438 30/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-04 7010068 m, 137207 m/sec, 51646016 t fired, .

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lola: CANCELED task # 17 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 14 (type EXCL) for 13 SatelliteMemory-PT-X01500Y0046-CTLFireability-03
lola: time limit : 493 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 5/493 18/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-03 4154938 m, 830987 m/sec, 6751117 t fired, .

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lola: CANCELED task # 14 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 64 (type EXCL) for 22 SatelliteMemory-PT-X01500Y0046-CTLFireability-06
lola: time limit : 574 sec
lola: memory limit: 32 pages
lola: FINISHED task # 64 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-06
lola: result : false
lola: markings : 5637
lola: fired transitions : 5638
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 60 (type EXCL) for 41 SatelliteMemory-PT-X01500Y0046-CTLFireability-11
lola: time limit : 861 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-11
lola: result : true
lola: markings : 2817
lola: fired transitions : 2817
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 62 (type EXCL) for 29 SatelliteMemory-PT-X01500Y0046-CTLFireability-07
lola: time limit : 1148 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ true LTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F false state space / EG
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 AGEF EXCL 5/1148 25/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-07 6542341 m, 1308468 m/sec, 6549619 t fired, .

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lola: CANCELED task # 62 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ true LTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F false state space / EG
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 33 (type EXCL) for 32 SatelliteMemory-PT-X01500Y0046-CTLFireability-08
lola: time limit : 1717 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-08
lola: result : false
lola: markings : 6001
lola: fired transitions : 27000
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 SatelliteMemory-PT-X01500Y0046-CTLFireability-01
lola: time limit : 3435 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ true LTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F false state space / EG
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/3435 13/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-01 3208025 m, 641605 m/sec, 8819067 t fired, .

Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ true LTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F false state space / EG
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/3435 24/32 SatelliteMemory-PT-X01500Y0046-CTLFireability-01 5946303 m, 547655 m/sec, 16349332 t fired, .

Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for SatelliteMemory-PT-X01500Y0046-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ true LTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F false state space / EG
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ 0 0 0 0 3 0 1 0
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SatelliteMemory-PT-X01500Y0046-CTLFireability-00: EF true findpath
SatelliteMemory-PT-X01500Y0046-CTLFireability-01: CTL unknown AGGR
SatelliteMemory-PT-X01500Y0046-CTLFireability-02: DISJ true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-03: CTL unknown AGGR
SatelliteMemory-PT-X01500Y0046-CTLFireability-04: CTL unknown AGGR
SatelliteMemory-PT-X01500Y0046-CTLFireability-05: CTL unknown AGGR
SatelliteMemory-PT-X01500Y0046-CTLFireability-06: DISJ true LTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-07: EFAG unknown AGGR
SatelliteMemory-PT-X01500Y0046-CTLFireability-08: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-09: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-10: CTL unknown AGGR
SatelliteMemory-PT-X01500Y0046-CTLFireability-11: F false state space / EG
SatelliteMemory-PT-X01500Y0046-CTLFireability-12: CTL false CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-13: CTL true CTL model checker
SatelliteMemory-PT-X01500Y0046-CTLFireability-14: DISJ unknown DISJ
SatelliteMemory-PT-X01500Y0046-CTLFireability-15: CTL unknown AGGR


Time elapsed: 180 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SatelliteMemory-PT-X01500Y0046"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is SatelliteMemory-PT-X01500Y0046, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r358-smll-167891807600314"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SatelliteMemory-PT-X01500Y0046.tgz
mv SatelliteMemory-PT-X01500Y0046 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;