About the Execution of LoLA for RwMutex-PT-r1000w0010
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16215.552 | 665585.00 | 714984.00 | 11903.00 | F?????F?FFT?FTF? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r358-smll-167891807400186.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is RwMutex-PT-r1000w0010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r358-smll-167891807400186
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.7M
-rw-r--r-- 1 mcc users 6.2K Feb 25 22:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 64K Feb 25 22:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.6K Feb 25 22:53 CTLFireability.txt
-rw-r--r-- 1 mcc users 39K Feb 25 22:53 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:49 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:49 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 16:49 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 16:49 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 23:09 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 147K Feb 25 23:09 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 25 23:03 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 101K Feb 25 23:03 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:49 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:49 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 11 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 2.2M Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-00
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-01
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-02
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-03
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-04
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-05
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-06
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-07
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-08
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-09
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-10
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-11
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-12
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-13
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-14
FORMULA_NAME RwMutex-PT-r1000w0010-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678977047096
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RwMutex-PT-r1000w0010
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT RwMutex-PT-r1000w0010
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA RwMutex-PT-r1000w0010-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r1000w0010-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r1000w0010-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r1000w0010-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r1000w0010-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r1000w0010-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r1000w0010-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r1000w0010-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678977712681
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: RELEASE
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 25 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 56 (type EXCL) for 0 RwMutex-PT-r1000w0010-CTLFireability-00
lola: time limit : 198 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-00
lola: result : true
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 44 RwMutex-PT-r1000w0010-CTLFireability-12
lola: time limit : 210 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-12
lola: result : false
lola: markings : 17
lola: fired transitions : 1412
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 0 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 30 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 8 (type EXCL) for 3 RwMutex-PT-r1000w0010-CTLFireability-01
lola: time limit : 222 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 8 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-01
lola: result : false
lola: markings : 2325
lola: fired transitions : 8404
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 RwMutex-PT-r1000w0010-CTLFireability-06
lola: time limit : 237 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 1/237 1/32 RwMutex-PT-r1000w0010-CTLFireability-06 69253 m, 13850 m/sec, 138731 t fired, .
Time elapsed: 35 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 6/237 2/32 RwMutex-PT-r1000w0010-CTLFireability-06 260190 m, 38187 m/sec, 450059 t fired, .
Time elapsed: 40 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 11/237 3/32 RwMutex-PT-r1000w0010-CTLFireability-06 419155 m, 31793 m/sec, 697174 t fired, .
Time elapsed: 45 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 16/237 4/32 RwMutex-PT-r1000w0010-CTLFireability-06 561718 m, 28512 m/sec, 918762 t fired, .
Time elapsed: 50 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 23 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-06
lola: result : false
lola: markings : 643201
lola: fired transitions : 1046302
lola: time used : 18.000000
lola: memory pages used : 4
lola: LAUNCH task # 54 (type EXCL) for 53 RwMutex-PT-r1000w0010-CTLFireability-15
lola: time limit : 253 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 3/253 1/32 RwMutex-PT-r1000w0010-CTLFireability-15 130366 m, 26073 m/sec, 235477 t fired, .
Time elapsed: 55 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 8/253 3/32 RwMutex-PT-r1000w0010-CTLFireability-15 326082 m, 39143 m/sec, 536513 t fired, .
Time elapsed: 60 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 13/253 4/32 RwMutex-PT-r1000w0010-CTLFireability-15 514778 m, 37739 m/sec, 839138 t fired, .
Time elapsed: 65 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 18/253 6/32 RwMutex-PT-r1000w0010-CTLFireability-15 745014 m, 46047 m/sec, 1559881 t fired, .
Time elapsed: 70 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 23/253 7/32 RwMutex-PT-r1000w0010-CTLFireability-15 913732 m, 33743 m/sec, 2564468 t fired, .
Time elapsed: 75 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 28/253 9/32 RwMutex-PT-r1000w0010-CTLFireability-15 1075831 m, 32419 m/sec, 3569529 t fired, .
Time elapsed: 80 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 33/253 11/32 RwMutex-PT-r1000w0010-CTLFireability-15 1234503 m, 31734 m/sec, 4558180 t fired, .
Time elapsed: 85 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 38/253 12/32 RwMutex-PT-r1000w0010-CTLFireability-15 1390982 m, 31295 m/sec, 5559155 t fired, .
Time elapsed: 90 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 43/253 14/32 RwMutex-PT-r1000w0010-CTLFireability-15 1543209 m, 30445 m/sec, 6547260 t fired, .
Time elapsed: 95 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 48/253 15/32 RwMutex-PT-r1000w0010-CTLFireability-15 1696232 m, 30604 m/sec, 7534313 t fired, .
Time elapsed: 100 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 53/253 17/32 RwMutex-PT-r1000w0010-CTLFireability-15 1849518 m, 30657 m/sec, 8513612 t fired, .
Time elapsed: 105 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 58/253 19/32 RwMutex-PT-r1000w0010-CTLFireability-15 1998616 m, 29819 m/sec, 9518601 t fired, .
Time elapsed: 110 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 63/253 20/32 RwMutex-PT-r1000w0010-CTLFireability-15 2149696 m, 30216 m/sec, 10481994 t fired, .
Time elapsed: 115 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 68/253 22/32 RwMutex-PT-r1000w0010-CTLFireability-15 2297874 m, 29635 m/sec, 11450839 t fired, .
Time elapsed: 120 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 73/253 23/32 RwMutex-PT-r1000w0010-CTLFireability-15 2447546 m, 29934 m/sec, 12415841 t fired, .
Time elapsed: 125 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 78/253 25/32 RwMutex-PT-r1000w0010-CTLFireability-15 2592673 m, 29025 m/sec, 13412660 t fired, .
Time elapsed: 130 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 83/253 26/32 RwMutex-PT-r1000w0010-CTLFireability-15 2734986 m, 28462 m/sec, 14378786 t fired, .
Time elapsed: 135 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 88/253 27/32 RwMutex-PT-r1000w0010-CTLFireability-15 2878941 m, 28791 m/sec, 15357299 t fired, .
Time elapsed: 140 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 93/253 29/32 RwMutex-PT-r1000w0010-CTLFireability-15 3020630 m, 28337 m/sec, 16356108 t fired, .
Time elapsed: 145 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 98/253 30/32 RwMutex-PT-r1000w0010-CTLFireability-15 3163946 m, 28663 m/sec, 17339824 t fired, .
Time elapsed: 150 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 103/253 31/32 RwMutex-PT-r1000w0010-CTLFireability-15 3305876 m, 28386 m/sec, 18311074 t fired, .
Time elapsed: 155 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 54 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 51 (type EXCL) for 50 RwMutex-PT-r1000w0010-CTLFireability-14
lola: time limit : 264 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-14
lola: result : false
lola: markings : 17054
lola: fired transitions : 55438
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 RwMutex-PT-r1000w0010-CTLFireability-13
lola: time limit : 286 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-13
lola: result : true
lola: markings : 4006
lola: fired transitions : 15034
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 RwMutex-PT-r1000w0010-CTLFireability-11
lola: time limit : 312 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 4/312 4/32 RwMutex-PT-r1000w0010-CTLFireability-11 449181 m, 89836 m/sec, 459035 t fired, .
Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 9/312 9/32 RwMutex-PT-r1000w0010-CTLFireability-11 1087784 m, 127720 m/sec, 1113937 t fired, .
Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 14/312 15/32 RwMutex-PT-r1000w0010-CTLFireability-11 1719091 m, 126261 m/sec, 1762925 t fired, .
Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 19/312 20/32 RwMutex-PT-r1000w0010-CTLFireability-11 2347213 m, 125624 m/sec, 2407060 t fired, .
Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 24/312 25/32 RwMutex-PT-r1000w0010-CTLFireability-11 2970922 m, 124741 m/sec, 3047593 t fired, .
Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 29/312 30/32 RwMutex-PT-r1000w0010-CTLFireability-11 3598259 m, 125467 m/sec, 3692881 t fired, .
Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 42 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 39 (type EXCL) for 38 RwMutex-PT-r1000w0010-CTLFireability-10
lola: time limit : 340 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-10
lola: result : true
lola: markings : 4884
lola: fired transitions : 34780
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 35 RwMutex-PT-r1000w0010-CTLFireability-09
lola: time limit : 378 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-09
lola: result : false
lola: markings : 1711
lola: fired transitions : 3827
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 33 (type EXCL) for 28 RwMutex-PT-r1000w0010-CTLFireability-08
lola: time limit : 425 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-08
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 28 RwMutex-PT-r1000w0010-CTLFireability-08
lola: time limit : 486 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 4/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 44073 m, 8814 m/sec, 44377 t fired, .
Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 9/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 53700 m, 1925 m/sec, 54035 t fired, .
Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 14/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 60392 m, 1338 m/sec, 60747 t fired, .
Time elapsed: 210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 19/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 66055 m, 1132 m/sec, 66426 t fired, .
Time elapsed: 215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 24/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 71242 m, 1037 m/sec, 71627 t fired, .
Time elapsed: 220 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 29/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 76243 m, 1000 m/sec, 76641 t fired, .
Time elapsed: 225 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 34/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 81311 m, 1013 m/sec, 81722 t fired, .
Time elapsed: 230 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 39/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 86160 m, 969 m/sec, 86583 t fired, .
Time elapsed: 235 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 44/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 91041 m, 976 m/sec, 91476 t fired, .
Time elapsed: 240 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 49/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 96228 m, 1037 m/sec, 96676 t fired, .
Time elapsed: 245 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 54/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 101449 m, 1044 m/sec, 101910 t fired, .
Time elapsed: 250 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 59/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 106703 m, 1050 m/sec, 107177 t fired, .
Time elapsed: 255 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 64/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 112323 m, 1124 m/sec, 112811 t fired, .
Time elapsed: 260 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 69/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 117971 m, 1129 m/sec, 118473 t fired, .
Time elapsed: 265 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 74/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 123691 m, 1144 m/sec, 124207 t fired, .
Time elapsed: 270 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 79/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 129776 m, 1217 m/sec, 130307 t fired, .
Time elapsed: 275 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 84/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 136223 m, 1289 m/sec, 136770 t fired, .
Time elapsed: 280 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 89/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 143051 m, 1365 m/sec, 143615 t fired, .
Time elapsed: 285 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 94/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 150282 m, 1446 m/sec, 150864 t fired, .
Time elapsed: 290 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 99/486 1/32 RwMutex-PT-r1000w0010-CTLFireability-08 158276 m, 1598 m/sec, 158878 t fired, .
Time elapsed: 295 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 104/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 166412 m, 1627 m/sec, 167034 t fired, .
Time elapsed: 300 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 109/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 175617 m, 1841 m/sec, 176262 t fired, .
Time elapsed: 305 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 114/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 185290 m, 1934 m/sec, 185959 t fired, .
Time elapsed: 310 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 119/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 197306 m, 2403 m/sec, 198005 t fired, .
Time elapsed: 315 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 124/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 210004 m, 2539 m/sec, 210741 t fired, .
Time elapsed: 320 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 129/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 214457 m, 890 m/sec, 215205 t fired, .
Time elapsed: 325 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 134/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 218910 m, 890 m/sec, 219669 t fired, .
Time elapsed: 330 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 139/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 223361 m, 890 m/sec, 224131 t fired, .
Time elapsed: 335 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 144/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 227741 m, 876 m/sec, 228522 t fired, .
Time elapsed: 340 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 149/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 232191 m, 890 m/sec, 232983 t fired, .
Time elapsed: 345 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 154/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 236646 m, 891 m/sec, 237449 t fired, .
Time elapsed: 350 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 159/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 241103 m, 891 m/sec, 241917 t fired, .
Time elapsed: 355 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 164/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 256282 m, 3035 m/sec, 257194 t fired, .
Time elapsed: 360 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 169/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 260731 m, 889 m/sec, 261654 t fired, .
Time elapsed: 365 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 174/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 265182 m, 890 m/sec, 266116 t fired, .
Time elapsed: 370 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 179/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 269636 m, 890 m/sec, 270581 t fired, .
Time elapsed: 375 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 184/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 274351 m, 943 m/sec, 275308 t fired, .
Time elapsed: 380 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 189/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 278794 m, 888 m/sec, 279762 t fired, .
Time elapsed: 385 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 194/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 283236 m, 888 m/sec, 284215 t fired, .
Time elapsed: 390 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 199/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 287674 m, 887 m/sec, 288664 t fired, .
Time elapsed: 395 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ 0 0 1 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 204/486 2/32 RwMutex-PT-r1000w0010-CTLFireability-08 292111 m, 887 m/sec, 293112 t fired, .
Time elapsed: 400 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 31 (type EXCL) for RwMutex-PT-r1000w0010-CTLFireability-08
lola: result : false
lola: markings : 295032
lola: fired transitions : 296041
lola: time used : 208.000000
lola: memory pages used : 2
lola: LAUNCH task # 26 (type EXCL) for 25 RwMutex-PT-r1000w0010-CTLFireability-07
lola: time limit : 532 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 1/532 1/32 RwMutex-PT-r1000w0010-CTLFireability-07 5628 m, 1125 m/sec, 37973 t fired, .
Time elapsed: 405 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 6/532 1/32 RwMutex-PT-r1000w0010-CTLFireability-07 18701 m, 2614 m/sec, 155512 t fired, .
Time elapsed: 410 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 11/532 1/32 RwMutex-PT-r1000w0010-CTLFireability-07 31703 m, 2600 m/sec, 279813 t fired, .
Time elapsed: 415 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 16/532 1/32 RwMutex-PT-r1000w0010-CTLFireability-07 44693 m, 2598 m/sec, 403749 t fired, .
Time elapsed: 420 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 21/532 1/32 RwMutex-PT-r1000w0010-CTLFireability-07 57665 m, 2594 m/sec, 529661 t fired, .
Time elapsed: 425 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 26/532 1/32 RwMutex-PT-r1000w0010-CTLFireability-07 70668 m, 2600 m/sec, 655065 t fired, .
Time elapsed: 430 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 31/532 1/32 RwMutex-PT-r1000w0010-CTLFireability-07 83659 m, 2598 m/sec, 777747 t fired, .
Time elapsed: 435 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 36/532 2/32 RwMutex-PT-r1000w0010-CTLFireability-07 96636 m, 2595 m/sec, 901781 t fired, .
Time elapsed: 440 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 41/532 2/32 RwMutex-PT-r1000w0010-CTLFireability-07 108620 m, 2396 m/sec, 1020048 t fired, .
Time elapsed: 445 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 46/532 2/32 RwMutex-PT-r1000w0010-CTLFireability-07 121309 m, 2537 m/sec, 1143643 t fired, .
Time elapsed: 450 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 51/532 2/32 RwMutex-PT-r1000w0010-CTLFireability-07 133559 m, 2450 m/sec, 1266394 t fired, .
Time elapsed: 455 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 56/532 2/32 RwMutex-PT-r1000w0010-CTLFireability-07 144734 m, 2235 m/sec, 1371672 t fired, .
Time elapsed: 460 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 61/532 2/32 RwMutex-PT-r1000w0010-CTLFireability-07 157157 m, 2484 m/sec, 1499839 t fired, .
Time elapsed: 465 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 66/532 2/32 RwMutex-PT-r1000w0010-CTLFireability-07 169658 m, 2500 m/sec, 1631494 t fired, .
Time elapsed: 470 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 71/532 3/32 RwMutex-PT-r1000w0010-CTLFireability-07 182010 m, 2470 m/sec, 1757982 t fired, .
Time elapsed: 475 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 76/532 3/32 RwMutex-PT-r1000w0010-CTLFireability-07 194139 m, 2425 m/sec, 1882995 t fired, .
Time elapsed: 480 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 81/532 3/32 RwMutex-PT-r1000w0010-CTLFireability-07 206723 m, 2516 m/sec, 2001137 t fired, .
Time elapsed: 485 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 86/532 3/32 RwMutex-PT-r1000w0010-CTLFireability-07 219186 m, 2492 m/sec, 2123276 t fired, .
Time elapsed: 490 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 91/532 3/32 RwMutex-PT-r1000w0010-CTLFireability-07 231774 m, 2517 m/sec, 2248462 t fired, .
Time elapsed: 495 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 96/532 3/32 RwMutex-PT-r1000w0010-CTLFireability-07 244110 m, 2467 m/sec, 2376344 t fired, .
Time elapsed: 500 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 101/532 3/32 RwMutex-PT-r1000w0010-CTLFireability-07 256539 m, 2485 m/sec, 2504426 t fired, .
Time elapsed: 505 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 106/532 3/32 RwMutex-PT-r1000w0010-CTLFireability-07 269105 m, 2513 m/sec, 2636514 t fired, .
Time elapsed: 510 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 111/532 4/32 RwMutex-PT-r1000w0010-CTLFireability-07 281717 m, 2522 m/sec, 2763439 t fired, .
Time elapsed: 515 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 116/532 4/32 RwMutex-PT-r1000w0010-CTLFireability-07 293729 m, 2402 m/sec, 2879424 t fired, .
Time elapsed: 520 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 121/532 4/32 RwMutex-PT-r1000w0010-CTLFireability-07 306284 m, 2511 m/sec, 3005316 t fired, .
Time elapsed: 525 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 126/532 4/32 RwMutex-PT-r1000w0010-CTLFireability-07 318968 m, 2536 m/sec, 3126520 t fired, .
Time elapsed: 530 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 131/532 4/32 RwMutex-PT-r1000w0010-CTLFireability-07 331562 m, 2518 m/sec, 3251991 t fired, .
Time elapsed: 535 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 136/532 4/32 RwMutex-PT-r1000w0010-CTLFireability-07 344061 m, 2499 m/sec, 3380164 t fired, .
Time elapsed: 540 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 141/532 4/32 RwMutex-PT-r1000w0010-CTLFireability-07 356492 m, 2486 m/sec, 3508390 t fired, .
Time elapsed: 545 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 146/532 5/32 RwMutex-PT-r1000w0010-CTLFireability-07 368947 m, 2491 m/sec, 3639140 t fired, .
Time elapsed: 550 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 151/532 5/32 RwMutex-PT-r1000w0010-CTLFireability-07 381359 m, 2482 m/sec, 3768605 t fired, .
Time elapsed: 555 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 156/532 5/32 RwMutex-PT-r1000w0010-CTLFireability-07 393694 m, 2467 m/sec, 3902367 t fired, .
Time elapsed: 560 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 161/532 5/32 RwMutex-PT-r1000w0010-CTLFireability-07 405194 m, 2300 m/sec, 4019296 t fired, .
Time elapsed: 565 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 166/532 5/32 RwMutex-PT-r1000w0010-CTLFireability-07 417651 m, 2491 m/sec, 4150503 t fired, .
Time elapsed: 570 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 171/532 5/32 RwMutex-PT-r1000w0010-CTLFireability-07 430044 m, 2478 m/sec, 4280228 t fired, .
Time elapsed: 575 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 176/532 5/32 RwMutex-PT-r1000w0010-CTLFireability-07 442439 m, 2479 m/sec, 4409547 t fired, .
Time elapsed: 580 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 181/532 5/32 RwMutex-PT-r1000w0010-CTLFireability-07 454942 m, 2500 m/sec, 4543181 t fired, .
Time elapsed: 585 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 186/532 6/32 RwMutex-PT-r1000w0010-CTLFireability-07 467417 m, 2495 m/sec, 4674071 t fired, .
Time elapsed: 590 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 191/532 6/32 RwMutex-PT-r1000w0010-CTLFireability-07 478201 m, 2156 m/sec, 4783556 t fired, .
Time elapsed: 595 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 197/532 6/32 RwMutex-PT-r1000w0010-CTLFireability-07 489593 m, 2278 m/sec, 4907625 t fired, .
Time elapsed: 601 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 202/532 6/32 RwMutex-PT-r1000w0010-CTLFireability-07 501561 m, 2393 m/sec, 5030677 t fired, .
Time elapsed: 606 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 207/532 6/32 RwMutex-PT-r1000w0010-CTLFireability-07 514298 m, 2547 m/sec, 5153227 t fired, .
Time elapsed: 611 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 212/532 6/32 RwMutex-PT-r1000w0010-CTLFireability-07 524534 m, 2047 m/sec, 5254199 t fired, .
Time elapsed: 616 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 217/532 6/32 RwMutex-PT-r1000w0010-CTLFireability-07 537087 m, 2510 m/sec, 5380866 t fired, .
Time elapsed: 621 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 222/532 6/32 RwMutex-PT-r1000w0010-CTLFireability-07 545605 m, 1703 m/sec, 5462384 t fired, .
Time elapsed: 626 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 227/532 6/32 RwMutex-PT-r1000w0010-CTLFireability-07 554063 m, 1691 m/sec, 5542877 t fired, .
Time elapsed: 631 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 232/532 6/32 RwMutex-PT-r1000w0010-CTLFireability-07 561726 m, 1532 m/sec, 5620804 t fired, .
Time elapsed: 636 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 237/532 7/32 RwMutex-PT-r1000w0010-CTLFireability-07 573866 m, 2428 m/sec, 5743318 t fired, .
Time elapsed: 641 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 242/532 7/32 RwMutex-PT-r1000w0010-CTLFireability-07 586259 m, 2478 m/sec, 5869157 t fired, .
Time elapsed: 646 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 247/532 7/32 RwMutex-PT-r1000w0010-CTLFireability-07 598700 m, 2488 m/sec, 5994854 t fired, .
Time elapsed: 651 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 252/532 7/32 RwMutex-PT-r1000w0010-CTLFireability-07 609611 m, 2182 m/sec, 6104370 t fired, .
Time elapsed: 656 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r1000w0010-CTLFireability-00: AGAF false state space /EFEG
RwMutex-PT-r1000w0010-CTLFireability-06: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-08: CONJ false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-09: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-10: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-12: CTL false CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r1000w0010-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r1000w0010-CTLFireability-01: DISJ 0 1 0 0 3 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r1000w0010-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r1000w0010-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 257/532 7/32 RwMutex-PT-r1000w0010-CTLFireability-07 619761 m, 2030 m/sec, 6211155 t fired, .
Time elapsed: 661 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 371 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RwMutex-PT-r1000w0010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is RwMutex-PT-r1000w0010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r358-smll-167891807400186"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RwMutex-PT-r1000w0010.tgz
mv RwMutex-PT-r1000w0010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;