About the Execution of LoLA for RwMutex-PT-r0100w0010
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16224.888 | 204306.00 | 203308.00 | 6227.60 | FFF??TTT?TTTFTFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r358-smll-167891807300170.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is RwMutex-PT-r0100w0010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r358-smll-167891807300170
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 696K
-rw-r--r-- 1 mcc users 5.6K Feb 25 22:39 CTLCardinality.txt
-rw-r--r-- 1 mcc users 56K Feb 25 22:39 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K Feb 25 22:38 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K Feb 25 22:38 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:49 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:49 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 16:49 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 16:49 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 22:40 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 134K Feb 25 22:40 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 22:39 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 100K Feb 25 22:39 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:49 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:49 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 11 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 215K Mar 5 18:23 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-00
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-01
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-02
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-03
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-04
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-05
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-06
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-07
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-08
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-09
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-10
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-11
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-12
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-13
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-14
FORMULA_NAME RwMutex-PT-r0100w0010-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678972450524
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RwMutex-PT-r0100w0010
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT RwMutex-PT-r0100w0010
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA RwMutex-PT-r0100w0010-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0100w0010-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0100w0010-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0100w0010-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0100w0010-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0100w0010-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0100w0010-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0100w0010-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0100w0010-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0100w0010-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0100w0010-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0100w0010-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RwMutex-PT-r0100w0010-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678972654830
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: ASSUMEDDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:715
lola: LAUNCH task # 64 (type SKEL/SRCH) for 0 RwMutex-PT-r0100w0010-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 64 (type SKEL/SRCH) for RwMutex-PT-r0100w0010-CTLFireability-00
lola: result : true
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: ASSUMEDDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 65 (type SKEL/SRCH) for 19 RwMutex-PT-r0100w0010-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 65 (type SKEL/SRCH) for RwMutex-PT-r0100w0010-CTLFireability-05
lola: result : true
lola: markings : 2
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: ASSUMEDDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 66 (type SKEL/SRCH) for 54 RwMutex-PT-r0100w0010-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 66 (type SKEL/SRCH) for RwMutex-PT-r0100w0010-CTLFireability-14
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 11 (type EXCL) for 10 RwMutex-PT-r0100w0010-CTLFireability-02
lola: time limit : 143 sec
lola: memory limit: 32 pages
lola: planning for (null) stopped (result already fixed).
lola: planning for (null) stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 11 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-02
lola: result : false
lola: markings : 13
lola: fired transitions : 14
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 39 RwMutex-PT-r0100w0010-CTLFireability-09
lola: time limit : 149 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: ASSUMEDDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 67 (type SKEL/SRCH) for 48 RwMutex-PT-r0100w0010-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 67 (type SKEL/SRCH) for RwMutex-PT-r0100w0010-CTLFireability-12
lola: result : false
lola: markings : 3
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:715
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 40 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-09
lola: result : true
lola: markings : 5061
lola: fired transitions : 24785
lola: time used : 0.000000
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 3 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-00
lola: result : true
lola: markings : 2
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: FINISHED task # 62 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-15
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lola: markings : 111
lola: fired transitions : 361
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lola: result : false
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lola: result : true
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lola: fired transitions : 444
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: RELEASE
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lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-05: DISJ true skeleton: CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
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RwMutex-PT-r0100w0010-CTLFireability-14: DISJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 5/299 3/32 RwMutex-PT-r0100w0010-CTLFireability-04 622883 m, 124576 m/sec, 4128222 t fired, .
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RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 10/299 6/32 RwMutex-PT-r0100w0010-CTLFireability-04 1289655 m, 133354 m/sec, 9102312 t fired, .
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RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
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17 CTL EXCL 15/299 9/32 RwMutex-PT-r0100w0010-CTLFireability-04 1953013 m, 132671 m/sec, 13833605 t fired, .
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RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
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17 CTL EXCL 20/299 12/32 RwMutex-PT-r0100w0010-CTLFireability-04 2551017 m, 119600 m/sec, 18497338 t fired, .
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17 CTL EXCL 25/299 14/32 RwMutex-PT-r0100w0010-CTLFireability-04 3182920 m, 126380 m/sec, 23144521 t fired, .
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17 CTL EXCL 30/299 17/32 RwMutex-PT-r0100w0010-CTLFireability-04 3842411 m, 131898 m/sec, 27893867 t fired, .
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17 CTL EXCL 35/299 20/32 RwMutex-PT-r0100w0010-CTLFireability-04 4488917 m, 129301 m/sec, 32589433 t fired, .
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17 CTL EXCL 40/299 22/32 RwMutex-PT-r0100w0010-CTLFireability-04 5016436 m, 105503 m/sec, 36763903 t fired, .
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RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0100w0010-CTLFireability-00: CONJ 0 1 0 0 3 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-14: DISJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 55/299 29/32 RwMutex-PT-r0100w0010-CTLFireability-04 6619821 m, 110189 m/sec, 49251356 t fired, .
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RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-05: DISJ true skeleton: CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0100w0010-CTLFireability-00: CONJ 0 1 0 0 3 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-14: DISJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 60/299 31/32 RwMutex-PT-r0100w0010-CTLFireability-04 7114039 m, 98843 m/sec, 53319859 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-05: DISJ true skeleton: CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0100w0010-CTLFireability-00: CONJ 0 1 0 0 3 0 0 0
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RwMutex-PT-r0100w0010-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-14: DISJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-05: DISJ true skeleton: CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-11: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-14: DISJ false DISJ
RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0100w0010-CTLFireability-00: CONJ 0 1 0 0 3 0 0 0
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RwMutex-PT-r0100w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 5/441 5/32 RwMutex-PT-r0100w0010-CTLFireability-08 891342 m, 178268 m/sec, 2224112 t fired, .
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RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-05: DISJ true skeleton: CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-11: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-14: DISJ false DISJ
RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0100w0010-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 10/441 8/32 RwMutex-PT-r0100w0010-CTLFireability-08 1742125 m, 170156 m/sec, 4417966 t fired, .
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RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-05: DISJ true skeleton: CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-11: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-14: DISJ false DISJ
RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0100w0010-CTLFireability-00: CONJ 0 1 0 0 3 0 0 0
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RwMutex-PT-r0100w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 15/441 12/32 RwMutex-PT-r0100w0010-CTLFireability-08 2571138 m, 165802 m/sec, 6598100 t fired, .
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RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-05: DISJ true skeleton: CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-11: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-14: DISJ false DISJ
RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0100w0010-CTLFireability-00: CONJ 0 1 0 0 3 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 20/441 16/32 RwMutex-PT-r0100w0010-CTLFireability-08 3400001 m, 165772 m/sec, 8784038 t fired, .
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RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-05: DISJ true skeleton: CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-11: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-14: DISJ false DISJ
RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RwMutex-PT-r0100w0010-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 25/441 20/32 RwMutex-PT-r0100w0010-CTLFireability-08 4230896 m, 166179 m/sec, 10964017 t fired, .
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RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-05: DISJ true skeleton: CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-11: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-14: DISJ false DISJ
RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
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RwMutex-PT-r0100w0010-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 30/441 23/32 RwMutex-PT-r0100w0010-CTLFireability-08 5043005 m, 162421 m/sec, 13134016 t fired, .
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RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-05: DISJ true skeleton: CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-11: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-14: DISJ false DISJ
RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
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37 CTL EXCL 35/441 27/32 RwMutex-PT-r0100w0010-CTLFireability-08 5845205 m, 160440 m/sec, 15291267 t fired, .
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RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
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RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-11: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-14: DISJ false DISJ
RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
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37 CTL EXCL 40/441 30/32 RwMutex-PT-r0100w0010-CTLFireability-08 6644456 m, 159850 m/sec, 17445851 t fired, .
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RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
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RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-11: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-13: CTL true CTL model checker
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RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
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RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-05: DISJ true skeleton: CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-11: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-14: DISJ false DISJ
RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 70/498 28/32 RwMutex-PT-r0100w0010-CTLFireability-03 6571405 m, 50903 m/sec, 48904218 t fired, .
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RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-05: DISJ true skeleton: CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-11: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-14: DISJ false DISJ
RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0100w0010-CTLFireability-00: CONJ 0 1 0 0 3 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 75/498 29/32 RwMutex-PT-r0100w0010-CTLFireability-03 6807106 m, 47140 m/sec, 50816457 t fired, .
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RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-05: DISJ true skeleton: CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-11: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-14: DISJ false DISJ
RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0100w0010-CTLFireability-00: CONJ 0 1 0 0 3 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 80/498 30/32 RwMutex-PT-r0100w0010-CTLFireability-03 7083176 m, 55214 m/sec, 53062907 t fired, .
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RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-05: DISJ true skeleton: CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-11: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-14: DISJ false DISJ
RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0100w0010-CTLFireability-00: CONJ 0 1 0 0 3 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 85/498 31/32 RwMutex-PT-r0100w0010-CTLFireability-03 7308527 m, 45070 m/sec, 54964916 t fired, .
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lola: CANCELED task # 14 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-03 (memory limit exceeded)
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RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-05: DISJ true skeleton: CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-11: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-14: DISJ false DISJ
RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RwMutex-PT-r0100w0010-CTLFireability-00: CONJ 0 1 0 0 3 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
RwMutex-PT-r0100w0010-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
RwMutex-PT-r0100w0010-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 8 (type EXCL) for 7 RwMutex-PT-r0100w0010-CTLFireability-01
lola: time limit : 566 sec
lola: memory limit: 32 pages
lola: FINISHED task # 8 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-01
lola: result : false
lola: markings : 158
lola: fired transitions : 482
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 42 RwMutex-PT-r0100w0010-CTLFireability-10
lola: time limit : 679 sec
lola: memory limit: 32 pages
lola: FINISHED task # 43 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-10
lola: result : true
lola: markings : 12
lola: fired transitions : 121
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 68 (type EXCL) for 0 RwMutex-PT-r0100w0010-CTLFireability-00
lola: time limit : 849 sec
lola: memory limit: 32 pages
lola: FINISHED task # 68 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-00
lola: result : true
lola: markings : 2
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 49 (type EXCL) for 48 RwMutex-PT-r0100w0010-CTLFireability-12
lola: time limit : 1132 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-12
lola: result : false
lola: markings : 2
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 29 RwMutex-PT-r0100w0010-CTLFireability-07
lola: time limit : 1698 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-07
lola: result : false
lola: markings : 11
lola: fired transitions : 23
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 29 RwMutex-PT-r0100w0010-CTLFireability-07
lola: time limit : 3397 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for RwMutex-PT-r0100w0010-CTLFireability-07
lola: result : true
lola: markings : 42
lola: fired transitions : 3415
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RwMutex-PT-r0100w0010-CTLFireability-00: CONJ false tscc_search
RwMutex-PT-r0100w0010-CTLFireability-01: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-02: CTL false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-03: CTL unknown AGGR
RwMutex-PT-r0100w0010-CTLFireability-04: CTL unknown AGGR
RwMutex-PT-r0100w0010-CTLFireability-05: DISJ true skeleton: CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-06: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-07: DISJ true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-08: CTL unknown AGGR
RwMutex-PT-r0100w0010-CTLFireability-09: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-10: AGEF true tscc_search
RwMutex-PT-r0100w0010-CTLFireability-11: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-12: AFAG false CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-13: CTL true CTL model checker
RwMutex-PT-r0100w0010-CTLFireability-14: DISJ false DISJ
RwMutex-PT-r0100w0010-CTLFireability-15: CTL true CTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RwMutex-PT-r0100w0010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is RwMutex-PT-r0100w0010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r358-smll-167891807300170"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RwMutex-PT-r0100w0010.tgz
mv RwMutex-PT-r0100w0010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;