Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199900666.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ResAllocation-PT-R003C002, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199900666
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 532K
-rw-r--r-- 1 mcc users 8.0K Feb 25 15:17 CTLCardinality.txt
-rw-r--r-- 1 mcc users 85K Feb 25 15:17 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 25 15:17 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 25 15:17 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 16:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Feb 25 15:17 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 165K Feb 25 15:17 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.5K Feb 25 15:17 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 71K Feb 25 15:17 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 9 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 14K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-00
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-01
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-02
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-03
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-04
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-05
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-06
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-07
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-08
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-09
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-10
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-11
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-12
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-13
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-14
FORMULA_NAME ResAllocation-PT-R003C002-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679054347413

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ResAllocation-PT-R003C002
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-17 11:59:09] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 11:59:09] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 11:59:09] [INFO ] Load time of PNML (sax parser for PT used): 22 ms
[2023-03-17 11:59:09] [INFO ] Transformed 12 places.
[2023-03-17 11:59:09] [INFO ] Transformed 8 transitions.
[2023-03-17 11:59:09] [INFO ] Found NUPN structural information;
[2023-03-17 11:59:09] [INFO ] Parsed PT model containing 12 places and 8 transitions and 30 arcs in 80 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Initial state reduction rules removed 2 formulas.
FORMULA ResAllocation-PT-R003C002-CTLFireability-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ResAllocation-PT-R003C002-CTLFireability-10 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 12 out of 12 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 8/8 transitions.
Applied a total of 0 rules in 9 ms. Remains 12 /12 variables (removed 0) and now considering 8/8 (removed 0) transitions.
// Phase 1: matrix 8 rows 12 cols
[2023-03-17 11:59:09] [INFO ] Computed 6 place invariants in 6 ms
[2023-03-17 11:59:09] [INFO ] Implicit Places using invariants in 154 ms returned []
[2023-03-17 11:59:09] [INFO ] Invariant cache hit.
[2023-03-17 11:59:09] [INFO ] Implicit Places using invariants and state equation in 35 ms returned []
Implicit Place search using SMT with State Equation took 217 ms to find 0 implicit places.
[2023-03-17 11:59:09] [INFO ] Invariant cache hit.
[2023-03-17 11:59:09] [INFO ] Dead Transitions using invariants and state equation in 58 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 285 ms. Remains : 12/12 places, 8/8 transitions.
Support contains 12 out of 12 places after structural reductions.
[2023-03-17 11:59:09] [INFO ] Flatten gal took : 13 ms
[2023-03-17 11:59:09] [INFO ] Flatten gal took : 4 ms
[2023-03-17 11:59:09] [INFO ] Input system was already deterministic with 8 transitions.
Incomplete random walk after 10000 steps, including 1552 resets, run finished after 407 ms. (steps per millisecond=24 ) properties (out of 26) seen :19
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 86 ms. (steps per millisecond=116 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 909 resets, run finished after 100 ms. (steps per millisecond=100 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10000 steps, including 364 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10000 steps, including 599 resets, run finished after 55 ms. (steps per millisecond=181 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 865 resets, run finished after 81 ms. (steps per millisecond=123 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 909 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 909 resets, run finished after 60 ms. (steps per millisecond=166 ) properties (out of 7) seen :0
Running SMT prover for 7 properties.
[2023-03-17 11:59:10] [INFO ] Invariant cache hit.
[2023-03-17 11:59:10] [INFO ] [Real]Absence check using 6 positive place invariants in 2 ms returned sat
[2023-03-17 11:59:10] [INFO ] After 8ms SMT Verify possible using state equation in real domain returned unsat :6 sat :1
[2023-03-17 11:59:10] [INFO ] After 12ms SMT Verify possible using trap constraints in real domain returned unsat :6 sat :1
Attempting to minimize the solution found.
Minimization took 4 ms.
[2023-03-17 11:59:10] [INFO ] After 64ms SMT Verify possible using all constraints in real domain returned unsat :6 sat :1
Fused 7 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 1 ms.
Support contains 2 out of 12 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 12/12 places, 8/8 transitions.
Free-agglomeration rule applied 1 times.
Iterating global reduction 0 with 1 rules applied. Total rules applied 1 place count 12 transition count 7
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 11 transition count 7
Free-agglomeration rule (complex) applied 1 times.
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 11 transition count 6
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 5 place count 9 transition count 6
Applied a total of 5 rules in 6 ms. Remains 9 /12 variables (removed 3) and now considering 6/8 (removed 2) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 6 ms. Remains : 9/12 places, 6/8 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=1111 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=833 ) properties (out of 1) seen :0
Probably explored full state space saw : 7 states, properties seen :0
Probabilistic random walk after 17 steps, saw 7 distinct states, run finished after 14 ms. (steps per millisecond=1 ) properties seen :0
Explored full state space saw : 7 states, properties seen :0
Exhaustive walk after 17 steps, saw 7 distinct states, run finished after 1 ms. (steps per millisecond=17 ) properties seen :0
Successfully simplified 7 atomic propositions for a total of 14 simplifications.
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 3 ms
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:59:10] [INFO ] Input system was already deterministic with 8 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 12/12 places, 8/8 transitions.
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:59:10] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 12/12 places, 8/8 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 0 with 5 rules applied. Total rules applied 5 place count 9 transition count 6
Applied a total of 5 rules in 1 ms. Remains 9 /12 variables (removed 3) and now considering 6/8 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 9/12 places, 6/8 transitions.
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Input system was already deterministic with 6 transitions.
Finished random walk after 2 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=2 )
FORMULA ResAllocation-PT-R003C002-CTLFireability-01 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 12/12 places, 8/8 transitions.
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 12/12 places, 8/8 transitions.
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 12/12 places, 8/8 transitions.
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 12/12 places, 8/8 transitions.
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 0 ms
[2023-03-17 11:59:10] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 12/12 places, 8/8 transitions.
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 12/12 places, 8/8 transitions.
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 0 ms
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 0 ms
[2023-03-17 11:59:10] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 12/12 places, 8/8 transitions.
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 0 ms
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 0 ms
[2023-03-17 11:59:10] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 12/12 places, 8/8 transitions.
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 12/12 places, 8/8 transitions.
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 12/12 places, 8/8 transitions.
Applied a total of 0 rules in 1 ms. Remains 12 /12 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 12/12 places, 8/8 transitions.
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 12/12 places, 8/8 transitions.
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 1 ms
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 0 ms
[2023-03-17 11:59:10] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 12/12 places, 8/8 transitions.
Applied a total of 0 rules in 0 ms. Remains 12 /12 variables (removed 0) and now considering 8/8 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 12/12 places, 8/8 transitions.
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 0 ms
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 0 ms
[2023-03-17 11:59:10] [INFO ] Input system was already deterministic with 8 transitions.
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:59:10] [INFO ] Flatten gal took : 2 ms
[2023-03-17 11:59:10] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-17 11:59:10] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 12 places, 8 transitions and 30 arcs took 1 ms.
Total runtime 1784 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ResAllocation-PT-R003C002
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA ResAllocation-PT-R003C002-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C002-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C002-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C002-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C002-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C002-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C002-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C002-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C002-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C002-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C002-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C002-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C002-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679054352076

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:227
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: LAUNCH task # 11 (type EXCL) for 0 ResAllocation-PT-R003C002-CTLFireability-00
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: FINISHED task # 11 (type EXCL) for ResAllocation-PT-R003C002-CTLFireability-00
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: planning for (null) stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 23 (type EXCL) for 22 ResAllocation-PT-R003C002-CTLFireability-03
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 23 (type EXCL) for ResAllocation-PT-R003C002-CTLFireability-03
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 41 (type EXCL) for 40 ResAllocation-PT-R003C002-CTLFireability-11
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 41 (type EXCL) for ResAllocation-PT-R003C002-CTLFireability-11
lola: result : false
lola: markings : 6
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH INITIAL
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 38 (type CNST) for 37 ResAllocation-PT-R003C002-CTLFireability-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH task # 44 (type EXCL) for 43 ResAllocation-PT-R003C002-CTLFireability-12
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 38 (type CNST) for ResAllocation-PT-R003C002-CTLFireability-08
lola: result : true
lola: FINISHED task # 44 (type EXCL) for ResAllocation-PT-R003C002-CTLFireability-12
lola: result : true
lola: markings : 18
lola: fired transitions : 86
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 ResAllocation-PT-R003C002-CTLFireability-06
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for ResAllocation-PT-R003C002-CTLFireability-06
lola: result : false
lola: markings : 20
lola: fired transitions : 88
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 ResAllocation-PT-R003C002-CTLFireability-05
lola: time limit : 399 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for ResAllocation-PT-R003C002-CTLFireability-05
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 19 ResAllocation-PT-R003C002-CTLFireability-02
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 20 (type EXCL) for ResAllocation-PT-R003C002-CTLFireability-02
lola: result : true
lola: markings : 15
lola: fired transitions : 34
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 26 (type EXCL) for 25 ResAllocation-PT-R003C002-CTLFireability-04
lola: time limit : 599 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 26 (type EXCL) for ResAllocation-PT-R003C002-CTLFireability-04
lola: result : true
lola: markings : 8
lola: fired transitions : 15
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 53 (type EXCL) for 52 ResAllocation-PT-R003C002-CTLFireability-15
lola: time limit : 719 sec
lola: memory limit: 32 pages
lola: FINISHED task # 53 (type EXCL) for ResAllocation-PT-R003C002-CTLFireability-15
lola: result : true
lola: markings : 15
lola: fired transitions : 16
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 50 (type EXCL) for 49 ResAllocation-PT-R003C002-CTLFireability-14
lola: time limit : 899 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for ResAllocation-PT-R003C002-CTLFireability-14
lola: result : false
lola: markings : 7
lola: fired transitions : 14
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 35 (type EXCL) for 34 ResAllocation-PT-R003C002-CTLFireability-07
lola: time limit : 1199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for ResAllocation-PT-R003C002-CTLFireability-07
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 3 (type EXCL) for 0 ResAllocation-PT-R003C002-CTLFireability-00
lola: time limit : 1799 sec
lola: memory limit: 32 pages
lola: FINISHED task # 3 (type EXCL) for ResAllocation-PT-R003C002-CTLFireability-00
lola: result : true
lola: markings : 9
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 47 (type EXCL) for 46 ResAllocation-PT-R003C002-CTLFireability-13
lola: time limit : 3599 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for ResAllocation-PT-R003C002-CTLFireability-13
lola: result : false
lola: markings : 7
lola: fired transitions : 24
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C002-CTLFireability-00: CONJ true CONJ
ResAllocation-PT-R003C002-CTLFireability-02: CTL true CTL model checker
ResAllocation-PT-R003C002-CTLFireability-03: EXEF true state space /EXEF
ResAllocation-PT-R003C002-CTLFireability-04: CTL true CTL model checker
ResAllocation-PT-R003C002-CTLFireability-05: CTL true CTL model checker
ResAllocation-PT-R003C002-CTLFireability-06: CTL false CTL model checker
ResAllocation-PT-R003C002-CTLFireability-07: CTL false CTL model checker
ResAllocation-PT-R003C002-CTLFireability-08: INITIAL true preprocessing
ResAllocation-PT-R003C002-CTLFireability-11: CTL false CTL model checker
ResAllocation-PT-R003C002-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C002-CTLFireability-13: CTL false CTL model checker
ResAllocation-PT-R003C002-CTLFireability-14: CTL false CTL model checker
ResAllocation-PT-R003C002-CTLFireability-15: CTL true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R003C002"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ResAllocation-PT-R003C002, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199900666"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R003C002.tgz
mv ResAllocation-PT-R003C002 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;