fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r327-tall-167889199300226
Last Updated
May 14, 2023

About the Execution of LoLa+red for RERS2020-PT-pb102

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16214.527 3600000.00 4011858.00 23482.90 F??F???????????? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199300226.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RERS2020-PT-pb102, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199300226
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 71M
-rw-r--r-- 1 mcc users 8.4K Feb 26 08:36 CTLCardinality.txt
-rw-r--r-- 1 mcc users 95K Feb 26 08:36 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.5K Feb 26 08:34 CTLFireability.txt
-rw-r--r-- 1 mcc users 65K Feb 26 08:34 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:40 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:40 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:40 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:40 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.8K Feb 26 08:44 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 71K Feb 26 08:44 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 26 08:42 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 84K Feb 26 08:42 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:40 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:40 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 70M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS2020-PT-pb102-CTLFireability-00
FORMULA_NAME RERS2020-PT-pb102-CTLFireability-01
FORMULA_NAME RERS2020-PT-pb102-CTLFireability-02
FORMULA_NAME RERS2020-PT-pb102-CTLFireability-03
FORMULA_NAME RERS2020-PT-pb102-CTLFireability-04
FORMULA_NAME RERS2020-PT-pb102-CTLFireability-05
FORMULA_NAME RERS2020-PT-pb102-CTLFireability-06
FORMULA_NAME RERS2020-PT-pb102-CTLFireability-07
FORMULA_NAME RERS2020-PT-pb102-CTLFireability-08
FORMULA_NAME RERS2020-PT-pb102-CTLFireability-09
FORMULA_NAME RERS2020-PT-pb102-CTLFireability-10
FORMULA_NAME RERS2020-PT-pb102-CTLFireability-11
FORMULA_NAME RERS2020-PT-pb102-CTLFireability-12
FORMULA_NAME RERS2020-PT-pb102-CTLFireability-13
FORMULA_NAME RERS2020-PT-pb102-CTLFireability-14
FORMULA_NAME RERS2020-PT-pb102-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679014840246

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS2020-PT-pb102
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-17 01:00:41] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-17 01:00:41] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-17 01:00:44] [INFO ] Load time of PNML (sax parser for PT used): 2361 ms
[2023-03-17 01:00:44] [INFO ] Transformed 1276 places.
[2023-03-17 01:00:44] [INFO ] Transformed 125387 transitions.
[2023-03-17 01:00:44] [INFO ] Found NUPN structural information;
[2023-03-17 01:00:44] [INFO ] Parsed PT model containing 1276 places and 125387 transitions and 499222 arcs in 2859 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 31 ms.
Ensure Unique test removed 2767 transitions
Reduce redundant transitions removed 2767 transitions.
Support contains 227 out of 1276 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1276/1276 places, 122620/122620 transitions.
Ensure Unique test removed 6 places
Iterating post reduction 0 with 6 rules applied. Total rules applied 6 place count 1270 transition count 122620
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 9 place count 1267 transition count 122617
Iterating global reduction 1 with 3 rules applied. Total rules applied 12 place count 1267 transition count 122617
Applied a total of 12 rules in 650 ms. Remains 1267 /1276 variables (removed 9) and now considering 122617/122620 (removed 3) transitions.
[2023-03-17 01:00:46] [INFO ] Flow matrix only has 94416 transitions (discarded 28201 similar events)
// Phase 1: matrix 94416 rows 1267 cols
[2023-03-17 01:00:46] [INFO ] Computed 7 place invariants in 667 ms
[2023-03-17 01:00:51] [INFO ] Implicit Places using invariants in 5780 ms returned []
Implicit Place search using SMT only with invariants took 5848 ms to find 0 implicit places.
[2023-03-17 01:00:51] [INFO ] Flow matrix only has 94416 transitions (discarded 28201 similar events)
[2023-03-17 01:00:51] [INFO ] Invariant cache hit.
[2023-03-17 01:01:22] [INFO ] Performed 93307/122617 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-17 01:01:31] [INFO ] Dead Transitions using invariants and state equation in 39571 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 1267/1276 places, 122617/122620 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 46095 ms. Remains : 1267/1276 places, 122617/122620 transitions.
Support contains 227 out of 1267 places after structural reductions.
[2023-03-17 01:01:35] [INFO ] Flatten gal took : 3223 ms
[2023-03-17 01:01:38] [INFO ] Flatten gal took : 3104 ms
[2023-03-17 01:01:45] [INFO ] Input system was already deterministic with 122617 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1208 ms. (steps per millisecond=8 ) properties (out of 118) seen :2
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=6 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=11 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 116) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 116) seen :0
Interrupted probabilistic random walk after 7554 steps, run timeout after 3003 ms. (steps per millisecond=2 ) properties seen :{}
Probabilistic random walk after 7554 steps, saw 5617 distinct states, run finished after 3004 ms. (steps per millisecond=2 ) properties seen :0
Running SMT prover for 116 properties.
[2023-03-17 01:01:50] [INFO ] Flow matrix only has 94416 transitions (discarded 28201 similar events)
[2023-03-17 01:01:50] [INFO ] Invariant cache hit.
[2023-03-17 01:01:53] [INFO ] [Real]Absence check using 7 positive place invariants in 15 ms returned sat
[2023-03-17 01:02:15] [INFO ] After 22274ms SMT Verify possible using state equation in real domain returned unsat :2 sat :5 real:108
[2023-03-17 01:02:16] [INFO ] State equation strengthened by 3015 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-17 01:02:16] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-17 01:02:16] [INFO ] After 26050ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 116 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 219 out of 1267 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1267/1267 places, 122617/122617 transitions.
Drop transitions removed 2004 transitions
Reduce isomorphic transitions removed 2004 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2006 rules applied. Total rules applied 2006 place count 1267 transition count 120611
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 2009 place count 1265 transition count 120610
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 2 Pre rules applied. Total rules applied 2009 place count 1265 transition count 120608
Deduced a syphon composed of 2 places in 53 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 2013 place count 1263 transition count 120608
Performed 36 Post agglomeration using F-continuation condition.Transition count delta: 36
Deduced a syphon composed of 36 places in 51 ms
Reduce places removed 36 places and 0 transitions.
Iterating global reduction 2 with 72 rules applied. Total rules applied 2085 place count 1227 transition count 120572
Ensure Unique test removed 1979 transitions
Reduce isomorphic transitions removed 1979 transitions.
Iterating post reduction 2 with 1979 rules applied. Total rules applied 4064 place count 1227 transition count 118593
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 47 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 4 rules applied. Total rules applied 4068 place count 1225 transition count 118591
Drop transitions removed 2 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 3 with 3 rules applied. Total rules applied 4071 place count 1225 transition count 118588
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: -1
Deduced a syphon composed of 5 places in 48 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 4 with 10 rules applied. Total rules applied 4081 place count 1220 transition count 118589
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 4 with 4 rules applied. Total rules applied 4085 place count 1220 transition count 118585
Free-agglomeration rule applied 37 times.
Iterating global reduction 5 with 37 rules applied. Total rules applied 4122 place count 1220 transition count 118548
Reduce places removed 37 places and 0 transitions.
Ensure Unique test removed 36 transitions
Reduce isomorphic transitions removed 36 transitions.
Iterating post reduction 5 with 73 rules applied. Total rules applied 4195 place count 1183 transition count 118512
Free-agglomeration rule (complex) applied 69 times with reduction of 3236 identical transitions.
Iterating global reduction 6 with 69 rules applied. Total rules applied 4264 place count 1183 transition count 130570
Reduce places removed 69 places and 0 transitions.
Drop transitions removed 39 transitions
Ensure Unique test removed 2188 transitions
Reduce isomorphic transitions removed 2227 transitions.
Iterating post reduction 6 with 2296 rules applied. Total rules applied 6560 place count 1114 transition count 128343
Applied a total of 6560 rules in 5800 ms. Remains 1114 /1267 variables (removed 153) and now considering 128343/122617 (removed -5726) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 5809 ms. Remains : 1114/1267 places, 128343/122617 transitions.
Incomplete random walk after 10000 steps, including 3 resets, run finished after 1131 ms. (steps per millisecond=8 ) properties (out of 114) seen :1
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=6 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=14 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Interrupted probabilistic random walk after 8431 steps, run timeout after 3002 ms. (steps per millisecond=2 ) properties seen :{}
Probabilistic random walk after 8431 steps, saw 6400 distinct states, run finished after 3002 ms. (steps per millisecond=2 ) properties seen :0
Running SMT prover for 113 properties.
[2023-03-17 01:02:27] [INFO ] Flow matrix only has 101520 transitions (discarded 26823 similar events)
// Phase 1: matrix 101520 rows 1114 cols
[2023-03-17 01:02:27] [INFO ] Computed 7 place invariants in 478 ms
[2023-03-17 01:02:29] [INFO ] [Real]Absence check using 7 positive place invariants in 14 ms returned sat
[2023-03-17 01:02:52] [INFO ] After 22831ms SMT Verify possible using state equation in real domain returned unsat :0 sat :2 real:104
[2023-03-17 01:02:53] [INFO ] State equation strengthened by 3459 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-17 01:02:53] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-17 01:02:53] [INFO ] After 25800ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Fused 113 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 219 out of 1114 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1114/1114 places, 128343/128343 transitions.
Applied a total of 0 rules in 560 ms. Remains 1114 /1114 variables (removed 0) and now considering 128343/128343 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 560 ms. Remains : 1114/1114 places, 128343/128343 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1382 ms. (steps per millisecond=7 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=7 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=14 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=14 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=9 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=12 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=14 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=14 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=14 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=14 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=14 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=14 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=20 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=14 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=14 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=14 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=14 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 100 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=14 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=14 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=16 ) properties (out of 113) seen :0
Incomplete Best-First random walk after 101 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=14 ) properties (out of 113) seen :0
Interrupted probabilistic random walk after 6710 steps, run timeout after 3001 ms. (steps per millisecond=2 ) properties seen :{}
Probabilistic random walk after 6710 steps, saw 5226 distinct states, run finished after 3001 ms. (steps per millisecond=2 ) properties seen :0
Running SMT prover for 113 properties.
[2023-03-17 01:02:58] [INFO ] Flow matrix only has 101520 transitions (discarded 26823 similar events)
[2023-03-17 01:02:58] [INFO ] Invariant cache hit.
[2023-03-17 01:03:00] [INFO ] [Real]Absence check using 7 positive place invariants in 10 ms returned sat
[2023-03-17 01:03:23] [INFO ] After 25020ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:104
[2023-03-17 01:03:25] [INFO ] [Nat]Absence check using 7 positive place invariants in 13 ms returned sat
[2023-03-17 01:03:48] [INFO ] After 21413ms SMT Verify possible using state equation in natural domain returned unsat :8 sat :104
[2023-03-17 01:03:49] [INFO ] State equation strengthened by 3459 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-17 01:03:49] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-17 01:03:49] [INFO ] After 25889ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:104
Fused 113 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 195 out of 1114 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1114/1114 places, 128343/128343 transitions.
Applied a total of 0 rules in 560 ms. Remains 1114 /1114 variables (removed 0) and now considering 128343/128343 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 562 ms. Remains : 1114/1114 places, 128343/128343 transitions.
Successfully simplified 10 atomic propositions for a total of 16 simplifications.
FORMULA RERS2020-PT-pb102-CTLFireability-03 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-17 01:03:52] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-17 01:03:53] [INFO ] Flatten gal took : 2809 ms
FORMULA RERS2020-PT-pb102-CTLFireability-00 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-17 01:03:56] [INFO ] Flatten gal took : 2977 ms
[2023-03-17 01:04:02] [INFO ] Input system was already deterministic with 122617 transitions.
Support contains 182 out of 1267 places (down from 189) after GAL structural reductions.
Computed a total of 245 stabilizing places and 27913 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 1267/1267 places, 122617/122617 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 1266 transition count 122614
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 5 place count 1264 transition count 122613
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 2 Pre rules applied. Total rules applied 5 place count 1264 transition count 122611
Deduced a syphon composed of 2 places in 54 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 9 place count 1262 transition count 122611
Performed 32 Post agglomeration using F-continuation condition.Transition count delta: 32
Deduced a syphon composed of 32 places in 49 ms
Reduce places removed 32 places and 0 transitions.
Iterating global reduction 2 with 64 rules applied. Total rules applied 73 place count 1230 transition count 122579
Ensure Unique test removed 1976 transitions
Reduce isomorphic transitions removed 1976 transitions.
Iterating post reduction 2 with 1976 rules applied. Total rules applied 2049 place count 1230 transition count 120603
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 48 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 4 rules applied. Total rules applied 2053 place count 1228 transition count 120601
Applied a total of 2053 rules in 2688 ms. Remains 1228 /1267 variables (removed 39) and now considering 120601/122617 (removed 2016) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2692 ms. Remains : 1228/1267 places, 120601/122617 transitions.
[2023-03-17 01:04:08] [INFO ] Flatten gal took : 2650 ms
[2023-03-17 01:04:11] [INFO ] Flatten gal took : 3032 ms
[2023-03-17 01:04:16] [INFO ] Input system was already deterministic with 120601 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 694 ms. (steps per millisecond=14 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 276 ms. (steps per millisecond=36 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 8176 steps, run timeout after 3001 ms. (steps per millisecond=2 ) properties seen :{}
Probabilistic random walk after 8176 steps, saw 6170 distinct states, run finished after 3003 ms. (steps per millisecond=2 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 01:04:21] [INFO ] Flow matrix only has 92385 transitions (discarded 28216 similar events)
// Phase 1: matrix 92385 rows 1228 cols
[2023-03-17 01:04:21] [INFO ] Computed 7 place invariants in 353 ms
[2023-03-17 01:04:21] [INFO ] [Real]Absence check using 7 positive place invariants in 11 ms returned sat
[2023-03-17 01:04:46] [INFO ] After 24935ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-17 01:04:47] [INFO ] State equation strengthened by 3026 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:669)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-17 01:04:47] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-17 01:04:47] [INFO ] After 25793ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 2 out of 1228 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1228/1228 places, 120601/120601 transitions.
Drop transitions removed 2006 transitions
Reduce isomorphic transitions removed 2006 transitions.
Iterating post reduction 0 with 2006 rules applied. Total rules applied 2006 place count 1228 transition count 118595
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 44 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 1 with 12 rules applied. Total rules applied 2018 place count 1222 transition count 118589
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 2024 place count 1222 transition count 118583
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: -1
Deduced a syphon composed of 5 places in 44 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 2 with 10 rules applied. Total rules applied 2034 place count 1217 transition count 118584
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 2 with 4 rules applied. Total rules applied 2038 place count 1217 transition count 118580
Free-agglomeration rule applied 39 times.
Iterating global reduction 3 with 39 rules applied. Total rules applied 2077 place count 1217 transition count 118541
Reduce places removed 39 places and 0 transitions.
Ensure Unique test removed 36 transitions
Reduce isomorphic transitions removed 36 transitions.
Iterating post reduction 3 with 75 rules applied. Total rules applied 2152 place count 1178 transition count 118505
Free-agglomeration rule applied 1 times.
Iterating global reduction 4 with 1 rules applied. Total rules applied 2153 place count 1178 transition count 118504
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 2 rules applied. Total rules applied 2155 place count 1177 transition count 118503
Free-agglomeration rule applied 1 times.
Iterating global reduction 5 with 1 rules applied. Total rules applied 2156 place count 1177 transition count 118502
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 2157 place count 1176 transition count 118502
Free-agglomeration rule (complex) applied 75 times with reduction of 4414 identical transitions.
Iterating global reduction 6 with 75 rules applied. Total rules applied 2232 place count 1176 transition count 134712
Reduce places removed 75 places and 0 transitions.
Drop transitions removed 48 transitions
Ensure Unique test removed 3410 transitions
Reduce isomorphic transitions removed 3458 transitions.
Iterating post reduction 6 with 3533 rules applied. Total rules applied 5765 place count 1101 transition count 131254
Applied a total of 5765 rules in 5079 ms. Remains 1101 /1228 variables (removed 127) and now considering 131254/120601 (removed -10653) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 5082 ms. Remains : 1101/1228 places, 131254/120601 transitions.
Interrupted random walk after 343288 steps, including 1 resets, run timeout after 30001 ms. (steps per millisecond=11 ) properties seen 0
Interrupted Best-First random walk after 475222 steps, including 1 resets, run timeout after 5001 ms. (steps per millisecond=95 ) properties seen 0
Interrupted probabilistic random walk after 242186 steps, run timeout after 105002 ms. (steps per millisecond=2 ) properties seen :{}
Probabilistic random walk after 242186 steps, saw 161522 distinct states, run finished after 105005 ms. (steps per millisecond=2 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 01:07:12] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
// Phase 1: matrix 104268 rows 1101 cols
[2023-03-17 01:07:13] [INFO ] Computed 7 place invariants in 525 ms
[2023-03-17 01:07:13] [INFO ] [Real]Absence check using 7 positive place invariants in 9 ms returned sat
[2023-03-17 01:07:43] [INFO ] After 29942ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-17 01:07:43] [INFO ] State equation strengthened by 3605 read => feed constraints.
[2023-03-17 01:07:57] [INFO ] After 13292ms SMT Verify possible using 3605 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-17 01:08:07] [INFO ] Deduced a trap composed of 378 places in 8979 ms of which 17 ms to minimize.
[2023-03-17 01:08:09] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 12690 ms
[2023-03-17 01:08:10] [INFO ] After 26892ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 01:08:10] [INFO ] After 57618ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 01:08:10] [INFO ] [Nat]Absence check using 7 positive place invariants in 10 ms returned sat
[2023-03-17 01:08:41] [INFO ] After 30623ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-17 01:08:56] [INFO ] After 15154ms SMT Verify possible using 3605 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-17 01:09:06] [INFO ] Deduced a trap composed of 378 places in 8701 ms of which 1 ms to minimize.
[2023-03-17 01:09:17] [INFO ] Deduced a trap composed of 59 places in 9840 ms of which 2 ms to minimize.
[2023-03-17 01:09:19] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 23284 ms
[2023-03-17 01:09:20] [INFO ] After 39332ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 1470 ms.
[2023-03-17 01:09:22] [INFO ] After 71575ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 0 ms.
Support contains 2 out of 1101 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1101/1101 places, 131254/131254 transitions.
Applied a total of 0 rules in 556 ms. Remains 1101 /1101 variables (removed 0) and now considering 131254/131254 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 556 ms. Remains : 1101/1101 places, 131254/131254 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1101/1101 places, 131254/131254 transitions.
Applied a total of 0 rules in 559 ms. Remains 1101 /1101 variables (removed 0) and now considering 131254/131254 (removed 0) transitions.
[2023-03-17 01:09:23] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:09:23] [INFO ] Invariant cache hit.
[2023-03-17 01:09:31] [INFO ] Implicit Places using invariants in 8293 ms returned []
Implicit Place search using SMT only with invariants took 8299 ms to find 0 implicit places.
[2023-03-17 01:09:31] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:09:31] [INFO ] Invariant cache hit.
[2023-03-17 01:10:01] [INFO ] Performed 97231/131254 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-17 01:10:11] [INFO ] Dead Transitions using invariants and state equation in 40162 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 49031 ms. Remains : 1101/1101 places, 131254/131254 transitions.
Incomplete random walk after 100000 steps, including 2 resets, run finished after 8082 ms. (steps per millisecond=12 ) properties (out of 2) seen :1
Running SMT prover for 1 properties.
[2023-03-17 01:10:20] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:10:20] [INFO ] Invariant cache hit.
[2023-03-17 01:10:20] [INFO ] [Real]Absence check using 7 positive place invariants in 8 ms returned sat
[2023-03-17 01:10:49] [INFO ] After 29103ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-17 01:10:50] [INFO ] State equation strengthened by 3605 read => feed constraints.
[2023-03-17 01:11:04] [INFO ] After 14202ms SMT Verify possible using 3605 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-17 01:11:16] [INFO ] Deduced a trap composed of 146 places in 10229 ms of which 5 ms to minimize.
[2023-03-17 01:11:28] [INFO ] Deduced a trap composed of 350 places in 10111 ms of which 1 ms to minimize.
[2023-03-17 01:11:30] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 26077 ms
[2023-03-17 01:11:31] [INFO ] After 41272ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 01:11:31] [INFO ] After 71721ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 01:11:32] [INFO ] [Nat]Absence check using 7 positive place invariants in 8 ms returned sat
[2023-03-17 01:12:01] [INFO ] After 29343ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-17 01:12:15] [INFO ] After 13825ms SMT Verify possible using 3605 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-17 01:12:26] [INFO ] Deduced a trap composed of 146 places in 10304 ms of which 1 ms to minimize.
[2023-03-17 01:12:39] [INFO ] Deduced a trap composed of 264 places in 11270 ms of which 2 ms to minimize.
[2023-03-17 01:12:47] [INFO ] Deduced a trap composed of 378 places in 6774 ms of which 0 ms to minimize.
[2023-03-17 01:12:59] [INFO ] Deduced a trap composed of 59 places in 10582 ms of which 2 ms to minimize.
[2023-03-17 01:13:03] [INFO ] Trap strengthening (SAT) tested/added 5/4 trap constraints in 47816 ms
[2023-03-17 01:13:03] [INFO ] After 62507ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 122 ms.
[2023-03-17 01:13:04] [INFO ] After 92099ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Interrupted random walk after 338211 steps, including 1 resets, run timeout after 30001 ms. (steps per millisecond=11 ) properties seen 0
Interrupted Best-First random walk after 436535 steps, including 1 resets, run timeout after 5001 ms. (steps per millisecond=87 ) properties seen 0
Interrupted probabilistic random walk after 190605 steps, run timeout after 105004 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 190605 steps, saw 125777 distinct states, run finished after 105005 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 01:15:24] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:15:24] [INFO ] Invariant cache hit.
[2023-03-17 01:15:24] [INFO ] [Real]Absence check using 7 positive place invariants in 9 ms returned sat
[2023-03-17 01:15:54] [INFO ] After 30658ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-17 01:15:55] [INFO ] State equation strengthened by 3605 read => feed constraints.
[2023-03-17 01:16:11] [INFO ] After 15717ms SMT Verify possible using 3605 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-17 01:16:23] [INFO ] Deduced a trap composed of 174 places in 10564 ms of which 2 ms to minimize.
[2023-03-17 01:16:35] [INFO ] Deduced a trap composed of 275 places in 10985 ms of which 1 ms to minimize.
[2023-03-17 01:16:45] [INFO ] Deduced a trap composed of 350 places in 8756 ms of which 2 ms to minimize.
[2023-03-17 01:16:48] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 36781 ms
[2023-03-17 01:16:49] [INFO ] After 53422ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 01:16:49] [INFO ] After 84873ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 01:16:49] [INFO ] [Nat]Absence check using 7 positive place invariants in 9 ms returned sat
[2023-03-17 01:17:19] [INFO ] After 30763ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-17 01:17:34] [INFO ] After 14200ms SMT Verify possible using 3605 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-17 01:17:45] [INFO ] Deduced a trap composed of 174 places in 10487 ms of which 2 ms to minimize.
[2023-03-17 01:17:58] [INFO ] Deduced a trap composed of 195 places in 11384 ms of which 2 ms to minimize.
[2023-03-17 01:18:06] [INFO ] Deduced a trap composed of 378 places in 6872 ms of which 1 ms to minimize.
[2023-03-17 01:18:18] [INFO ] Deduced a trap composed of 67 places in 10169 ms of which 2 ms to minimize.
[2023-03-17 01:18:29] [INFO ] Deduced a trap composed of 52 places in 9820 ms of which 1 ms to minimize.
[2023-03-17 01:18:32] [INFO ] Trap strengthening (SAT) tested/added 6/5 trap constraints in 58506 ms
[2023-03-17 01:18:33] [INFO ] After 73582ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 1376 ms.
[2023-03-17 01:18:34] [INFO ] After 105884ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 0 ms.
Support contains 2 out of 1101 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1101/1101 places, 131254/131254 transitions.
Applied a total of 0 rules in 604 ms. Remains 1101 /1101 variables (removed 0) and now considering 131254/131254 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 604 ms. Remains : 1101/1101 places, 131254/131254 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1101/1101 places, 131254/131254 transitions.
Applied a total of 0 rules in 601 ms. Remains 1101 /1101 variables (removed 0) and now considering 131254/131254 (removed 0) transitions.
[2023-03-17 01:18:36] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:18:36] [INFO ] Invariant cache hit.
[2023-03-17 01:18:44] [INFO ] Implicit Places using invariants in 7935 ms returned []
Implicit Place search using SMT only with invariants took 7936 ms to find 0 implicit places.
[2023-03-17 01:18:44] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:18:44] [INFO ] Invariant cache hit.
[2023-03-17 01:19:14] [INFO ] Performed 95606/131254 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-17 01:19:24] [INFO ] Dead Transitions using invariants and state equation in 40814 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 49363 ms. Remains : 1101/1101 places, 131254/131254 transitions.
Incomplete random walk after 100000 steps, including 2 resets, run finished after 7655 ms. (steps per millisecond=13 ) properties (out of 2) seen :1
Running SMT prover for 1 properties.
[2023-03-17 01:19:32] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:19:32] [INFO ] Invariant cache hit.
[2023-03-17 01:19:32] [INFO ] [Real]Absence check using 7 positive place invariants in 7 ms returned sat
[2023-03-17 01:20:01] [INFO ] After 28991ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-17 01:20:02] [INFO ] State equation strengthened by 3605 read => feed constraints.
[2023-03-17 01:20:15] [INFO ] After 13325ms SMT Verify possible using 3605 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-17 01:20:29] [INFO ] Deduced a trap composed of 146 places in 11778 ms of which 2 ms to minimize.
[2023-03-17 01:20:39] [INFO ] Deduced a trap composed of 350 places in 8526 ms of which 2 ms to minimize.
[2023-03-17 01:20:41] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 25891 ms
[2023-03-17 01:20:42] [INFO ] After 40232ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 01:20:42] [INFO ] After 69977ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 01:20:42] [INFO ] [Nat]Absence check using 7 positive place invariants in 8 ms returned sat
[2023-03-17 01:21:12] [INFO ] After 29533ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-17 01:21:25] [INFO ] After 12817ms SMT Verify possible using 3605 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-17 01:21:37] [INFO ] Deduced a trap composed of 146 places in 10564 ms of which 1 ms to minimize.
[2023-03-17 01:21:49] [INFO ] Deduced a trap composed of 264 places in 10733 ms of which 1 ms to minimize.
[2023-03-17 01:21:57] [INFO ] Deduced a trap composed of 378 places in 6692 ms of which 0 ms to minimize.
[2023-03-17 01:22:09] [INFO ] Deduced a trap composed of 59 places in 10997 ms of which 2 ms to minimize.
[2023-03-17 01:22:12] [INFO ] Trap strengthening (SAT) tested/added 5/4 trap constraints in 47704 ms
[2023-03-17 01:22:13] [INFO ] After 61400ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 107 ms.
[2023-03-17 01:22:13] [INFO ] After 91178ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Finished random walk after 394 steps, including 1 resets, run visited all 1 properties in 37 ms. (steps per millisecond=10 )
Incomplete random walk after 10000 steps, including 2 resets, run finished after 911 ms. (steps per millisecond=10 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 125 ms. (steps per millisecond=80 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 6350 steps, run timeout after 3004 ms. (steps per millisecond=2 ) properties seen :{}
Probabilistic random walk after 6350 steps, saw 4979 distinct states, run finished after 3005 ms. (steps per millisecond=2 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 01:22:18] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:22:18] [INFO ] Invariant cache hit.
[2023-03-17 01:22:18] [INFO ] [Real]Absence check using 7 positive place invariants in 9 ms returned sat
[2023-03-17 01:22:43] [INFO ] After 25022ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 1 out of 1101 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1101/1101 places, 131254/131254 transitions.
Applied a total of 0 rules in 613 ms. Remains 1101 /1101 variables (removed 0) and now considering 131254/131254 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 616 ms. Remains : 1101/1101 places, 131254/131254 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1165 ms. (steps per millisecond=8 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 185 ms. (steps per millisecond=54 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 6120 steps, run timeout after 3001 ms. (steps per millisecond=2 ) properties seen :{}
Probabilistic random walk after 6120 steps, saw 4813 distinct states, run finished after 3001 ms. (steps per millisecond=2 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 01:22:48] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:22:48] [INFO ] Invariant cache hit.
[2023-03-17 01:22:48] [INFO ] [Real]Absence check using 7 positive place invariants in 9 ms returned sat
[2023-03-17 01:23:13] [INFO ] After 25012ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 1 out of 1101 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1101/1101 places, 131254/131254 transitions.
Applied a total of 0 rules in 572 ms. Remains 1101 /1101 variables (removed 0) and now considering 131254/131254 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 573 ms. Remains : 1101/1101 places, 131254/131254 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1101/1101 places, 131254/131254 transitions.
Applied a total of 0 rules in 563 ms. Remains 1101 /1101 variables (removed 0) and now considering 131254/131254 (removed 0) transitions.
[2023-03-17 01:23:14] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:23:14] [INFO ] Invariant cache hit.
[2023-03-17 01:23:22] [INFO ] Implicit Places using invariants in 8028 ms returned []
Implicit Place search using SMT only with invariants took 8029 ms to find 0 implicit places.
[2023-03-17 01:23:22] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:23:22] [INFO ] Invariant cache hit.
[2023-03-17 01:23:52] [INFO ] Performed 95441/131254 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-17 01:24:03] [INFO ] Dead Transitions using invariants and state equation in 40977 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 49583 ms. Remains : 1101/1101 places, 131254/131254 transitions.
Graph (trivial) has 31203 edges and 1101 vertex of which 893 / 1101 are part of one of the 139 SCC in 9 ms
Free SCC test removed 754 places
Drop transitions removed 62733 transitions
Ensure Unique test removed 56018 transitions
Reduce isomorphic transitions removed 118751 transitions.
Graph (complete) has 8619 edges and 347 vertex of which 339 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.6 ms
Discarding 8 places :
Also discarding 0 output transitions
Drop transitions removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 0 with 12 rules applied. Total rules applied 14 place count 339 transition count 12491
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 18 place count 335 transition count 12483
Iterating global reduction 1 with 4 rules applied. Total rules applied 22 place count 335 transition count 12483
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 25 place count 332 transition count 12458
Iterating global reduction 1 with 3 rules applied. Total rules applied 28 place count 332 transition count 12458
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 30 place count 330 transition count 12456
Iterating global reduction 1 with 2 rules applied. Total rules applied 32 place count 330 transition count 12456
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: 5
Deduced a syphon composed of 5 places in 3 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 1 with 10 rules applied. Total rules applied 42 place count 325 transition count 12451
Ensure Unique test removed 69 transitions
Reduce isomorphic transitions removed 69 transitions.
Iterating post reduction 1 with 69 rules applied. Total rules applied 111 place count 325 transition count 12382
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -11
Deduced a syphon composed of 1 places in 2 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 113 place count 324 transition count 12393
Drop transitions removed 5643 transitions
Redundant transition composition rules discarded 5643 transitions
Iterating global reduction 2 with 5643 rules applied. Total rules applied 5756 place count 324 transition count 6750
Reduce places removed 1 places and 0 transitions.
Drop transitions removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Graph (complete) has 5978 edges and 323 vertex of which 295 are kept as prefixes of interest. Removing 28 places using SCC suffix rule.3 ms
Discarding 28 places :
Also discarding 20 output transitions
Drop transitions removed 20 transitions
Iterating post reduction 2 with 9 rules applied. Total rules applied 5765 place count 295 transition count 6723
Drop transitions removed 507 transitions
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 517 transitions.
Iterating post reduction 3 with 517 rules applied. Total rules applied 6282 place count 295 transition count 6206
Discarding 11 places :
Symmetric choice reduction at 4 with 11 rule applications. Total rules 6293 place count 284 transition count 6171
Iterating global reduction 4 with 11 rules applied. Total rules applied 6304 place count 284 transition count 6171
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 6305 place count 283 transition count 6158
Iterating global reduction 4 with 1 rules applied. Total rules applied 6306 place count 283 transition count 6158
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 4 with 2 rules applied. Total rules applied 6308 place count 282 transition count 6157
Drop transitions removed 29 transitions
Redundant transition composition rules discarded 29 transitions
Iterating global reduction 4 with 29 rules applied. Total rules applied 6337 place count 282 transition count 6128
Free-agglomeration rule applied 5 times.
Iterating global reduction 4 with 5 rules applied. Total rules applied 6342 place count 282 transition count 6123
Reduce places removed 5 places and 0 transitions.
Ensure Unique test removed 32 transitions
Reduce isomorphic transitions removed 32 transitions.
Iterating post reduction 4 with 37 rules applied. Total rules applied 6379 place count 277 transition count 6091
Drop transitions removed 29 transitions
Redundant transition composition rules discarded 29 transitions
Iterating global reduction 5 with 29 rules applied. Total rules applied 6408 place count 277 transition count 6062
Free-agglomeration rule applied 3 times.
Iterating global reduction 5 with 3 rules applied. Total rules applied 6411 place count 277 transition count 6059
Reduce places removed 3 places and 0 transitions.
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 5 with 19 rules applied. Total rules applied 6430 place count 274 transition count 6043
Drop transitions removed 31 transitions
Redundant transition composition rules discarded 31 transitions
Iterating global reduction 6 with 31 rules applied. Total rules applied 6461 place count 274 transition count 6012
Free-agglomeration rule applied 1 times.
Iterating global reduction 6 with 1 rules applied. Total rules applied 6462 place count 274 transition count 6011
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 6463 place count 273 transition count 6011
Drop transitions removed 10 transitions
Redundant transition composition rules discarded 10 transitions
Iterating global reduction 7 with 10 rules applied. Total rules applied 6473 place count 273 transition count 6001
Free-agglomeration rule (complex) applied 15 times with reduction of 195 identical transitions.
Iterating global reduction 7 with 15 rules applied. Total rules applied 6488 place count 273 transition count 8906
Reduce places removed 15 places and 0 transitions.
Ensure Unique test removed 258 transitions
Reduce isomorphic transitions removed 258 transitions.
Iterating post reduction 7 with 273 rules applied. Total rules applied 6761 place count 258 transition count 8648
Drop transitions removed 459 transitions
Redundant transition composition rules discarded 459 transitions
Iterating global reduction 8 with 459 rules applied. Total rules applied 7220 place count 258 transition count 8189
Partial Free-agglomeration rule applied 218 times.
Drop transitions removed 218 transitions
Iterating global reduction 8 with 218 rules applied. Total rules applied 7438 place count 258 transition count 8189
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 8 with 6 rules applied. Total rules applied 7444 place count 258 transition count 8183
Discarding 4 places :
Symmetric choice reduction at 9 with 4 rule applications. Total rules 7448 place count 254 transition count 8159
Iterating global reduction 9 with 4 rules applied. Total rules applied 7452 place count 254 transition count 8159
Discarding 1 places :
Symmetric choice reduction at 9 with 1 rule applications. Total rules 7453 place count 253 transition count 8148
Iterating global reduction 9 with 1 rules applied. Total rules applied 7454 place count 253 transition count 8148
Partial Free-agglomeration rule applied 214 times.
Drop transitions removed 214 transitions
Iterating global reduction 9 with 214 rules applied. Total rules applied 7668 place count 253 transition count 8148
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 9 with 2 rules applied. Total rules applied 7670 place count 253 transition count 8146
Discarding 2 places :
Symmetric choice reduction at 10 with 2 rule applications. Total rules 7672 place count 251 transition count 8124
Iterating global reduction 10 with 2 rules applied. Total rules applied 7674 place count 251 transition count 8124
Applied a total of 7674 rules in 4713 ms. Remains 251 /1101 variables (removed 850) and now considering 8124/131254 (removed 123130) transitions.
Running SMT prover for 1 properties.
[2023-03-17 01:24:08] [INFO ] Flow matrix only has 8004 transitions (discarded 120 similar events)
// Phase 1: matrix 8004 rows 251 cols
[2023-03-17 01:24:08] [INFO ] Computed 0 place invariants in 46 ms
[2023-03-17 01:24:09] [INFO ] After 1186ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 01:24:11] [INFO ] After 1154ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-17 01:24:11] [INFO ] State equation strengthened by 21 read => feed constraints.
[2023-03-17 01:24:11] [INFO ] After 159ms SMT Verify possible using 21 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-17 01:24:11] [INFO ] After 384ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 129 ms.
[2023-03-17 01:24:11] [INFO ] After 1722ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Starting structural reductions in LTL mode, iteration 0 : 1267/1267 places, 122617/122617 transitions.
Applied a total of 0 rules in 204 ms. Remains 1267 /1267 variables (removed 0) and now considering 122617/122617 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 207 ms. Remains : 1267/1267 places, 122617/122617 transitions.
[2023-03-17 01:24:14] [INFO ] Flatten gal took : 2842 ms
[2023-03-17 01:24:18] [INFO ] Flatten gal took : 3275 ms
[2023-03-17 01:24:24] [INFO ] Input system was already deterministic with 122617 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1267/1267 places, 122617/122617 transitions.
Applied a total of 0 rules in 240 ms. Remains 1267 /1267 variables (removed 0) and now considering 122617/122617 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 243 ms. Remains : 1267/1267 places, 122617/122617 transitions.
[2023-03-17 01:24:27] [INFO ] Flatten gal took : 2749 ms
[2023-03-17 01:24:31] [INFO ] Flatten gal took : 3051 ms
[2023-03-17 01:24:37] [INFO ] Input system was already deterministic with 122617 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1267/1267 places, 122617/122617 transitions.
Applied a total of 0 rules in 189 ms. Remains 1267 /1267 variables (removed 0) and now considering 122617/122617 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 191 ms. Remains : 1267/1267 places, 122617/122617 transitions.
[2023-03-17 01:24:40] [INFO ] Flatten gal took : 2771 ms
[2023-03-17 01:24:43] [INFO ] Flatten gal took : 3111 ms
[2023-03-17 01:24:49] [INFO ] Input system was already deterministic with 122617 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1267/1267 places, 122617/122617 transitions.
Applied a total of 0 rules in 174 ms. Remains 1267 /1267 variables (removed 0) and now considering 122617/122617 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 178 ms. Remains : 1267/1267 places, 122617/122617 transitions.
[2023-03-17 01:24:52] [INFO ] Flatten gal took : 2768 ms
[2023-03-17 01:24:56] [INFO ] Flatten gal took : 3139 ms
[2023-03-17 01:25:01] [INFO ] Input system was already deterministic with 122617 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1267/1267 places, 122617/122617 transitions.
Applied a total of 0 rules in 214 ms. Remains 1267 /1267 variables (removed 0) and now considering 122617/122617 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 216 ms. Remains : 1267/1267 places, 122617/122617 transitions.
[2023-03-17 01:25:05] [INFO ] Flatten gal took : 2800 ms
[2023-03-17 01:25:08] [INFO ] Flatten gal took : 3101 ms
[2023-03-17 01:25:14] [INFO ] Input system was already deterministic with 122617 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1267/1267 places, 122617/122617 transitions.
Applied a total of 0 rules in 188 ms. Remains 1267 /1267 variables (removed 0) and now considering 122617/122617 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 191 ms. Remains : 1267/1267 places, 122617/122617 transitions.
[2023-03-17 01:25:17] [INFO ] Flatten gal took : 2821 ms
[2023-03-17 01:25:21] [INFO ] Flatten gal took : 3505 ms
[2023-03-17 01:25:27] [INFO ] Input system was already deterministic with 122617 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1267/1267 places, 122617/122617 transitions.
Applied a total of 0 rules in 277 ms. Remains 1267 /1267 variables (removed 0) and now considering 122617/122617 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 281 ms. Remains : 1267/1267 places, 122617/122617 transitions.
[2023-03-17 01:25:31] [INFO ] Flatten gal took : 2978 ms
[2023-03-17 01:25:34] [INFO ] Flatten gal took : 3318 ms
[2023-03-17 01:25:40] [INFO ] Input system was already deterministic with 122617 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1267/1267 places, 122617/122617 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 1266 transition count 122614
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 5 place count 1264 transition count 122613
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 2 Pre rules applied. Total rules applied 5 place count 1264 transition count 122611
Deduced a syphon composed of 2 places in 53 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 9 place count 1262 transition count 122611
Performed 32 Post agglomeration using F-continuation condition.Transition count delta: 32
Deduced a syphon composed of 32 places in 47 ms
Reduce places removed 32 places and 0 transitions.
Iterating global reduction 2 with 64 rules applied. Total rules applied 73 place count 1230 transition count 122579
Ensure Unique test removed 1976 transitions
Reduce isomorphic transitions removed 1976 transitions.
Iterating post reduction 2 with 1976 rules applied. Total rules applied 2049 place count 1230 transition count 120603
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 46 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 4 rules applied. Total rules applied 2053 place count 1228 transition count 120601
Applied a total of 2053 rules in 2245 ms. Remains 1228 /1267 variables (removed 39) and now considering 120601/122617 (removed 2016) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2247 ms. Remains : 1228/1267 places, 120601/122617 transitions.
[2023-03-17 01:25:45] [INFO ] Flatten gal took : 2657 ms
[2023-03-17 01:25:48] [INFO ] Flatten gal took : 2966 ms
[2023-03-17 01:25:54] [INFO ] Input system was already deterministic with 120601 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1267/1267 places, 122617/122617 transitions.
Applied a total of 0 rules in 179 ms. Remains 1267 /1267 variables (removed 0) and now considering 122617/122617 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 182 ms. Remains : 1267/1267 places, 122617/122617 transitions.
[2023-03-17 01:25:57] [INFO ] Flatten gal took : 2746 ms
[2023-03-17 01:26:00] [INFO ] Flatten gal took : 3191 ms
[2023-03-17 01:26:06] [INFO ] Input system was already deterministic with 122617 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1267/1267 places, 122617/122617 transitions.
Applied a total of 0 rules in 173 ms. Remains 1267 /1267 variables (removed 0) and now considering 122617/122617 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 175 ms. Remains : 1267/1267 places, 122617/122617 transitions.
[2023-03-17 01:26:09] [INFO ] Flatten gal took : 2981 ms
[2023-03-17 01:26:12] [INFO ] Flatten gal took : 3034 ms
[2023-03-17 01:26:18] [INFO ] Input system was already deterministic with 122617 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1267/1267 places, 122617/122617 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 1266 transition count 122614
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 5 place count 1264 transition count 122613
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 2 Pre rules applied. Total rules applied 5 place count 1264 transition count 122611
Deduced a syphon composed of 2 places in 62 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 9 place count 1262 transition count 122611
Performed 32 Post agglomeration using F-continuation condition.Transition count delta: 32
Deduced a syphon composed of 32 places in 56 ms
Reduce places removed 32 places and 0 transitions.
Iterating global reduction 2 with 64 rules applied. Total rules applied 73 place count 1230 transition count 122579
Ensure Unique test removed 1976 transitions
Reduce isomorphic transitions removed 1976 transitions.
Iterating post reduction 2 with 1976 rules applied. Total rules applied 2049 place count 1230 transition count 120603
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 57 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 4 rules applied. Total rules applied 2053 place count 1228 transition count 120601
Applied a total of 2053 rules in 2721 ms. Remains 1228 /1267 variables (removed 39) and now considering 120601/122617 (removed 2016) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2724 ms. Remains : 1228/1267 places, 120601/122617 transitions.
[2023-03-17 01:26:24] [INFO ] Flatten gal took : 2862 ms
[2023-03-17 01:26:27] [INFO ] Flatten gal took : 3253 ms
[2023-03-17 01:26:33] [INFO ] Input system was already deterministic with 120601 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 809 ms. (steps per millisecond=12 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 116 ms. (steps per millisecond=86 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 6210 steps, run timeout after 3003 ms. (steps per millisecond=2 ) properties seen :{}
Probabilistic random walk after 6210 steps, saw 4658 distinct states, run finished after 3003 ms. (steps per millisecond=2 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 01:26:38] [INFO ] Flow matrix only has 92385 transitions (discarded 28216 similar events)
// Phase 1: matrix 92385 rows 1228 cols
[2023-03-17 01:26:38] [INFO ] Computed 7 place invariants in 433 ms
[2023-03-17 01:26:38] [INFO ] [Real]Absence check using 7 positive place invariants in 9 ms returned sat
[2023-03-17 01:27:03] [INFO ] After 24664ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-17 01:27:04] [INFO ] State equation strengthened by 3026 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:669)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-17 01:27:04] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-17 01:27:04] [INFO ] After 25580ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 2 out of 1228 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1228/1228 places, 120601/120601 transitions.
Drop transitions removed 2006 transitions
Reduce isomorphic transitions removed 2006 transitions.
Iterating post reduction 0 with 2006 rules applied. Total rules applied 2006 place count 1228 transition count 118595
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 55 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 1 with 12 rules applied. Total rules applied 2018 place count 1222 transition count 118589
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 2024 place count 1222 transition count 118583
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: -1
Deduced a syphon composed of 5 places in 55 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 2 with 10 rules applied. Total rules applied 2034 place count 1217 transition count 118584
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 2 with 4 rules applied. Total rules applied 2038 place count 1217 transition count 118580
Free-agglomeration rule applied 39 times.
Iterating global reduction 3 with 39 rules applied. Total rules applied 2077 place count 1217 transition count 118541
Reduce places removed 39 places and 0 transitions.
Ensure Unique test removed 36 transitions
Reduce isomorphic transitions removed 36 transitions.
Iterating post reduction 3 with 75 rules applied. Total rules applied 2152 place count 1178 transition count 118505
Free-agglomeration rule applied 1 times.
Iterating global reduction 4 with 1 rules applied. Total rules applied 2153 place count 1178 transition count 118504
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 2 rules applied. Total rules applied 2155 place count 1177 transition count 118503
Free-agglomeration rule applied 1 times.
Iterating global reduction 5 with 1 rules applied. Total rules applied 2156 place count 1177 transition count 118502
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 2157 place count 1176 transition count 118502
Free-agglomeration rule (complex) applied 75 times with reduction of 4414 identical transitions.
Iterating global reduction 6 with 75 rules applied. Total rules applied 2232 place count 1176 transition count 134712
Reduce places removed 75 places and 0 transitions.
Drop transitions removed 48 transitions
Ensure Unique test removed 3410 transitions
Reduce isomorphic transitions removed 3458 transitions.
Iterating post reduction 6 with 3533 rules applied. Total rules applied 5765 place count 1101 transition count 131254
Applied a total of 5765 rules in 5690 ms. Remains 1101 /1228 variables (removed 127) and now considering 131254/120601 (removed -10653) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 5694 ms. Remains : 1101/1228 places, 131254/120601 transitions.
Interrupted random walk after 374366 steps, including 1 resets, run timeout after 30001 ms. (steps per millisecond=12 ) properties seen 0
Interrupted Best-First random walk after 439647 steps, including 1 resets, run timeout after 5001 ms. (steps per millisecond=87 ) properties seen 0
Interrupted probabilistic random walk after 231679 steps, run timeout after 105003 ms. (steps per millisecond=2 ) properties seen :{}
Probabilistic random walk after 231679 steps, saw 154453 distinct states, run finished after 105003 ms. (steps per millisecond=2 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 01:29:30] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
// Phase 1: matrix 104268 rows 1101 cols
[2023-03-17 01:29:30] [INFO ] Computed 7 place invariants in 508 ms
[2023-03-17 01:29:30] [INFO ] [Real]Absence check using 7 positive place invariants in 8 ms returned sat
[2023-03-17 01:30:01] [INFO ] After 30652ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-17 01:30:02] [INFO ] State equation strengthened by 3605 read => feed constraints.
[2023-03-17 01:30:16] [INFO ] After 14148ms SMT Verify possible using 3605 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-17 01:30:29] [INFO ] Deduced a trap composed of 350 places in 11605 ms of which 1 ms to minimize.
[2023-03-17 01:30:42] [INFO ] Deduced a trap composed of 139 places in 11135 ms of which 2 ms to minimize.
[2023-03-17 01:30:46] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 29972 ms
[2023-03-17 01:30:47] [INFO ] After 45029ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 01:30:47] [INFO ] After 77193ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 01:30:47] [INFO ] [Nat]Absence check using 7 positive place invariants in 8 ms returned sat
[2023-03-17 01:31:18] [INFO ] After 30349ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-17 01:31:33] [INFO ] After 15153ms SMT Verify possible using 3605 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-17 01:31:45] [INFO ] Deduced a trap composed of 350 places in 11207 ms of which 2 ms to minimize.
[2023-03-17 01:31:58] [INFO ] Deduced a trap composed of 52 places in 10939 ms of which 2 ms to minimize.
[2023-03-17 01:32:09] [INFO ] Deduced a trap composed of 139 places in 10380 ms of which 1 ms to minimize.
[2023-03-17 01:32:13] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 40129 ms
[2023-03-17 01:32:14] [INFO ] After 56142ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 1294 ms.
[2023-03-17 01:32:15] [INFO ] After 87936ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 0 ms.
Support contains 2 out of 1101 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1101/1101 places, 131254/131254 transitions.
Applied a total of 0 rules in 583 ms. Remains 1101 /1101 variables (removed 0) and now considering 131254/131254 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 583 ms. Remains : 1101/1101 places, 131254/131254 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1101/1101 places, 131254/131254 transitions.
Applied a total of 0 rules in 576 ms. Remains 1101 /1101 variables (removed 0) and now considering 131254/131254 (removed 0) transitions.
[2023-03-17 01:32:16] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:32:16] [INFO ] Invariant cache hit.
[2023-03-17 01:32:24] [INFO ] Implicit Places using invariants in 7774 ms returned []
Implicit Place search using SMT only with invariants took 7775 ms to find 0 implicit places.
[2023-03-17 01:32:24] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:32:24] [INFO ] Invariant cache hit.
[2023-03-17 01:32:54] [INFO ] Performed 91710/131254 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-17 01:33:07] [INFO ] Dead Transitions using invariants and state equation in 42671 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 51034 ms. Remains : 1101/1101 places, 131254/131254 transitions.
Incomplete random walk after 100000 steps, including 2 resets, run finished after 8520 ms. (steps per millisecond=11 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-17 01:33:16] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:33:16] [INFO ] Invariant cache hit.
[2023-03-17 01:33:16] [INFO ] [Real]Absence check using 7 positive place invariants in 7 ms returned sat
[2023-03-17 01:33:44] [INFO ] After 28506ms SMT Verify possible using state equation in real domain returned unsat :0 sat :2
[2023-03-17 01:33:45] [INFO ] State equation strengthened by 3605 read => feed constraints.
[2023-03-17 01:33:57] [INFO ] After 11899ms SMT Verify possible using 3605 Read/Feed constraints in real domain returned unsat :0 sat :2
[2023-03-17 01:34:09] [INFO ] Deduced a trap composed of 350 places in 10661 ms of which 2 ms to minimize.
[2023-03-17 01:34:21] [INFO ] Deduced a trap composed of 139 places in 10966 ms of which 2 ms to minimize.
[2023-03-17 01:34:24] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 26574 ms
[2023-03-17 01:34:28] [INFO ] After 42737ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-17 01:34:28] [INFO ] After 72377ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-17 01:34:28] [INFO ] [Nat]Absence check using 7 positive place invariants in 7 ms returned sat
[2023-03-17 01:34:56] [INFO ] After 28429ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-17 01:35:09] [INFO ] After 12503ms SMT Verify possible using 3605 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2023-03-17 01:35:21] [INFO ] Deduced a trap composed of 350 places in 10795 ms of which 5 ms to minimize.
[2023-03-17 01:35:34] [INFO ] Deduced a trap composed of 52 places in 11601 ms of which 2 ms to minimize.
[2023-03-17 01:35:45] [INFO ] Deduced a trap composed of 139 places in 9730 ms of which 1 ms to minimize.
[2023-03-17 01:35:47] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 38250 ms
[2023-03-17 01:35:51] [INFO ] After 54629ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 145 ms.
[2023-03-17 01:35:51] [INFO ] After 83325ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Interrupted random walk after 362419 steps, including 1 resets, run timeout after 30001 ms. (steps per millisecond=12 ) properties seen 0
Interrupted Best-First random walk after 413323 steps, including 1 resets, run timeout after 5001 ms. (steps per millisecond=82 ) properties seen 0
Interrupted probabilistic random walk after 234808 steps, run timeout after 105001 ms. (steps per millisecond=2 ) properties seen :{}
Probabilistic random walk after 234808 steps, saw 156686 distinct states, run finished after 105001 ms. (steps per millisecond=2 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 01:38:11] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:38:11] [INFO ] Invariant cache hit.
[2023-03-17 01:38:12] [INFO ] [Real]Absence check using 7 positive place invariants in 7 ms returned sat
[2023-03-17 01:38:41] [INFO ] After 29901ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-17 01:38:43] [INFO ] State equation strengthened by 3605 read => feed constraints.
[2023-03-17 01:38:56] [INFO ] After 13543ms SMT Verify possible using 3605 Read/Feed constraints in real domain returned unsat :0 sat :1
[2023-03-17 01:39:08] [INFO ] Deduced a trap composed of 350 places in 10639 ms of which 2 ms to minimize.
[2023-03-17 01:39:19] [INFO ] Deduced a trap composed of 139 places in 9826 ms of which 1 ms to minimize.
[2023-03-17 01:39:21] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 25353 ms
[2023-03-17 01:39:22] [INFO ] After 39846ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 01:39:22] [INFO ] After 71018ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 01:39:23] [INFO ] [Nat]Absence check using 7 positive place invariants in 7 ms returned sat
[2023-03-17 01:39:53] [INFO ] After 30797ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-17 01:40:06] [INFO ] After 12948ms SMT Verify possible using 3605 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-17 01:40:18] [INFO ] Deduced a trap composed of 350 places in 10579 ms of which 2 ms to minimize.
[2023-03-17 01:40:30] [INFO ] Deduced a trap composed of 52 places in 10683 ms of which 1 ms to minimize.
[2023-03-17 01:40:41] [INFO ] Deduced a trap composed of 139 places in 9618 ms of which 2 ms to minimize.
[2023-03-17 01:40:44] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 37759 ms
[2023-03-17 01:40:45] [INFO ] After 51616ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 1435 ms.
[2023-03-17 01:40:46] [INFO ] After 83986ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 0 ms.
Support contains 2 out of 1101 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1101/1101 places, 131254/131254 transitions.
Applied a total of 0 rules in 594 ms. Remains 1101 /1101 variables (removed 0) and now considering 131254/131254 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 594 ms. Remains : 1101/1101 places, 131254/131254 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1101/1101 places, 131254/131254 transitions.
Applied a total of 0 rules in 608 ms. Remains 1101 /1101 variables (removed 0) and now considering 131254/131254 (removed 0) transitions.
[2023-03-17 01:40:48] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:40:48] [INFO ] Invariant cache hit.
[2023-03-17 01:40:56] [INFO ] Implicit Places using invariants in 8301 ms returned []
Implicit Place search using SMT only with invariants took 8302 ms to find 0 implicit places.
[2023-03-17 01:40:56] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:40:56] [INFO ] Invariant cache hit.
[2023-03-17 01:41:26] [INFO ] Performed 99274/131254 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-17 01:41:36] [INFO ] Dead Transitions using invariants and state equation in 39993 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 48915 ms. Remains : 1101/1101 places, 131254/131254 transitions.
Incomplete random walk after 100000 steps, including 2 resets, run finished after 9566 ms. (steps per millisecond=10 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-17 01:41:46] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:41:46] [INFO ] Invariant cache hit.
[2023-03-17 01:41:46] [INFO ] [Real]Absence check using 7 positive place invariants in 7 ms returned sat
[2023-03-17 01:42:15] [INFO ] After 28842ms SMT Verify possible using state equation in real domain returned unsat :0 sat :2
[2023-03-17 01:42:16] [INFO ] State equation strengthened by 3605 read => feed constraints.
[2023-03-17 01:42:27] [INFO ] After 11578ms SMT Verify possible using 3605 Read/Feed constraints in real domain returned unsat :0 sat :2
[2023-03-17 01:42:41] [INFO ] Deduced a trap composed of 350 places in 11977 ms of which 2 ms to minimize.
[2023-03-17 01:42:54] [INFO ] Deduced a trap composed of 139 places in 11633 ms of which 1 ms to minimize.
[2023-03-17 01:42:56] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 28560 ms
[2023-03-17 01:43:00] [INFO ] After 44201ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-17 01:43:00] [INFO ] After 74214ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-17 01:43:00] [INFO ] [Nat]Absence check using 7 positive place invariants in 7 ms returned sat
[2023-03-17 01:43:28] [INFO ] After 28385ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-17 01:43:40] [INFO ] After 11195ms SMT Verify possible using 3605 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2023-03-17 01:43:52] [INFO ] Deduced a trap composed of 350 places in 10763 ms of which 2 ms to minimize.
[2023-03-17 01:44:04] [INFO ] Deduced a trap composed of 52 places in 11088 ms of which 1 ms to minimize.
[2023-03-17 01:44:15] [INFO ] Deduced a trap composed of 139 places in 10254 ms of which 2 ms to minimize.
[2023-03-17 01:44:18] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 37932 ms
[2023-03-17 01:44:21] [INFO ] After 52940ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 131 ms.
[2023-03-17 01:44:21] [INFO ] After 81573ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Incomplete random walk after 10000 steps, including 2 resets, run finished after 784 ms. (steps per millisecond=12 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 146 ms. (steps per millisecond=68 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 7257 steps, run timeout after 3003 ms. (steps per millisecond=2 ) properties seen :{}
Probabilistic random walk after 7257 steps, saw 5605 distinct states, run finished after 3003 ms. (steps per millisecond=2 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 01:44:26] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:44:26] [INFO ] Invariant cache hit.
[2023-03-17 01:44:26] [INFO ] [Real]Absence check using 7 positive place invariants in 9 ms returned sat
[2023-03-17 01:44:51] [INFO ] After 25017ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 1 out of 1101 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1101/1101 places, 131254/131254 transitions.
Applied a total of 0 rules in 549 ms. Remains 1101 /1101 variables (removed 0) and now considering 131254/131254 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 552 ms. Remains : 1101/1101 places, 131254/131254 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 792 ms. (steps per millisecond=12 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 108 ms. (steps per millisecond=92 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 8060 steps, run timeout after 3002 ms. (steps per millisecond=2 ) properties seen :{}
Probabilistic random walk after 8060 steps, saw 6142 distinct states, run finished after 3003 ms. (steps per millisecond=2 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 01:44:55] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:44:55] [INFO ] Invariant cache hit.
[2023-03-17 01:44:55] [INFO ] [Real]Absence check using 7 positive place invariants in 8 ms returned sat
[2023-03-17 01:45:20] [INFO ] After 25023ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 1 out of 1101 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1101/1101 places, 131254/131254 transitions.
Applied a total of 0 rules in 565 ms. Remains 1101 /1101 variables (removed 0) and now considering 131254/131254 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 565 ms. Remains : 1101/1101 places, 131254/131254 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1101/1101 places, 131254/131254 transitions.
Applied a total of 0 rules in 561 ms. Remains 1101 /1101 variables (removed 0) and now considering 131254/131254 (removed 0) transitions.
[2023-03-17 01:45:21] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:45:21] [INFO ] Invariant cache hit.
[2023-03-17 01:45:29] [INFO ] Implicit Places using invariants in 8041 ms returned []
Implicit Place search using SMT only with invariants took 8042 ms to find 0 implicit places.
[2023-03-17 01:45:29] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:45:29] [INFO ] Invariant cache hit.
[2023-03-17 01:46:00] [INFO ] Performed 97244/131254 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-17 01:46:09] [INFO ] Dead Transitions using invariants and state equation in 40043 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 48655 ms. Remains : 1101/1101 places, 131254/131254 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 787 ms. (steps per millisecond=12 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 149 ms. (steps per millisecond=67 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 7365 steps, run timeout after 3001 ms. (steps per millisecond=2 ) properties seen :{}
Probabilistic random walk after 7365 steps, saw 5676 distinct states, run finished after 3001 ms. (steps per millisecond=2 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 01:46:14] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:46:14] [INFO ] Invariant cache hit.
[2023-03-17 01:46:14] [INFO ] [Real]Absence check using 7 positive place invariants in 7 ms returned sat
[2023-03-17 01:46:39] [INFO ] After 25027ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 1 out of 1101 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1101/1101 places, 131254/131254 transitions.
Applied a total of 0 rules in 653 ms. Remains 1101 /1101 variables (removed 0) and now considering 131254/131254 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 658 ms. Remains : 1101/1101 places, 131254/131254 transitions.
Incomplete random walk after 10000 steps, including 3 resets, run finished after 811 ms. (steps per millisecond=12 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 114 ms. (steps per millisecond=87 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 6919 steps, run timeout after 3003 ms. (steps per millisecond=2 ) properties seen :{}
Probabilistic random walk after 6919 steps, saw 5371 distinct states, run finished after 3003 ms. (steps per millisecond=2 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-17 01:46:44] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:46:44] [INFO ] Invariant cache hit.
[2023-03-17 01:46:44] [INFO ] [Real]Absence check using 7 positive place invariants in 8 ms returned sat
[2023-03-17 01:47:09] [INFO ] After 25020ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 1 out of 1101 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1101/1101 places, 131254/131254 transitions.
Applied a total of 0 rules in 574 ms. Remains 1101 /1101 variables (removed 0) and now considering 131254/131254 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 574 ms. Remains : 1101/1101 places, 131254/131254 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1101/1101 places, 131254/131254 transitions.
Applied a total of 0 rules in 558 ms. Remains 1101 /1101 variables (removed 0) and now considering 131254/131254 (removed 0) transitions.
[2023-03-17 01:47:10] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:47:10] [INFO ] Invariant cache hit.
[2023-03-17 01:47:18] [INFO ] Implicit Places using invariants in 7901 ms returned []
Implicit Place search using SMT only with invariants took 7901 ms to find 0 implicit places.
[2023-03-17 01:47:18] [INFO ] Flow matrix only has 104268 transitions (discarded 26986 similar events)
[2023-03-17 01:47:18] [INFO ] Invariant cache hit.
[2023-03-17 01:47:48] [INFO ] Performed 96580/131254 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-17 01:47:58] [INFO ] Dead Transitions using invariants and state equation in 40391 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 48861 ms. Remains : 1101/1101 places, 131254/131254 transitions.
Graph (trivial) has 31176 edges and 1101 vertex of which 893 / 1101 are part of one of the 139 SCC in 6 ms
Free SCC test removed 754 places
Drop transitions removed 62855 transitions
Ensure Unique test removed 55810 transitions
Reduce isomorphic transitions removed 118665 transitions.
Graph (complete) has 8639 edges and 347 vertex of which 339 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.5 ms
Discarding 8 places :
Also discarding 0 output transitions
Drop transitions removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 0 with 12 rules applied. Total rules applied 14 place count 339 transition count 12577
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 18 place count 335 transition count 12569
Iterating global reduction 1 with 4 rules applied. Total rules applied 22 place count 335 transition count 12569
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 25 place count 332 transition count 12544
Iterating global reduction 1 with 3 rules applied. Total rules applied 28 place count 332 transition count 12544
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 30 place count 330 transition count 12542
Iterating global reduction 1 with 2 rules applied. Total rules applied 32 place count 330 transition count 12542
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: 5
Deduced a syphon composed of 5 places in 3 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 1 with 10 rules applied. Total rules applied 42 place count 325 transition count 12537
Ensure Unique test removed 69 transitions
Reduce isomorphic transitions removed 69 transitions.
Iterating post reduction 1 with 69 rules applied. Total rules applied 111 place count 325 transition count 12468
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -11
Deduced a syphon composed of 1 places in 2 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 113 place count 324 transition count 12479
Drop transitions removed 5677 transitions
Redundant transition composition rules discarded 5677 transitions
Iterating global reduction 2 with 5677 rules applied. Total rules applied 5790 place count 324 transition count 6802
Reduce places removed 1 places and 0 transitions.
Drop transitions removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Graph (complete) has 6000 edges and 323 vertex of which 295 are kept as prefixes of interest. Removing 28 places using SCC suffix rule.2 ms
Discarding 28 places :
Also discarding 20 output transitions
Drop transitions removed 20 transitions
Iterating post reduction 2 with 9 rules applied. Total rules applied 5799 place count 295 transition count 6775
Drop transitions removed 507 transitions
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 517 transitions.
Iterating post reduction 3 with 517 rules applied. Total rules applied 6316 place count 295 transition count 6258
Discarding 11 places :
Symmetric choice reduction at 4 with 11 rule applications. Total rules 6327 place count 284 transition count 6223
Iterating global reduction 4 with 11 rules applied. Total rules applied 6338 place count 284 transition count 6223
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 6339 place count 283 transition count 6210
Iterating global reduction 4 with 1 rules applied. Total rules applied 6340 place count 283 transition count 6210
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 2 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 4 with 2 rules applied. Total rules applied 6342 place count 282 transition count 6209
Drop transitions removed 34 transitions
Redundant transition composition rules discarded 34 transitions
Iterating global reduction 4 with 34 rules applied. Total rules applied 6376 place count 282 transition count 6175
Free-agglomeration rule applied 5 times.
Iterating global reduction 4 with 5 rules applied. Total rules applied 6381 place count 282 transition count 6170
Reduce places removed 5 places and 0 transitions.
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 4 with 21 rules applied. Total rules applied 6402 place count 277 transition count 6154
Drop transitions removed 46 transitions
Redundant transition composition rules discarded 46 transitions
Iterating global reduction 5 with 46 rules applied. Total rules applied 6448 place count 277 transition count 6108
Free-agglomeration rule applied 3 times.
Iterating global reduction 5 with 3 rules applied. Total rules applied 6451 place count 277 transition count 6105
Reduce places removed 3 places and 0 transitions.
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 5 with 19 rules applied. Total rules applied 6470 place count 274 transition count 6089
Drop transitions removed 31 transitions
Redundant transition composition rules discarded 31 transitions
Iterating global reduction 6 with 31 rules applied. Total rules applied 6501 place count 274 transition count 6058
Free-agglomeration rule applied 1 times.
Iterating global reduction 6 with 1 rules applied. Total rules applied 6502 place count 274 transition count 6057
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 6503 place count 273 transition count 6057
Drop transitions removed 10 transitions
Redundant transition composition rules discarded 10 transitions
Iterating global reduction 7 with 10 rules applied. Total rules applied 6513 place count 273 transition count 6047
Free-agglomeration rule (complex) applied 16 times with reduction of 195 identical transitions.
Iterating global reduction 7 with 16 rules applied. Total rules applied 6529 place count 273 transition count 8997
Reduce places removed 16 places and 0 transitions.
Ensure Unique test removed 279 transitions
Reduce isomorphic transitions removed 279 transitions.
Iterating post reduction 7 with 295 rules applied. Total rules applied 6824 place count 257 transition count 8718
Drop transitions removed 463 transitions
Redundant transition composition rules discarded 463 transitions
Iterating global reduction 8 with 463 rules applied. Total rules applied 7287 place count 257 transition count 8255
Partial Free-agglomeration rule applied 218 times.
Drop transitions removed 218 transitions
Iterating global reduction 8 with 218 rules applied. Total rules applied 7505 place count 257 transition count 8255
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 8 with 6 rules applied. Total rules applied 7511 place count 257 transition count 8249
Discarding 4 places :
Symmetric choice reduction at 9 with 4 rule applications. Total rules 7515 place count 253 transition count 8225
Iterating global reduction 9 with 4 rules applied. Total rules applied 7519 place count 253 transition count 8225
Discarding 1 places :
Symmetric choice reduction at 9 with 1 rule applications. Total rules 7520 place count 252 transition count 8214
Iterating global reduction 9 with 1 rules applied. Total rules applied 7521 place count 252 transition count 8214
Partial Free-agglomeration rule applied 214 times.
Drop transitions removed 214 transitions
Iterating global reduction 9 with 214 rules applied. Total rules applied 7735 place count 252 transition count 8214
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 9 with 2 rules applied. Total rules applied 7737 place count 252 transition count 8212
Discarding 2 places :
Symmetric choice reduction at 10 with 2 rule applications. Total rules 7739 place count 250 transition count 8190
Iterating global reduction 10 with 2 rules applied. Total rules applied 7741 place count 250 transition count 8190
Applied a total of 7741 rules in 4508 ms. Remains 250 /1101 variables (removed 851) and now considering 8190/131254 (removed 123064) transitions.
Running SMT prover for 1 properties.
[2023-03-17 01:48:03] [INFO ] Flow matrix only has 8068 transitions (discarded 122 similar events)
// Phase 1: matrix 8068 rows 250 cols
[2023-03-17 01:48:03] [INFO ] Computed 0 place invariants in 97 ms
[2023-03-17 01:48:04] [INFO ] After 1326ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-17 01:48:05] [INFO ] After 1193ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-17 01:48:05] [INFO ] State equation strengthened by 21 read => feed constraints.
[2023-03-17 01:48:05] [INFO ] After 177ms SMT Verify possible using 21 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-17 01:48:06] [INFO ] After 403ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 141 ms.
[2023-03-17 01:48:06] [INFO ] After 1787ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Starting structural reductions in LTL mode, iteration 0 : 1267/1267 places, 122617/122617 transitions.
Applied a total of 0 rules in 178 ms. Remains 1267 /1267 variables (removed 0) and now considering 122617/122617 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 180 ms. Remains : 1267/1267 places, 122617/122617 transitions.
[2023-03-17 01:48:09] [INFO ] Flatten gal took : 2771 ms
[2023-03-17 01:48:12] [INFO ] Flatten gal took : 3014 ms
[2023-03-17 01:48:18] [INFO ] Input system was already deterministic with 122617 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1267/1267 places, 122617/122617 transitions.
Applied a total of 0 rules in 181 ms. Remains 1267 /1267 variables (removed 0) and now considering 122617/122617 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 183 ms. Remains : 1267/1267 places, 122617/122617 transitions.
[2023-03-17 01:48:21] [INFO ] Flatten gal took : 2744 ms
[2023-03-17 01:48:24] [INFO ] Flatten gal took : 3114 ms
[2023-03-17 01:48:30] [INFO ] Input system was already deterministic with 122617 transitions.
[2023-03-17 01:48:34] [INFO ] Flatten gal took : 2985 ms
[2023-03-17 01:48:37] [INFO ] Flatten gal took : 3093 ms
[2023-03-17 01:48:37] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 9 ms.
[2023-03-17 01:48:37] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1267 places, 122617 transitions and 488182 arcs took 253 ms.
Total runtime 2876091 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RERS2020-PT-pb102
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 152244 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16286112 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 343 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 348 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 353 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 358 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 363 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 368 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 373 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 378 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 383 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 388 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 393 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 398 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 403 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 408 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 413 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 418 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 423 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 428 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 433 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 438 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 443 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 448 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 453 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 458 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 463 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 468 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 473 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 478 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 483 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 488 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 493 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 498 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 503 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 508 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 513 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 518 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 523 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 528 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 533 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 538 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 543 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 548 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 553 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 558 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 563 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 568 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
lola: Created skeleton in 232.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 573 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 578 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 583 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 588 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 593 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 598 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 603 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 608 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 613 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 618 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 623 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 628 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 633 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 638 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 643 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 648 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 653 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 658 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 663 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 668 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 673 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 678 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 683 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 688 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 693 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 698 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 703 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 708 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 713 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS2020-PT-pb102-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS2020-PT-pb102-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-13: EF 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS2020-PT-pb102-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 718 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
lola: caught signal Terminated - aborting LoLA

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS2020-PT-pb102-CTLFireability-01: EF unknown AGGR
RERS2020-PT-pb102-CTLFireability-02: CTL unknown AGGR
RERS2020-PT-pb102-CTLFireability-04: CTL unknown AGGR
RERS2020-PT-pb102-CTLFireability-05: CTL unknown AGGR
RERS2020-PT-pb102-CTLFireability-06: CTL unknown AGGR
RERS2020-PT-pb102-CTLFireability-07: CTL unknown AGGR
RERS2020-PT-pb102-CTLFireability-08: CTL unknown AGGR
RERS2020-PT-pb102-CTLFireability-09: CTL unknown AGGR
RERS2020-PT-pb102-CTLFireability-10: CTL unknown AGGR
RERS2020-PT-pb102-CTLFireability-11: CTL unknown AGGR
RERS2020-PT-pb102-CTLFireability-12: CTL unknown AGGR
RERS2020-PT-pb102-CTLFireability-13: EF unknown AGGR
RERS2020-PT-pb102-CTLFireability-14: CTL unknown AGGR
RERS2020-PT-pb102-CTLFireability-15: CTL unknown AGGR


Time elapsed: 722 secs. Pages in use: 0

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS2020-PT-pb102"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RERS2020-PT-pb102, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199300226"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS2020-PT-pb102.tgz
mv RERS2020-PT-pb102 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;