fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r327-tall-167889199200138
Last Updated
May 14, 2023

About the Execution of LoLa+red for RERS17pb114-PT-9

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16108.287 3600000.00 3732409.00 12524.40 [undef] Time out reached

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199200138.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RERS17pb114-PT-9, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199200138
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 73M
-rw-r--r-- 1 mcc users 8.7K Feb 26 05:00 CTLCardinality.txt
-rw-r--r-- 1 mcc users 99K Feb 26 05:00 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.7K Feb 26 04:57 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 26 04:57 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:39 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:39 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.3K Feb 25 16:39 LTLFireability.txt
-rw-r--r-- 1 mcc users 20K Feb 25 16:39 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Feb 26 05:11 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 162K Feb 26 05:11 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.8K Feb 26 05:04 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 37K Feb 26 05:04 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:39 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:39 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 73M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb114-PT-9-CTLFireability-00
FORMULA_NAME RERS17pb114-PT-9-CTLFireability-01
FORMULA_NAME RERS17pb114-PT-9-CTLFireability-02
FORMULA_NAME RERS17pb114-PT-9-CTLFireability-03
FORMULA_NAME RERS17pb114-PT-9-CTLFireability-04
FORMULA_NAME RERS17pb114-PT-9-CTLFireability-05
FORMULA_NAME RERS17pb114-PT-9-CTLFireability-06
FORMULA_NAME RERS17pb114-PT-9-CTLFireability-07
FORMULA_NAME RERS17pb114-PT-9-CTLFireability-08
FORMULA_NAME RERS17pb114-PT-9-CTLFireability-09
FORMULA_NAME RERS17pb114-PT-9-CTLFireability-10
FORMULA_NAME RERS17pb114-PT-9-CTLFireability-11
FORMULA_NAME RERS17pb114-PT-9-CTLFireability-12
FORMULA_NAME RERS17pb114-PT-9-CTLFireability-13
FORMULA_NAME RERS17pb114-PT-9-CTLFireability-14
FORMULA_NAME RERS17pb114-PT-9-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678977967539

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb114-PT-9
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 14:46:09] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-16 14:46:09] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 14:46:11] [INFO ] Load time of PNML (sax parser for PT used): 1953 ms
[2023-03-16 14:46:11] [INFO ] Transformed 1446 places.
[2023-03-16 14:46:11] [INFO ] Transformed 151085 transitions.
[2023-03-16 14:46:11] [INFO ] Parsed PT model containing 1446 places and 151085 transitions and 604252 arcs in 2521 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 35 ms.
Support contains 196 out of 1446 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1446/1446 places, 151085/151085 transitions.
Ensure Unique test removed 17 places
Iterating post reduction 0 with 17 rules applied. Total rules applied 17 place count 1429 transition count 151085
Applied a total of 17 rules in 1071 ms. Remains 1429 /1446 variables (removed 17) and now considering 151085/151085 (removed 0) transitions.
[2023-03-16 14:46:14] [INFO ] Flow matrix only has 84691 transitions (discarded 66394 similar events)
// Phase 1: matrix 84691 rows 1429 cols
[2023-03-16 14:46:14] [INFO ] Computed 18 place invariants in 436 ms
[2023-03-16 14:46:22] [INFO ] Implicit Places using invariants in 8410 ms returned []
Implicit Place search using SMT only with invariants took 8443 ms to find 0 implicit places.
[2023-03-16 14:46:22] [INFO ] Flow matrix only has 84691 transitions (discarded 66394 similar events)
[2023-03-16 14:46:22] [INFO ] Invariant cache hit.
[2023-03-16 14:46:52] [INFO ] Performed 91024/151085 'is it Dead' test of which 0 returned DEAD in 30 seconds.
[2023-03-16 14:47:12] [INFO ] Dead Transitions using invariants and state equation in 49554 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 1429/1446 places, 151085/151085 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 59089 ms. Remains : 1429/1446 places, 151085/151085 transitions.
Support contains 196 out of 1429 places after structural reductions.
[2023-03-16 14:47:16] [INFO ] Flatten gal took : 3700 ms
[2023-03-16 14:47:20] [INFO ] Flatten gal took : 3419 ms
[2023-03-16 14:47:27] [INFO ] Input system was already deterministic with 151085 transitions.
Support contains 194 out of 1429 places (down from 196) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1386 ms. (steps per millisecond=7 ) properties (out of 72) seen :4
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 68) seen :0
Interrupted probabilistic random walk after 9946 steps, run timeout after 6001 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 9946 steps, saw 8464 distinct states, run finished after 6002 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 68 properties.
[2023-03-16 14:47:37] [INFO ] Flow matrix only has 84691 transitions (discarded 66394 similar events)
[2023-03-16 14:47:37] [INFO ] Invariant cache hit.
[2023-03-16 14:47:39] [INFO ] [Real]Absence check using 18 positive place invariants in 16 ms returned sat
[2023-03-16 14:47:39] [INFO ] After 2612ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:68
[2023-03-16 14:47:41] [INFO ] [Nat]Absence check using 18 positive place invariants in 19 ms returned sat
[2023-03-16 14:48:04] [INFO ] After 21965ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :68
[2023-03-16 14:48:06] [INFO ] State equation strengthened by 2342 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 14:48:06] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 14:48:06] [INFO ] After 26371ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:68
Fused 68 Parikh solutions to 2 different solutions.
Parikh walk visited 0 properties in 49 ms.
Support contains 177 out of 1429 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Drop transitions removed 512 transitions
Reduce isomorphic transitions removed 512 transitions.
Iterating post reduction 0 with 512 rules applied. Total rules applied 512 place count 1429 transition count 150573
Applied a total of 512 rules in 1715 ms. Remains 1429 /1429 variables (removed 0) and now considering 150573/151085 (removed 512) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1719 ms. Remains : 1429/1429 places, 150573/151085 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 919 ms. (steps per millisecond=10 ) properties (out of 68) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 65) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 65) seen :0
Interrupted probabilistic random walk after 9627 steps, run timeout after 6001 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 9627 steps, saw 8825 distinct states, run finished after 6001 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 65 properties.
[2023-03-16 14:48:16] [INFO ] Flow matrix only has 84690 transitions (discarded 65883 similar events)
// Phase 1: matrix 84690 rows 1429 cols
[2023-03-16 14:48:17] [INFO ] Computed 18 place invariants in 410 ms
[2023-03-16 14:48:18] [INFO ] [Real]Absence check using 18 positive place invariants in 15 ms returned sat
[2023-03-16 14:48:19] [INFO ] After 2455ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:65
[2023-03-16 14:48:21] [INFO ] [Nat]Absence check using 18 positive place invariants in 17 ms returned sat
0timeout
^^^^^^^^
(error "Invalid token: 0timeout")
[2023-03-16 14:48:44] [INFO ] After 22172ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :65
[2023-03-16 14:48:46] [INFO ] State equation strengthened by 2341 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 14:48:46] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 14:48:46] [INFO ] After 26798ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:65
Fused 65 Parikh solutions to 2 different solutions.
Parikh walk visited 0 properties in 17 ms.
Support contains 172 out of 1429 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1429/1429 places, 150573/150573 transitions.
Applied a total of 0 rules in 1350 ms. Remains 1429 /1429 variables (removed 0) and now considering 150573/150573 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1350 ms. Remains : 1429/1429 places, 150573/150573 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1020 ms. (steps per millisecond=9 ) properties (out of 65) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 64) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 64) seen :0
Interrupted probabilistic random walk after 9565 steps, run timeout after 6005 ms. (steps per millisecond=1 ) properties seen :{}
Probabilistic random walk after 9565 steps, saw 8772 distinct states, run finished after 6006 ms. (steps per millisecond=1 ) properties seen :0
Running SMT prover for 64 properties.
[2023-03-16 14:48:56] [INFO ] Flow matrix only has 84690 transitions (discarded 65883 similar events)
[2023-03-16 14:48:56] [INFO ] Invariant cache hit.
[2023-03-16 14:48:58] [INFO ] [Real]Absence check using 18 positive place invariants in 16 ms returned sat
[2023-03-16 14:48:58] [INFO ] After 2372ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:64
[2023-03-16 14:49:00] [INFO ] [Nat]Absence check using 18 positive place invariants in 15 ms returned sat
[2023-03-16 14:49:24] [INFO ] After 22197ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :64
[2023-03-16 14:49:25] [INFO ] State equation strengthened by 2341 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 14:49:25] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 14:49:25] [INFO ] After 26489ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:64
Fused 64 Parikh solutions to 2 different solutions.
Parikh walk visited 0 properties in 15 ms.
Support contains 170 out of 1429 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1429/1429 places, 150573/150573 transitions.
Applied a total of 0 rules in 1248 ms. Remains 1429 /1429 variables (removed 0) and now considering 150573/150573 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1249 ms. Remains : 1429/1429 places, 150573/150573 transitions.
[2023-03-16 14:49:30] [INFO ] Flatten gal took : 3094 ms
[2023-03-16 14:49:33] [INFO ] Flatten gal took : 3225 ms
[2023-03-16 14:49:40] [INFO ] Input system was already deterministic with 151085 transitions.
Computed a total of 1 stabilizing places and 1 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1224 ms. Remains 1428 /1429 variables (removed 1) and now considering 151084/151085 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1229 ms. Remains : 1428/1429 places, 151084/151085 transitions.
[2023-03-16 14:49:45] [INFO ] Flatten gal took : 3378 ms
[2023-03-16 14:49:49] [INFO ] Flatten gal took : 3828 ms
[2023-03-16 14:49:56] [INFO ] Input system was already deterministic with 151084 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1189 ms. Remains 1428 /1429 variables (removed 1) and now considering 151084/151085 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1194 ms. Remains : 1428/1429 places, 151084/151085 transitions.
[2023-03-16 14:50:01] [INFO ] Flatten gal took : 3260 ms
[2023-03-16 14:50:05] [INFO ] Flatten gal took : 3782 ms
[2023-03-16 14:50:12] [INFO ] Input system was already deterministic with 151084 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 651 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 654 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 14:50:16] [INFO ] Flatten gal took : 2934 ms
[2023-03-16 14:50:20] [INFO ] Flatten gal took : 3426 ms
[2023-03-16 14:50:27] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 629 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 634 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 14:50:32] [INFO ] Flatten gal took : 3097 ms
[2023-03-16 14:50:35] [INFO ] Flatten gal took : 3560 ms
[2023-03-16 14:50:42] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 642 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 645 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 14:50:46] [INFO ] Flatten gal took : 2961 ms
[2023-03-16 14:50:49] [INFO ] Flatten gal took : 3493 ms
[2023-03-16 14:50:56] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 557 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 561 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 14:51:01] [INFO ] Flatten gal took : 3196 ms
[2023-03-16 14:51:04] [INFO ] Flatten gal took : 3320 ms
[2023-03-16 14:51:11] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 577 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 580 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 14:51:15] [INFO ] Flatten gal took : 2954 ms
[2023-03-16 14:51:18] [INFO ] Flatten gal took : 3401 ms
[2023-03-16 14:51:26] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 585 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 592 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 14:51:31] [INFO ] Flatten gal took : 3110 ms
[2023-03-16 14:51:34] [INFO ] Flatten gal took : 3362 ms
[2023-03-16 14:51:40] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 568 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 571 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 14:51:45] [INFO ] Flatten gal took : 2915 ms
[2023-03-16 14:51:48] [INFO ] Flatten gal took : 3603 ms
[2023-03-16 14:51:54] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 611 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 614 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 14:51:58] [INFO ] Flatten gal took : 2956 ms
[2023-03-16 14:52:02] [INFO ] Flatten gal took : 3382 ms
[2023-03-16 14:52:08] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 571 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 573 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 14:52:12] [INFO ] Flatten gal took : 2930 ms
[2023-03-16 14:52:16] [INFO ] Flatten gal took : 3433 ms
[2023-03-16 14:52:22] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 570 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 573 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 14:52:26] [INFO ] Flatten gal took : 2907 ms
[2023-03-16 14:52:30] [INFO ] Flatten gal took : 3431 ms
[2023-03-16 14:52:36] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 576 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 579 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 14:52:40] [INFO ] Flatten gal took : 2905 ms
[2023-03-16 14:52:43] [INFO ] Flatten gal took : 3386 ms
[2023-03-16 14:52:50] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 564 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 567 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 14:52:54] [INFO ] Flatten gal took : 2945 ms
[2023-03-16 14:52:57] [INFO ] Flatten gal took : 3407 ms
[2023-03-16 14:53:04] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Applied a total of 0 rules in 610 ms. Remains 1429 /1429 variables (removed 0) and now considering 151085/151085 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 616 ms. Remains : 1429/1429 places, 151085/151085 transitions.
[2023-03-16 14:53:08] [INFO ] Flatten gal took : 2947 ms
[2023-03-16 14:53:11] [INFO ] Flatten gal took : 3429 ms
[2023-03-16 14:53:18] [INFO ] Input system was already deterministic with 151085 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1429/1429 places, 151085/151085 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 1082 ms. Remains 1428 /1429 variables (removed 1) and now considering 151084/151085 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1084 ms. Remains : 1428/1429 places, 151084/151085 transitions.
[2023-03-16 14:53:22] [INFO ] Flatten gal took : 3240 ms
[2023-03-16 14:53:26] [INFO ] Flatten gal took : 3747 ms
[2023-03-16 14:53:33] [INFO ] Input system was already deterministic with 151084 transitions.
[2023-03-16 14:53:36] [INFO ] Flatten gal took : 3223 ms
[2023-03-16 14:53:40] [INFO ] Flatten gal took : 3440 ms
[2023-03-16 14:53:40] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 30 ms.
[2023-03-16 14:53:41] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1429 places, 151085 transitions and 604235 arcs took 1321 ms.
Total runtime 452581 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RERS17pb114-PT-9
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 2842204 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16073264 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 272 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 277 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 282 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 287 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 292 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 297 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 302 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 307 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 312 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 317 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 322 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 327 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 332 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 337 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 342 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 347 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 352 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 357 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 362 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 367 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 372 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 377 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 382 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 387 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 392 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 397 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 402 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 407 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 412 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 417 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 422 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 427 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 432 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 437 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 442 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 447 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 452 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 457 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 462 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 467 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 472 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 477 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 482 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 487 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 492 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 497 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 502 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 507 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 512 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 517 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 522 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 527 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 532 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 537 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 542 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 547 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 552 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 557 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 562 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 567 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 572 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 577 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 582 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 587 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 592 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 597 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 602 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 607 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 612 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 617 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 622 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 627 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 632 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 637 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 642 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 647 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 652 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 657 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 662 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 667 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 672 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 677 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 682 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 687 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 692 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 697 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 702 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 707 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 712 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 717 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 722 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 727 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 732 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 737 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 742 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 747 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 752 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 757 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 762 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 767 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 772 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 777 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 782 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 787 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 792 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 797 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 802 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 807 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 812 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 817 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 822 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 827 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 832 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 837 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 842 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 847 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 584.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 852 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 857 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 862 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 867 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 872 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 877 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 882 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 887 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 892 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 897 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 902 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 907 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 912 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 917 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 922 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 927 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 932 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 937 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 942 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 947 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 952 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 957 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 962 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 967 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 972 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 977 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 982 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 987 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 992 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 997 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1002 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1007 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1012 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1017 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1022 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1027 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1032 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1037 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1042 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1047 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1052 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1057 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1062 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1067 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1072 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1077 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1082 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1087 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1092 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1097 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1102 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1107 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1112 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1117 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1122 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1127 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1132 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1137 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1142 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1147 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1152 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1157 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1162 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1167 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1172 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1177 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1182 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1187 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1192 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1197 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1202 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1207 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1212 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1217 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1222 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1227 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1232 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1237 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1242 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1247 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1252 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1257 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1262 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1267 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1272 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1277 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1282 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1287 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1292 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1297 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1302 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1307 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1312 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1317 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1322 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1327 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1332 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1337 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1343 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1348 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1353 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1358 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1363 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1368 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1373 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1378 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1383 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1388 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1393 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1398 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1403 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1408 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1413 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1418 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1423 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1428 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1433 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1438 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1443 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1448 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1453 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 604.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1458 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1463 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1468 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1473 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1478 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1483 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1488 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1493 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1498 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1503 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1508 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1513 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1518 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1523 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1528 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1533 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1538 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1543 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1548 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1553 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1558 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1563 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1568 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1573 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1578 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1583 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1588 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1593 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1598 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1603 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1608 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1613 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1618 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1623 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1628 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1633 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1638 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1643 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1648 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1653 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1658 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1663 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1668 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1673 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1678 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1683 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1688 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1693 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1698 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1703 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1708 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1713 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1718 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1723 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1728 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1733 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1738 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1743 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1748 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1753 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1758 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1763 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1768 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1773 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1778 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1783 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1788 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1793 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1798 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1803 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1808 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1813 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1818 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1823 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1828 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1833 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1838 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1843 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1848 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1853 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1858 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1863 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1868 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1873 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1878 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1883 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1888 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1893 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1898 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1903 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1908 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1913 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1918 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1923 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1928 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1933 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1938 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1943 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1948 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1953 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1958 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1963 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1968 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1973 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1978 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1983 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1988 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1993 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1998 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2003 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2008 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2013 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2018 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2023 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2028 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2033 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2038 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2043 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2048 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 595.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2053 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2058 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2063 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2068 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2073 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2078 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2083 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2088 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2093 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2098 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2103 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2108 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2113 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2118 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2123 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2128 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2133 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2138 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2143 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2148 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2153 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2158 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2163 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2168 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2173 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2178 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2183 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2188 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2193 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2198 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2203 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2208 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2213 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2218 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2223 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2228 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2233 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2238 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2243 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2248 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2253 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2258 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2263 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2268 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2273 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2278 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2283 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2288 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2293 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2298 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2303 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2308 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2313 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2318 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2323 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2328 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2333 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2338 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2343 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2348 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2353 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2358 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2363 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2368 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2373 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2378 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2383 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2388 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2393 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2398 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2403 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2408 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2413 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2418 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2423 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2428 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2433 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2438 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2443 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2448 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2453 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2458 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2463 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2468 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2473 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2478 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2483 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2488 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2493 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2498 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2503 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2508 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2513 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2518 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2523 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2528 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2533 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2538 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2543 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2548 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2553 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2558 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2563 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2568 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2573 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2578 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 532.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2583 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2588 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2594 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2599 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2604 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2609 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2614 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2619 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2624 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2629 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2634 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2639 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2644 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2649 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2654 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2659 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2664 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2669 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2674 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2679 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2684 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2689 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2694 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2699 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2704 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2709 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2714 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2719 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2724 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2729 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2734 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2739 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2744 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2749 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2754 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2759 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2764 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2769 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2774 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2779 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2784 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2789 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2794 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2799 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2804 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2809 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2814 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2819 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2824 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2829 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2834 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2839 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2844 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2849 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2854 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2859 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2864 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2869 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2874 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2879 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2884 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2889 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2894 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2899 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2904 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2909 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2914 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2919 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2924 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2929 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2934 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2939 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2944 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2949 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2954 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2959 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2964 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2969 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2974 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2979 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2984 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2989 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2994 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2999 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3004 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3009 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3014 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3019 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3024 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3029 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3034 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3039 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3044 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3049 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3054 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3059 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3064 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3069 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3074 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3079 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3084 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3089 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3094 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3099 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3104 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3109 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3114 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3119 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3124 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3129 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3134 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3139 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb114-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-01: F 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb114-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb114-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3144 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: caught signal Terminated - aborting LoLA

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb114-PT-9-CTLFireability-00: CTL unknown AGGR
RERS17pb114-PT-9-CTLFireability-01: F unknown AGGR
RERS17pb114-PT-9-CTLFireability-02: CTL unknown AGGR
RERS17pb114-PT-9-CTLFireability-03: CTL unknown AGGR
RERS17pb114-PT-9-CTLFireability-04: CTL unknown AGGR
RERS17pb114-PT-9-CTLFireability-05: CTL unknown AGGR
RERS17pb114-PT-9-CTLFireability-06: CTL unknown AGGR
RERS17pb114-PT-9-CTLFireability-07: CTL unknown AGGR
RERS17pb114-PT-9-CTLFireability-08: CTL unknown AGGR
RERS17pb114-PT-9-CTLFireability-09: CTL unknown AGGR
RERS17pb114-PT-9-CTLFireability-10: CTL unknown AGGR
RERS17pb114-PT-9-CTLFireability-11: CTL unknown AGGR
RERS17pb114-PT-9-CTLFireability-12: CTL unknown AGGR
RERS17pb114-PT-9-CTLFireability-13: CTL unknown AGGR
RERS17pb114-PT-9-CTLFireability-14: CTL unknown AGGR
RERS17pb114-PT-9-CTLFireability-15: CTL unknown AGGR


Time elapsed: 3144 secs. Pages in use: 0

========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb114-PT-9"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RERS17pb114-PT-9, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199200138"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb114-PT-9.tgz
mv RERS17pb114-PT-9 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;