fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r327-tall-167889199100066
Last Updated
May 14, 2023

About the Execution of LoLa+red for RERS17pb113-PT-9

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16220.212 773819.00 1468081.00 22094.20 ?????T?????????? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r327-tall-167889199100066.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is RERS17pb113-PT-9, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r327-tall-167889199100066
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 7.4K Feb 26 18:11 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K Feb 26 18:11 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Feb 26 18:10 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K Feb 26 18:10 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:38 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:38 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 16:38 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:38 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 18:15 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 121K Feb 26 18:15 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 13K Feb 26 18:13 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Feb 26 18:13 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:38 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:38 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 15M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb113-PT-9-CTLFireability-00
FORMULA_NAME RERS17pb113-PT-9-CTLFireability-01
FORMULA_NAME RERS17pb113-PT-9-CTLFireability-02
FORMULA_NAME RERS17pb113-PT-9-CTLFireability-03
FORMULA_NAME RERS17pb113-PT-9-CTLFireability-04
FORMULA_NAME RERS17pb113-PT-9-CTLFireability-05
FORMULA_NAME RERS17pb113-PT-9-CTLFireability-06
FORMULA_NAME RERS17pb113-PT-9-CTLFireability-07
FORMULA_NAME RERS17pb113-PT-9-CTLFireability-08
FORMULA_NAME RERS17pb113-PT-9-CTLFireability-09
FORMULA_NAME RERS17pb113-PT-9-CTLFireability-10
FORMULA_NAME RERS17pb113-PT-9-CTLFireability-11
FORMULA_NAME RERS17pb113-PT-9-CTLFireability-12
FORMULA_NAME RERS17pb113-PT-9-CTLFireability-13
FORMULA_NAME RERS17pb113-PT-9-CTLFireability-14
FORMULA_NAME RERS17pb113-PT-9-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678949972156

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb113-PT-9
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-16 06:59:33] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-16 06:59:33] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-16 06:59:34] [INFO ] Load time of PNML (sax parser for PT used): 720 ms
[2023-03-16 06:59:34] [INFO ] Transformed 639 places.
[2023-03-16 06:59:34] [INFO ] Transformed 31353 transitions.
[2023-03-16 06:59:34] [INFO ] Parsed PT model containing 639 places and 31353 transitions and 125418 arcs in 1072 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 18 ms.
Support contains 211 out of 639 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 639/639 places, 31353/31353 transitions.
Ensure Unique test removed 12 places
Iterating post reduction 0 with 12 rules applied. Total rules applied 12 place count 627 transition count 31353
Applied a total of 12 rules in 219 ms. Remains 627 /639 variables (removed 12) and now considering 31353/31353 (removed 0) transitions.
[2023-03-16 06:59:35] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
// Phase 1: matrix 18326 rows 627 cols
[2023-03-16 06:59:35] [INFO ] Computed 13 place invariants in 119 ms
[2023-03-16 06:59:37] [INFO ] Implicit Places using invariants in 1915 ms returned []
Implicit Place search using SMT only with invariants took 1941 ms to find 0 implicit places.
[2023-03-16 06:59:37] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 06:59:37] [INFO ] Invariant cache hit.
[2023-03-16 06:59:46] [INFO ] Dead Transitions using invariants and state equation in 9457 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 627/639 places, 31353/31353 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11631 ms. Remains : 627/639 places, 31353/31353 transitions.
Support contains 211 out of 627 places after structural reductions.
[2023-03-16 06:59:48] [INFO ] Flatten gal took : 1044 ms
[2023-03-16 06:59:48] [INFO ] Flatten gal took : 795 ms
[2023-03-16 06:59:50] [INFO ] Input system was already deterministic with 31353 transitions.
Support contains 210 out of 627 places (down from 211) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 775 ms. (steps per millisecond=12 ) properties (out of 109) seen :26
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 83) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 83) seen :0
Running SMT prover for 83 properties.
[2023-03-16 06:59:52] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 06:59:52] [INFO ] Invariant cache hit.
[2023-03-16 06:59:54] [INFO ] [Real]Absence check using 13 positive place invariants in 12 ms returned sat
[2023-03-16 06:59:54] [INFO ] After 1274ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:83
[2023-03-16 06:59:55] [INFO ] [Nat]Absence check using 13 positive place invariants in 11 ms returned sat
[2023-03-16 07:00:19] [INFO ] After 23448ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :83
[2023-03-16 07:00:19] [INFO ] State equation strengthened by 829 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 07:00:19] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 07:00:19] [INFO ] After 25338ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:83
Fused 83 Parikh solutions to 5 different solutions.
Parikh walk visited 0 properties in 47 ms.
Support contains 162 out of 627 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 284 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 286 ms. Remains : 627/627 places, 31353/31353 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 507 ms. (steps per millisecond=19 ) properties (out of 83) seen :8
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 75) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 75) seen :0
Running SMT prover for 75 properties.
[2023-03-16 07:00:21] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 07:00:21] [INFO ] Invariant cache hit.
[2023-03-16 07:00:22] [INFO ] [Real]Absence check using 13 positive place invariants in 8 ms returned sat
[2023-03-16 07:00:22] [INFO ] After 1066ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:75
[2023-03-16 07:00:23] [INFO ] [Nat]Absence check using 13 positive place invariants in 8 ms returned sat
[2023-03-16 07:00:47] [INFO ] After 23561ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :75
[2023-03-16 07:00:48] [INFO ] State equation strengthened by 829 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 07:00:48] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 07:00:48] [INFO ] After 25415ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:75
Fused 75 Parikh solutions to 4 different solutions.
Parikh walk visited 0 properties in 21 ms.
Support contains 150 out of 627 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 204 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 204 ms. Remains : 627/627 places, 31353/31353 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 435 ms. (steps per millisecond=22 ) properties (out of 75) seen :3
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 72) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 72) seen :0
Interrupted probabilistic random walk after 22095 steps, run timeout after 3001 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 22095 steps, saw 20069 distinct states, run finished after 3003 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 72 properties.
[2023-03-16 07:00:52] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 07:00:52] [INFO ] Invariant cache hit.
[2023-03-16 07:00:53] [INFO ] [Real]Absence check using 13 positive place invariants in 8 ms returned sat
[2023-03-16 07:00:54] [INFO ] After 991ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:72
[2023-03-16 07:00:54] [INFO ] [Nat]Absence check using 13 positive place invariants in 8 ms returned sat
[2023-03-16 07:01:19] [INFO ] After 23641ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :72
[2023-03-16 07:01:19] [INFO ] State equation strengthened by 829 read => feed constraints.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:642)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 07:01:19] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 07:01:19] [INFO ] After 25236ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:72
Fused 72 Parikh solutions to 11 different solutions.
Parikh walk visited 0 properties in 56 ms.
Support contains 145 out of 627 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 220 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 220 ms. Remains : 627/627 places, 31353/31353 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 583 ms. (steps per millisecond=17 ) properties (out of 72) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 69) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 69) seen :0
Interrupted probabilistic random walk after 22394 steps, run timeout after 3001 ms. (steps per millisecond=7 ) properties seen :{}
Probabilistic random walk after 22394 steps, saw 20335 distinct states, run finished after 3004 ms. (steps per millisecond=7 ) properties seen :0
Running SMT prover for 69 properties.
[2023-03-16 07:01:23] [INFO ] Flow matrix only has 18326 transitions (discarded 13027 similar events)
[2023-03-16 07:01:23] [INFO ] Invariant cache hit.
[2023-03-16 07:01:25] [INFO ] [Real]Absence check using 13 positive place invariants in 29 ms returned sat
[2023-03-16 07:01:25] [INFO ] After 951ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:69
[2023-03-16 07:01:26] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.checkResults(DeadlockTester.java:797)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:631)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 07:01:50] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 07:01:50] [INFO ] After 25036ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:69
Fused 69 Parikh solutions to 6 different solutions.
Parikh walk visited 0 properties in 24 ms.
Support contains 137 out of 627 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 196 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 197 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 07:01:51] [INFO ] Flatten gal took : 579 ms
[2023-03-16 07:01:52] [INFO ] Flatten gal took : 680 ms
[2023-03-16 07:01:53] [INFO ] Input system was already deterministic with 31353 transitions.
Computed a total of 1 stabilizing places and 1 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 79 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 81 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 07:01:54] [INFO ] Flatten gal took : 586 ms
[2023-03-16 07:01:55] [INFO ] Flatten gal took : 658 ms
[2023-03-16 07:01:56] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 85 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 87 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 07:01:57] [INFO ] Flatten gal took : 583 ms
[2023-03-16 07:01:58] [INFO ] Flatten gal took : 671 ms
[2023-03-16 07:01:59] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 347 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 352 ms. Remains : 626/627 places, 31352/31353 transitions.
[2023-03-16 07:02:00] [INFO ] Flatten gal took : 573 ms
[2023-03-16 07:02:01] [INFO ] Flatten gal took : 702 ms
[2023-03-16 07:02:03] [INFO ] Input system was already deterministic with 31352 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 76 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 76 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 07:02:03] [INFO ] Flatten gal took : 586 ms
[2023-03-16 07:02:04] [INFO ] Flatten gal took : 730 ms
[2023-03-16 07:02:06] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 76 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 76 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 07:02:06] [INFO ] Flatten gal took : 552 ms
[2023-03-16 07:02:07] [INFO ] Flatten gal took : 648 ms
[2023-03-16 07:02:08] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 202 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 203 ms. Remains : 626/627 places, 31352/31353 transitions.
[2023-03-16 07:02:09] [INFO ] Flatten gal took : 544 ms
[2023-03-16 07:02:10] [INFO ] Flatten gal took : 630 ms
[2023-03-16 07:02:11] [INFO ] Input system was already deterministic with 31352 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 302 ms. (steps per millisecond=33 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 26117 steps, run timeout after 3001 ms. (steps per millisecond=8 ) properties seen :{}
Probabilistic random walk after 26117 steps, saw 23675 distinct states, run finished after 3005 ms. (steps per millisecond=8 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-16 07:02:15] [INFO ] Flow matrix only has 18325 transitions (discarded 13027 similar events)
// Phase 1: matrix 18325 rows 626 cols
[2023-03-16 07:02:15] [INFO ] Computed 13 place invariants in 94 ms
[2023-03-16 07:02:15] [INFO ] [Real]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 07:02:32] [INFO ] After 17118ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-16 07:02:32] [INFO ] [Nat]Absence check using 13 positive place invariants in 6 ms returned sat
[2023-03-16 07:02:50] [INFO ] After 18294ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-16 07:02:50] [INFO ] State equation strengthened by 268 read => feed constraints.
[2023-03-16 07:02:55] [INFO ] After 4627ms SMT Verify possible using 268 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-16 07:02:56] [INFO ] Deduced a trap composed of 24 places in 769 ms of which 9 ms to minimize.
[2023-03-16 07:02:57] [INFO ] Deduced a trap composed of 40 places in 563 ms of which 0 ms to minimize.
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.refineWithTraps(DeadlockTester.java:1255)
at fr.lip6.move.gal.structural.smt.DeadlockTester.refineResultsWithTraps(DeadlockTester.java:736)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:656)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:350)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:669)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-16 07:02:57] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-16 07:02:57] [INFO ] After 25312ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0 real:1
Parikh walk visited 0 properties in 6 ms.
Support contains 2 out of 626 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 626/626 places, 31352/31352 transitions.
Applied a total of 0 rules in 197 ms. Remains 626 /626 variables (removed 0) and now considering 31352/31352 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 199 ms. Remains : 626/626 places, 31352/31352 transitions.
Finished random walk after 8544 steps, including 0 resets, run visited all 2 properties in 440 ms. (steps per millisecond=19 )
Interrupted random walk after 656206 steps, including 1 resets, run timeout after 30001 ms. (steps per millisecond=21 ) properties seen 0
Finished Best-First random walk after 349563 steps, including 1 resets, run visited all 1 properties in 829 ms. (steps per millisecond=421 )
FORMULA RERS17pb113-PT-9-CTLFireability-05 TRUE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 82 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 82 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 07:03:30] [INFO ] Flatten gal took : 592 ms
[2023-03-16 07:03:30] [INFO ] Flatten gal took : 725 ms
[2023-03-16 07:03:32] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 87 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 88 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 07:03:33] [INFO ] Flatten gal took : 618 ms
[2023-03-16 07:03:33] [INFO ] Flatten gal took : 731 ms
[2023-03-16 07:03:35] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 203 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 204 ms. Remains : 626/627 places, 31352/31353 transitions.
[2023-03-16 07:03:36] [INFO ] Flatten gal took : 553 ms
[2023-03-16 07:03:37] [INFO ] Flatten gal took : 677 ms
[2023-03-16 07:03:38] [INFO ] Input system was already deterministic with 31352 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 81 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 82 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 07:03:39] [INFO ] Flatten gal took : 580 ms
[2023-03-16 07:03:40] [INFO ] Flatten gal took : 698 ms
[2023-03-16 07:03:41] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 176 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 177 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 07:03:42] [INFO ] Flatten gal took : 593 ms
[2023-03-16 07:03:43] [INFO ] Flatten gal took : 692 ms
[2023-03-16 07:03:44] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 74 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 75 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 07:03:45] [INFO ] Flatten gal took : 540 ms
[2023-03-16 07:03:46] [INFO ] Flatten gal took : 649 ms
[2023-03-16 07:03:47] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 78 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 79 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 07:03:48] [INFO ] Flatten gal took : 574 ms
[2023-03-16 07:03:49] [INFO ] Flatten gal took : 665 ms
[2023-03-16 07:03:50] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 73 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 74 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 07:03:51] [INFO ] Flatten gal took : 576 ms
[2023-03-16 07:03:52] [INFO ] Flatten gal took : 680 ms
[2023-03-16 07:03:53] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in LTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Applied a total of 0 rules in 74 ms. Remains 627 /627 variables (removed 0) and now considering 31353/31353 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 74 ms. Remains : 627/627 places, 31353/31353 transitions.
[2023-03-16 07:03:54] [INFO ] Flatten gal took : 542 ms
[2023-03-16 07:03:55] [INFO ] Flatten gal took : 638 ms
[2023-03-16 07:03:56] [INFO ] Input system was already deterministic with 31353 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 627/627 places, 31353/31353 transitions.
Reduce places removed 1 places and 1 transitions.
Applied a total of 0 rules in 195 ms. Remains 626 /627 variables (removed 1) and now considering 31352/31353 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 196 ms. Remains : 626/627 places, 31352/31353 transitions.
[2023-03-16 07:03:57] [INFO ] Flatten gal took : 575 ms
[2023-03-16 07:03:58] [INFO ] Flatten gal took : 667 ms
[2023-03-16 07:03:59] [INFO ] Input system was already deterministic with 31352 transitions.
[2023-03-16 07:04:00] [INFO ] Flatten gal took : 634 ms
[2023-03-16 07:04:00] [INFO ] Flatten gal took : 689 ms
[2023-03-16 07:04:00] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-16 07:04:01] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 627 places, 31353 transitions and 125406 arcs took 96 ms.
Total runtime 267374 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT RERS17pb113-PT-9
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/367
CTLFireability

BK_STOP 1678950745975

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/367/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/367/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/367/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 39 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 44 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 49 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 54 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 59 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 64 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 69 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 11.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 74 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 79 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 84 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 89 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 94 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 99 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 104 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 11.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 109 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 114 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 119 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 124 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 129 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 134 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 139 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 11.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 144 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 149 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 154 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 159 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 164 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 169 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 174 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 12.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 179 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 184 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 11.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 189 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 194 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 199 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 204 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 209 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 12.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 214 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 219 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 11.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 224 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 229 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 234 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 239 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 244 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 249 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 254 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 259 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 264 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 269 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 274 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 279 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 284 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 289 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 294 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 299 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 304 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 309 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 314 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 319 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 324 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 329 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 334 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 339 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 119.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 344 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 349 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 354 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 359 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 364 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 369 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 374 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 379 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 384 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 389 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 394 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 399 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 404 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 409 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 414 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 74.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 419 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 424 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 429 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 434 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 441 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 446 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 451 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 457 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 462 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 468 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 1 0 0 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 473 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: LAUNCH task # 27 (type EXCL) for 24 RERS17pb113-PT-9-CTLFireability-09
lola: time limit : 173 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 1 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 1 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 0/173 1/32 RERS17pb113-PT-9-CTLFireability-09 983 m, 196 m/sec, 983 t fired, .

Time elapsed: 478 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 1 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 1 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 5/173 1/32 RERS17pb113-PT-9-CTLFireability-09 6685 m, 1140 m/sec, 6685 t fired, .

Time elapsed: 483 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 1 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 1 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 10/173 1/32 RERS17pb113-PT-9-CTLFireability-09 13106 m, 1284 m/sec, 13137 t fired, .

Time elapsed: 488 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-9-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-09: DISJ 0 0 1 0 3 0 0 0
RERS17pb113-PT-9-CTLFireability-10: CONJ 0 1 0 0 2 0 0 0
RERS17pb113-PT-9-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-12: CTL 1 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
RERS17pb113-PT-9-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 15/173 1/32 RERS17pb113-PT-9-CTLFireability-09 18243 m, 1027 m/sec, 18335 t fired, .

Time elapsed: 493 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 15
/home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin//../BenchKit_head.sh: line 63: 523 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb113-PT-9"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is RERS17pb113-PT-9, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r327-tall-167889199100066"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb113-PT-9.tgz
mv RERS17pb113-PT-9 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;