fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r326-tall-167889198800767
Last Updated
May 14, 2023

About the Execution of LoLA for ResAllocation-PT-R050C002

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
1960.752 36866.00 146121.00 32.30 TTFFFTFTTTTTFFTT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r326-tall-167889198800767.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is ResAllocation-PT-R050C002, examination is ReachabilityFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r326-tall-167889198800767
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 704K
-rw-r--r-- 1 mcc users 6.6K Feb 25 15:30 CTLCardinality.txt
-rw-r--r-- 1 mcc users 65K Feb 25 15:30 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 25 15:29 CTLFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 25 15:29 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:45 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:45 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:45 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:45 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 25 15:32 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 167K Feb 25 15:32 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.1K Feb 25 15:31 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 64K Feb 25 15:31 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:45 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:45 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 9 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 212K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R050C002-ReachabilityFireability-00
FORMULA_NAME ResAllocation-PT-R050C002-ReachabilityFireability-01
FORMULA_NAME ResAllocation-PT-R050C002-ReachabilityFireability-02
FORMULA_NAME ResAllocation-PT-R050C002-ReachabilityFireability-03
FORMULA_NAME ResAllocation-PT-R050C002-ReachabilityFireability-04
FORMULA_NAME ResAllocation-PT-R050C002-ReachabilityFireability-05
FORMULA_NAME ResAllocation-PT-R050C002-ReachabilityFireability-06
FORMULA_NAME ResAllocation-PT-R050C002-ReachabilityFireability-07
FORMULA_NAME ResAllocation-PT-R050C002-ReachabilityFireability-08
FORMULA_NAME ResAllocation-PT-R050C002-ReachabilityFireability-09
FORMULA_NAME ResAllocation-PT-R050C002-ReachabilityFireability-10
FORMULA_NAME ResAllocation-PT-R050C002-ReachabilityFireability-11
FORMULA_NAME ResAllocation-PT-R050C002-ReachabilityFireability-12
FORMULA_NAME ResAllocation-PT-R050C002-ReachabilityFireability-13
FORMULA_NAME ResAllocation-PT-R050C002-ReachabilityFireability-14
FORMULA_NAME ResAllocation-PT-R050C002-ReachabilityFireability-15

=== Now, execution of the tool begins

BK_START 1679078415838

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=ReachabilityFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ResAllocation-PT-R050C002
Not applying reductions.
Model is PT
ReachabilityFireability PT
starting LoLA
BK_INPUT ResAllocation-PT-R050C002
BK_EXAMINATION: ReachabilityFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
ReachabilityFireability

FORMULA ResAllocation-PT-R050C002-ReachabilityFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-ReachabilityFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-ReachabilityFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-ReachabilityFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-ReachabilityFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-ReachabilityFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-ReachabilityFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-ReachabilityFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-ReachabilityFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-ReachabilityFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-ReachabilityFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-ReachabilityFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-ReachabilityFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-ReachabilityFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-ReachabilityFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R050C002-ReachabilityFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679078452704

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityFireability.xml
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 62 (type EXCL) for 6 ResAllocation-PT-R050C002-ReachabilityFireability-02
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 75 (type FNDP) for 30 ResAllocation-PT-R050C002-ReachabilityFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 76 (type EQUN) for 30 ResAllocation-PT-R050C002-ReachabilityFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 78 (type SRCH) for 30 ResAllocation-PT-R050C002-ReachabilityFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 75 (type FNDP) for ResAllocation-PT-R050C002-ReachabilityFireability-10
lola: result : true
lola: fired transitions : 45
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: CANCELED task # 76 (type EQUN) for ResAllocation-PT-R050C002-ReachabilityFireability-10 (obsolete)
lola: CANCELED task # 78 (type SRCH) for ResAllocation-PT-R050C002-ReachabilityFireability-10 (obsolete)
lola: LAUNCH task # 58 (type FNDP) for 24 ResAllocation-PT-R050C002-ReachabilityFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type EQUN) for 24 ResAllocation-PT-R050C002-ReachabilityFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 82 (type SRCH) for 24 ResAllocation-PT-R050C002-ReachabilityFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 58 (type FNDP) for ResAllocation-PT-R050C002-ReachabilityFireability-08
lola: result : true
lola: fired transitions : 79
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 59 (type EQUN) for ResAllocation-PT-R050C002-ReachabilityFireability-08 (obsolete)
lola: CANCELED task # 82 (type SRCH) for ResAllocation-PT-R050C002-ReachabilityFireability-08 (obsolete)
lola: LAUNCH task # 56 (type FNDP) for 12 ResAllocation-PT-R050C002-ReachabilityFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type EQUN) for 12 ResAllocation-PT-R050C002-ReachabilityFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 103 (type SRCH) for 12 ResAllocation-PT-R050C002-ReachabilityFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 56 (type FNDP) for ResAllocation-PT-R050C002-ReachabilityFireability-04
lola: result : true
lola: fired transitions : 56
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 103 (type SRCH) for ResAllocation-PT-R050C002-ReachabilityFireability-04
lola: result : true
lola: markings : 58
lola: fired transitions : 57
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 57 (type EQUN) for ResAllocation-PT-R050C002-ReachabilityFireability-04 (obsolete)
lola: LAUNCH task # 92 (type FNDP) for 15 ResAllocation-PT-R050C002-ReachabilityFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 93 (type EQUN) for 15 ResAllocation-PT-R050C002-ReachabilityFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 95 (type SRCH) for 15 ResAllocation-PT-R050C002-ReachabilityFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 95 (type SRCH) for ResAllocation-PT-R050C002-ReachabilityFireability-05
lola: result : true
lola: markings : 39
lola: fired transitions : 38
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 92 (type FNDP) for ResAllocation-PT-R050C002-ReachabilityFireability-05 (obsolete)
lola: CANCELED task # 93 (type EQUN) for ResAllocation-PT-R050C002-ReachabilityFireability-05 (obsolete)
lola: LAUNCH task # 52 (type FNDP) for 0 ResAllocation-PT-R050C002-ReachabilityFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 53 (type EQUN) for 0 ResAllocation-PT-R050C002-ReachabilityFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 72 (type SRCH) for 0 ResAllocation-PT-R050C002-ReachabilityFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 92 (type FNDP) for ResAllocation-PT-R050C002-ReachabilityFireability-05
lola: result : true
lola: fired transitions : 37
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 72 (type SRCH) for ResAllocation-PT-R050C002-ReachabilityFireability-00
lola: result : true
lola: markings : 40
lola: fired transitions : 39
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 52 (type FNDP) for ResAllocation-PT-R050C002-ReachabilityFireability-00 (obsolete)
lola: CANCELED task # 53 (type EQUN) for ResAllocation-PT-R050C002-ReachabilityFireability-00 (obsolete)
lola: LAUNCH task # 65 (type FNDP) for 18 ResAllocation-PT-R050C002-ReachabilityFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 66 (type EQUN) for 18 ResAllocation-PT-R050C002-ReachabilityFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-93.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 68 (type SRCH) for 18 ResAllocation-PT-R050C002-ReachabilityFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 53 (type EQUN) for ResAllocation-PT-R050C002-ReachabilityFireability-00
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: result : unknown
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-57.sara.
sara: place or transition ordering is non-deterministic

sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 52 (type FNDP) for ResAllocation-PT-R050C002-ReachabilityFireability-00
lola: result : true
lola: fired transitions : 38
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 93 (type EQUN) for ResAllocation-PT-R050C002-ReachabilityFireability-05
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 68 (type SRCH) for ResAllocation-PT-R050C002-ReachabilityFireability-06
lola: result : true
lola: markings : 28
lola: fired transitions : 27
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: CANCELED task # 65 (type FNDP) for ResAllocation-PT-R050C002-ReachabilityFireability-06 (obsolete)
lola: CANCELED task # 66 (type EQUN) for ResAllocation-PT-R050C002-ReachabilityFireability-06 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-66.sara.
lola: LAUNCH task # 107 (type FNDP) for 36 ResAllocation-PT-R050C002-ReachabilityFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 111 (type EQUN) for 36 ResAllocation-PT-R050C002-ReachabilityFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 113 (type SRCH) for 36 ResAllocation-PT-R050C002-ReachabilityFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 65 (type FNDP) for ResAllocation-PT-R050C002-ReachabilityFireability-06
lola: result : true
lola: fired transitions : 26
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: place or transition ordering is non-deterministic

lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 113 (type SRCH) for ResAllocation-PT-R050C002-ReachabilityFireability-12
lola: result : true
lola: markings : 49
lola: fired transitions : 48
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 107 (type FNDP) for ResAllocation-PT-R050C002-ReachabilityFireability-12 (obsolete)
lola: CANCELED task # 111 (type EQUN) for ResAllocation-PT-R050C002-ReachabilityFireability-12 (obsolete)
lola: LAUNCH task # 110 (type FNDP) for 42 ResAllocation-PT-R050C002-ReachabilityFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 118 (type EQUN) for 42 ResAllocation-PT-R050C002-ReachabilityFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 128 (type SRCH) for 42 ResAllocation-PT-R050C002-ReachabilityFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 107 (type FNDP) for ResAllocation-PT-R050C002-ReachabilityFireability-12
lola: result : true
lola: fired transitions : 47
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 66 (type EQUN) for ResAllocation-PT-R050C002-ReachabilityFireability-06
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 110 (type FNDP) for ResAllocation-PT-R050C002-ReachabilityFireability-14
lola: result : true
lola: fired transitions : 42
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 118 (type EQUN) for ResAllocation-PT-R050C002-ReachabilityFireability-14 (obsolete)
lola: CANCELED task # 128 (type SRCH) for ResAllocation-PT-R050C002-ReachabilityFireability-14 (obsolete)
lola: LAUNCH task # 133 (type FNDP) for 39 ResAllocation-PT-R050C002-ReachabilityFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 137 (type EQUN) for 39 ResAllocation-PT-R050C002-ReachabilityFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 141 (type SRCH) for 39 ResAllocation-PT-R050C002-ReachabilityFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-111.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 62 (type EXCL) for ResAllocation-PT-R050C002-ReachabilityFireability-02
lola: result : true
lola: markings : 27521
lola: fired transitions : 28466
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 89 (type EXCL) for 3 ResAllocation-PT-R050C002-ReachabilityFireability-01
lola: time limit : 514 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-137.sara.
sara: warning, failure of lp_solve (at job 98)
lola: FINISHED task # 89 (type EXCL) for ResAllocation-PT-R050C002-ReachabilityFireability-01
lola: result : true
lola: markings : 31486
lola: fired transitions : 32520
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 101 (type EXCL) for 9 ResAllocation-PT-R050C002-ReachabilityFireability-03
lola: time limit : 599 sec
lola: memory limit: 32 pages
lola: FINISHED task # 101 (type EXCL) for ResAllocation-PT-R050C002-ReachabilityFireability-03
lola: result : true
lola: markings : 40
lola: fired transitions : 39
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 147 (type EXCL) for 27 ResAllocation-PT-R050C002-ReachabilityFireability-09
lola: time limit : 719 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-118.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 147 (type EXCL) for ResAllocation-PT-R050C002-ReachabilityFireability-09
lola: result : true
lola: markings : 17715
lola: fired transitions : 18344
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 136 (type EXCL) for 33 ResAllocation-PT-R050C002-ReachabilityFireability-11
lola: time limit : 899 sec
lola: memory limit: 32 pages
lola: FINISHED task # 136 (type EXCL) for ResAllocation-PT-R050C002-ReachabilityFireability-11
lola: result : true
lola: markings : 30
lola: fired transitions : 29
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 131 (type EXCL) for 21 ResAllocation-PT-R050C002-ReachabilityFireability-07
lola: time limit : 1199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 131 (type EXCL) for ResAllocation-PT-R050C002-ReachabilityFireability-07
lola: result : true
lola: markings : 29
lola: fired transitions : 28
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 123 (type EXCL) for 45 ResAllocation-PT-R050C002-ReachabilityFireability-15
lola: time limit : 1799 sec
lola: memory limit: 32 pages
lola: FINISHED task # 123 (type EXCL) for ResAllocation-PT-R050C002-ReachabilityFireability-15
lola: result : true
lola: markings : 18196
lola: fired transitions : 18471
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 142 (type EXCL) for 39 ResAllocation-PT-R050C002-ReachabilityFireability-13
lola: time limit : 3598 sec
lola: memory limit: 32 pages
sara: warning, failure of lp_solve (at job 63)
sara: warning, failure of lp_solve (at job 440)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-ReachabilityFireability-00: EF true tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-01: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-02: AG false tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-03: AG false tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-04: AG false findpath
ResAllocation-PT-R050C002-ReachabilityFireability-05: EF true tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-06: AG false tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-07: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-08: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-09: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-10: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-11: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-12: AG false tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-14: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-15: EF true tandem / relaxed

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-ReachabilityFireability-13: EF 0 1 4 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
133 EF FNDP 5/1798 0/5 ResAllocation-PT-R050C002-ReachabilityFireability-13 2292223 t fired, 35545 attempts, .
137 EF STEQ 5/3598 0/5 ResAllocation-PT-R050C002-ReachabilityFireability-13 sara is running.
141 EF SRCH 5/3598 4/5 ResAllocation-PT-R050C002-ReachabilityFireability-13 1052738 m, 210547 m/sec, 2323412 t fired, .
142 EF EXCL 4/3598 1/32 ResAllocation-PT-R050C002-ReachabilityFireability-13 186700 m, 37340 m/sec, 300790 t fired, .

Time elapsed: 6 secs. Pages in use: 5
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 141 (type SRCH) for ResAllocation-PT-R050C002-ReachabilityFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-ReachabilityFireability-00: EF true tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-01: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-02: AG false tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-03: AG false tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-04: AG false findpath
ResAllocation-PT-R050C002-ReachabilityFireability-05: EF true tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-06: AG false tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-07: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-08: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-09: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-10: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-11: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-12: AG false tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-14: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-15: EF true tandem / relaxed

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-ReachabilityFireability-13: EF 0 1 3 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
133 EF FNDP 10/1794 0/5 ResAllocation-PT-R050C002-ReachabilityFireability-13 5222864 t fired, 81002 attempts, .
137 EF STEQ 10/3594 0/5 ResAllocation-PT-R050C002-ReachabilityFireability-13 sara is running.
142 EF EXCL 9/3598 2/32 ResAllocation-PT-R050C002-ReachabilityFireability-13 480694 m, 58798 m/sec, 795001 t fired, .

Time elapsed: 11 secs. Pages in use: 7
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 145 (type SRCH) for 39 ResAllocation-PT-R050C002-ReachabilityFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 145 (type SRCH) for ResAllocation-PT-R050C002-ReachabilityFireability-13
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-59.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-ReachabilityFireability-00: EF true tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-01: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-02: AG false tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-03: AG false tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-04: AG false findpath
ResAllocation-PT-R050C002-ReachabilityFireability-05: EF true tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-06: AG false tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-07: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-08: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-09: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-10: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-11: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-12: AG false tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-14: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-15: EF true tandem / relaxed

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-ReachabilityFireability-13: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
133 EF FNDP 15/3599 0/5 ResAllocation-PT-R050C002-ReachabilityFireability-13 8359655 t fired, 129630 attempts, .
137 EF STEQ 15/3599 0/5 ResAllocation-PT-R050C002-ReachabilityFireability-13 sara is running.
142 EF EXCL 14/3598 3/32 ResAllocation-PT-R050C002-ReachabilityFireability-13 772463 m, 58353 m/sec, 1312155 t fired, .

Time elapsed: 16 secs. Pages in use: 7
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-ReachabilityFireability-00: EF true tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-01: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-02: AG false tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-03: AG false tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-04: AG false findpath
ResAllocation-PT-R050C002-ReachabilityFireability-05: EF true tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-06: AG false tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-07: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-08: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-09: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-10: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-11: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-12: AG false tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-14: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-15: EF true tandem / relaxed

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-ReachabilityFireability-13: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
133 EF FNDP 20/3599 0/5 ResAllocation-PT-R050C002-ReachabilityFireability-13 11522187 t fired, 178805 attempts, .
137 EF STEQ 20/3599 0/5 ResAllocation-PT-R050C002-ReachabilityFireability-13 sara is running.
142 EF EXCL 19/3598 5/32 ResAllocation-PT-R050C002-ReachabilityFireability-13 1054181 m, 56343 m/sec, 1891558 t fired, .

Time elapsed: 21 secs. Pages in use: 7
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-ReachabilityFireability-00: EF true tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-01: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-02: AG false tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-03: AG false tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-04: AG false findpath
ResAllocation-PT-R050C002-ReachabilityFireability-05: EF true tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-06: AG false tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-07: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-08: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-09: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-10: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-11: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-12: AG false tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-14: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-15: EF true tandem / relaxed

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-ReachabilityFireability-13: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
133 EF FNDP 25/3599 0/5 ResAllocation-PT-R050C002-ReachabilityFireability-13 14682567 t fired, 227928 attempts, .
137 EF STEQ 25/3599 0/5 ResAllocation-PT-R050C002-ReachabilityFireability-13 sara is running.
142 EF EXCL 24/3598 6/32 ResAllocation-PT-R050C002-ReachabilityFireability-13 1354615 m, 60086 m/sec, 2409760 t fired, .

Time elapsed: 26 secs. Pages in use: 7
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-ReachabilityFireability-00: EF true tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-01: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-02: AG false tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-03: AG false tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-04: AG false findpath
ResAllocation-PT-R050C002-ReachabilityFireability-05: EF true tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-06: AG false tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-07: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-08: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-09: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-10: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-11: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-12: AG false tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-14: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-15: EF true tandem / relaxed

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-ReachabilityFireability-13: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
133 EF FNDP 30/3599 0/5 ResAllocation-PT-R050C002-ReachabilityFireability-13 17840677 t fired, 277026 attempts, .
137 EF STEQ 30/3599 0/5 ResAllocation-PT-R050C002-ReachabilityFireability-13 sara is running.
142 EF EXCL 29/3598 7/32 ResAllocation-PT-R050C002-ReachabilityFireability-13 1652392 m, 59555 m/sec, 3015850 t fired, .

Time elapsed: 31 secs. Pages in use: 7
# running tasks: 3 of 4 Visible: 16
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-76.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-ReachabilityFireability-00: EF true tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-01: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-02: AG false tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-03: AG false tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-04: AG false findpath
ResAllocation-PT-R050C002-ReachabilityFireability-05: EF true tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-06: AG false tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-07: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-08: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-09: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-10: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-11: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-12: AG false tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-14: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-15: EF true tandem / relaxed

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R050C002-ReachabilityFireability-13: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
133 EF FNDP 35/3599 0/5 ResAllocation-PT-R050C002-ReachabilityFireability-13 20950137 t fired, 325322 attempts, .
137 EF STEQ 35/3599 0/5 ResAllocation-PT-R050C002-ReachabilityFireability-13 sara is running.
142 EF EXCL 34/3598 8/32 ResAllocation-PT-R050C002-ReachabilityFireability-13 1916396 m, 52800 m/sec, 3709289 t fired, .

Time elapsed: 36 secs. Pages in use: 8
# running tasks: 3 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 142 (type EXCL) for ResAllocation-PT-R050C002-ReachabilityFireability-13
lola: result : false
lola: markings : 1986275
lola: fired transitions : 3873359
lola: time used : 35.000000
lola: memory pages used : 8
lola: CANCELED task # 133 (type FNDP) for ResAllocation-PT-R050C002-ReachabilityFireability-13 (obsolete)
lola: CANCELED task # 137 (type EQUN) for ResAllocation-PT-R050C002-ReachabilityFireability-13 (obsolete)
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R050C002-ReachabilityFireability-00: EF true tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-01: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-02: AG false tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-03: AG false tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-04: AG false findpath
ResAllocation-PT-R050C002-ReachabilityFireability-05: EF true tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-06: AG false tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-07: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-08: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-09: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-10: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-11: EF true tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-12: AG false tandem / insertion
ResAllocation-PT-R050C002-ReachabilityFireability-13: EF false tandem / relaxed
ResAllocation-PT-R050C002-ReachabilityFireability-14: EF true findpath
ResAllocation-PT-R050C002-ReachabilityFireability-15: EF true tandem / relaxed


Time elapsed: 37 secs. Pages in use: 8

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R050C002"
export BK_EXAMINATION="ReachabilityFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is ResAllocation-PT-R050C002, examination is ReachabilityFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r326-tall-167889198800767"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R050C002.tgz
mv ResAllocation-PT-R050C002 execution
cd execution
if [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "UpperBounds" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] || [ "ReachabilityFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;