fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r326-tall-167889198600618
Last Updated
May 14, 2023

About the Execution of LoLA for RefineWMG-PT-025026

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
5517.163 75349.00 66940.00 262.40 ?TT?F??TFFFTTTTT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r326-tall-167889198600618.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is RefineWMG-PT-025026, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r326-tall-167889198600618
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 512K
-rw-r--r-- 1 mcc users 7.3K Feb 26 16:06 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K Feb 26 16:06 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.6K Feb 26 16:06 CTLFireability.txt
-rw-r--r-- 1 mcc users 39K Feb 26 16:06 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:43 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 16:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 16:43 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 26 16:08 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 110K Feb 26 16:08 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.5K Feb 26 16:07 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 86K Feb 26 16:07 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 56K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-00
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-01
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-02
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-03
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-04
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-05
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-06
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-07
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-08
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-09
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-10
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-11
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-12
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-13
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-14
FORMULA_NAME RefineWMG-PT-025026-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679069662857

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RefineWMG-PT-025026
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT RefineWMG-PT-025026
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA RefineWMG-PT-025026-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RefineWMG-PT-025026-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RefineWMG-PT-025026-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RefineWMG-PT-025026-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RefineWMG-PT-025026-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RefineWMG-PT-025026-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RefineWMG-PT-025026-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RefineWMG-PT-025026-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RefineWMG-PT-025026-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RefineWMG-PT-025026-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RefineWMG-PT-025026-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA RefineWMG-PT-025026-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679069738206

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: LAUNCH task # 4 (type EXCL) for 3 RefineWMG-PT-025026-CTLFireability-01
lola: time limit : 143 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 72 (type FNDP) for 6 RefineWMG-PT-025026-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type EQUN) for 6 RefineWMG-PT-025026-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type SRCH) for 6 RefineWMG-PT-025026-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 75 (type SRCH) for RefineWMG-PT-025026-CTLFireability-02
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 72 (type FNDP) for RefineWMG-PT-025026-CTLFireability-02
lola: result : true
lola: fired transitions : 25
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 73 (type EQUN) for RefineWMG-PT-025026-CTLFireability-02 (obsolete)
lola: FINISHED task # 73 (type EQUN) for RefineWMG-PT-025026-CTLFireability-02
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
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lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 79 (type FNDP) for 39 RefineWMG-PT-025026-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 80 (type EQUN) for 39 RefineWMG-PT-025026-CTLFireability-09
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 82 (type SRCH) for 39 RefineWMG-PT-025026-CTLFireability-09
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lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 82 (type SRCH) for RefineWMG-PT-025026-CTLFireability-09
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 79 (type FNDP) for RefineWMG-PT-025026-CTLFireability-09
lola: result : true
lola: fired transitions : 25
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 80 (type EQUN) for RefineWMG-PT-025026-CTLFireability-09 (obsolete)
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: FINISHED task # 80 (type EQUN) for RefineWMG-PT-025026-CTLFireability-09
lola: result : unknown
lola: FINISHED task # 4 (type EXCL) for RefineWMG-PT-025026-CTLFireability-01
lola: result : true
lola: markings : 17825
lola: fired transitions : 33789
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 83 (type EXCL) for 46 RefineWMG-PT-025026-CTLFireability-10
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 83 (type EXCL) for RefineWMG-PT-025026-CTLFireability-10
lola: result : true
lola: markings : 27
lola: fired transitions : 26
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 70 (type EXCL) for 69 RefineWMG-PT-025026-CTLFireability-15
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 70 (type EXCL) for RefineWMG-PT-025026-CTLFireability-15
lola: result : true
lola: markings : 1456
lola: fired transitions : 1596
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 67 (type EXCL) for 66 RefineWMG-PT-025026-CTLFireability-14
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 67 (type EXCL) for RefineWMG-PT-025026-CTLFireability-14
lola: result : true
lola: markings : 26
lola: fired transitions : 25
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 64 (type EXCL) for 63 RefineWMG-PT-025026-CTLFireability-13
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: FINISHED task # 64 (type EXCL) for RefineWMG-PT-025026-CTLFireability-13
lola: result : true
lola: markings : 26
lola: fired transitions : 77
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 61 (type EXCL) for 60 RefineWMG-PT-025026-CTLFireability-12
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 61 (type EXCL) for RefineWMG-PT-025026-CTLFireability-12
lola: result : true
lola: markings : 288
lola: fired transitions : 638
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 58 (type EXCL) for 53 RefineWMG-PT-025026-CTLFireability-11
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type EXCL) for RefineWMG-PT-025026-CTLFireability-11
lola: result : true
lola: markings : 486
lola: fired transitions : 886
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 56 (type EXCL) for 53 RefineWMG-PT-025026-CTLFireability-11
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for RefineWMG-PT-025026-CTLFireability-11
lola: result : true
lola: markings : 26
lola: fired transitions : 51
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 51 (type EXCL) for 46 RefineWMG-PT-025026-CTLFireability-10
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for RefineWMG-PT-025026-CTLFireability-10
lola: result : false
lola: markings : 2466
lola: fired transitions : 4325
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 RefineWMG-PT-025026-CTLFireability-07
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for RefineWMG-PT-025026-CTLFireability-07
lola: result : true
lola: markings : 2032
lola: fired transitions : 2732
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 RefineWMG-PT-025026-CTLFireability-06
lola: time limit : 399 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-025026-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-025026-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-02: DISJ 0 2 0 0 6 0 0 1
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 4/399 6/32 RefineWMG-PT-025026-CTLFireability-06 945729 m, 189145 m/sec, 2709572 t fired, .

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RefineWMG-PT-025026-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker

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RefineWMG-PT-025026-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-02: DISJ 0 2 0 0 6 0 0 1
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 9/399 12/32 RefineWMG-PT-025026-CTLFireability-06 1924710 m, 195796 m/sec, 5138517 t fired, .

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RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker

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RefineWMG-PT-025026-CTLFireability-02: DISJ 0 2 0 0 6 0 0 1
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 14/399 18/32 RefineWMG-PT-025026-CTLFireability-06 2904692 m, 195996 m/sec, 7569213 t fired, .

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RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
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RefineWMG-PT-025026-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 19/399 24/32 RefineWMG-PT-025026-CTLFireability-06 3874145 m, 193890 m/sec, 9974152 t fired, .

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RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker

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RefineWMG-PT-025026-CTLFireability-02: DISJ 0 2 0 0 6 0 0 1
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 24/399 30/32 RefineWMG-PT-025026-CTLFireability-06 4857395 m, 196650 m/sec, 12413100 t fired, .

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RefineWMG-PT-025026-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker

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RefineWMG-PT-025026-CTLFireability-02: DISJ 0 2 0 0 6 0 0 1
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-025026-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
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RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
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RefineWMG-PT-025026-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/446 12/32 RefineWMG-PT-025026-CTLFireability-05 1899218 m, 379843 m/sec, 4710708 t fired, .

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RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
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RefineWMG-PT-025026-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/446 24/32 RefineWMG-PT-025026-CTLFireability-05 3776143 m, 375385 m/sec, 9366739 t fired, .

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RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
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RefineWMG-PT-025026-CTLFireability-02: DISJ 0 2 0 0 6 0 0 1
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0

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lola: result : false
lola: time used : 0.000000
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RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
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RefineWMG-PT-025026-CTLFireability-02: DISJ 0 1 0 0 7 0 0 1
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/711 13/32 RefineWMG-PT-025026-CTLFireability-00 2354184 m, 470836 m/sec, 3159443 t fired, .

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RefineWMG-PT-025026-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-025026-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-02: DISJ 0 1 0 0 7 0 0 1
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/711 26/32 RefineWMG-PT-025026-CTLFireability-00 4633641 m, 455891 m/sec, 6202393 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-025026-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RefineWMG-PT-025026-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-02: DISJ 0 1 0 0 7 0 0 1
RefineWMG-PT-025026-CTLFireability-03: DISJ 0 1 0 0 3 0 0 0
RefineWMG-PT-025026-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-08: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 76 (type EXCL) for 24 RefineWMG-PT-025026-CTLFireability-04
lola: time limit : 885 sec
lola: memory limit: 32 pages
lola: FINISHED task # 76 (type EXCL) for RefineWMG-PT-025026-CTLFireability-04
lola: result : true
lola: markings : 432
lola: fired transitions : 1044
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 RefineWMG-PT-025026-CTLFireability-08
lola: time limit : 1180 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for RefineWMG-PT-025026-CTLFireability-08
lola: result : false
lola: markings : 7
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 77 (type EXCL) for 6 RefineWMG-PT-025026-CTLFireability-02
lola: time limit : 1770 sec
lola: memory limit: 32 pages
lola: FINISHED task # 77 (type EXCL) for RefineWMG-PT-025026-CTLFireability-02
lola: result : true
lola: markings : 205353
lola: fired transitions : 943038
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 20 (type EXCL) for 17 RefineWMG-PT-025026-CTLFireability-03
lola: time limit : 3539 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-025026-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-02: DISJ true LTL model checker
RefineWMG-PT-025026-CTLFireability-04: EFAG false tscc_search
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-08: AFAG false CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RefineWMG-PT-025026-CTLFireability-03: DISJ 0 0 1 0 3 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 4/3539 13/32 RefineWMG-PT-025026-CTLFireability-03 3013832 m, 602766 m/sec, 11128877 t fired, .

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RefineWMG-PT-025026-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-02: DISJ true LTL model checker
RefineWMG-PT-025026-CTLFireability-04: EFAG false tscc_search
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-08: AFAG false CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RefineWMG-PT-025026-CTLFireability-03: DISJ 0 0 1 0 3 0 0 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 9/3539 26/32 RefineWMG-PT-025026-CTLFireability-03 6187001 m, 634633 m/sec, 22854353 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-025026-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-02: DISJ true LTL model checker
RefineWMG-PT-025026-CTLFireability-04: EFAG false tscc_search
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-08: AFAG false CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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RefineWMG-PT-025026-CTLFireability-03: DISJ 0 0 0 0 3 0 1 0
RefineWMG-PT-025026-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
RefineWMG-PT-025026-CTLFireability-06: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RefineWMG-PT-025026-CTLFireability-00: CTL unknown AGGR
RefineWMG-PT-025026-CTLFireability-01: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-02: DISJ true LTL model checker
RefineWMG-PT-025026-CTLFireability-03: DISJ unknown DISJ
RefineWMG-PT-025026-CTLFireability-04: EFAG false tscc_search
RefineWMG-PT-025026-CTLFireability-05: CTL unknown AGGR
RefineWMG-PT-025026-CTLFireability-06: CTL unknown AGGR
RefineWMG-PT-025026-CTLFireability-07: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-08: AFAG false CTL model checker
RefineWMG-PT-025026-CTLFireability-09: CONJ false findpath
RefineWMG-PT-025026-CTLFireability-10: DISJ false DISJ
RefineWMG-PT-025026-CTLFireability-11: CONJ true CONJ
RefineWMG-PT-025026-CTLFireability-12: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-13: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-14: CTL true CTL model checker
RefineWMG-PT-025026-CTLFireability-15: CTL true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RefineWMG-PT-025026"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is RefineWMG-PT-025026, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r326-tall-167889198600618"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RefineWMG-PT-025026.tgz
mv RefineWMG-PT-025026 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;