fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r326-tall-167889198300370
Last Updated
May 14, 2023

About the Execution of LoLA for Railroad-PT-010

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
907.191 93734.00 95152.00 478.80 FTTFFFFFTFTTFFTF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r326-tall-167889198300370.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is Railroad-PT-010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r326-tall-167889198300370
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 604K
-rw-r--r-- 1 mcc users 9.0K Feb 25 22:26 CTLCardinality.txt
-rw-r--r-- 1 mcc users 98K Feb 25 22:26 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Feb 25 22:25 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 25 22:25 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Feb 25 16:41 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:41 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:41 LTLFireability.txt
-rw-r--r-- 1 mcc users 14K Feb 25 16:41 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Feb 25 22:27 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 148K Feb 25 22:27 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 22:27 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Feb 25 22:27 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:41 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:41 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 82K Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Railroad-PT-010-CTLFireability-00
FORMULA_NAME Railroad-PT-010-CTLFireability-01
FORMULA_NAME Railroad-PT-010-CTLFireability-02
FORMULA_NAME Railroad-PT-010-CTLFireability-03
FORMULA_NAME Railroad-PT-010-CTLFireability-04
FORMULA_NAME Railroad-PT-010-CTLFireability-05
FORMULA_NAME Railroad-PT-010-CTLFireability-06
FORMULA_NAME Railroad-PT-010-CTLFireability-07
FORMULA_NAME Railroad-PT-010-CTLFireability-08
FORMULA_NAME Railroad-PT-010-CTLFireability-09
FORMULA_NAME Railroad-PT-010-CTLFireability-10
FORMULA_NAME Railroad-PT-010-CTLFireability-11
FORMULA_NAME Railroad-PT-010-CTLFireability-12
FORMULA_NAME Railroad-PT-010-CTLFireability-13
FORMULA_NAME Railroad-PT-010-CTLFireability-14
FORMULA_NAME Railroad-PT-010-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679040054009

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Railroad-PT-010
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT Railroad-PT-010
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA Railroad-PT-010-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Railroad-PT-010-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679040147743

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:114
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:114
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:182
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 10 transitions removed,31 places removed
lola: LAUNCH INITIAL
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 50 (type CNST) for 49 Railroad-PT-010-CTLFireability-15
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 50 (type CNST) for Railroad-PT-010-CTLFireability-15
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 44 (type CNST) for 43 Railroad-PT-010-CTLFireability-13
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 44 (type CNST) for Railroad-PT-010-CTLFireability-13
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 10 (type EXCL) for 9 Railroad-PT-010-CTLFireability-03
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 53 (type FNDP) for 33 Railroad-PT-010-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type EQUN) for 33 Railroad-PT-010-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type SRCH) for 33 Railroad-PT-010-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 56 (type SRCH) for Railroad-PT-010-CTLFireability-11
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 53 (type FNDP) for Railroad-PT-010-CTLFireability-11
lola: result : true
lola: fired transitions : 10
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: CANCELED task # 54 (type EQUN) for Railroad-PT-010-CTLFireability-11 (obsolete)
sara: try reading problem file /home/mcc/execution/CTLFireability-54.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 54 (type EQUN) for Railroad-PT-010-CTLFireability-11
lola: result : true
lola: FINISHED task # 10 (type EXCL) for Railroad-PT-010-CTLFireability-03
lola: result : false
lola: markings : 276543
lola: fired transitions : 2619972
lola: time used : 2.000000
lola: memory pages used : 2
lola: LAUNCH task # 41 (type EXCL) for 40 Railroad-PT-010-CTLFireability-12
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for Railroad-PT-010-CTLFireability-12
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 Railroad-PT-010-CTLFireability-06
lola: time limit : 299 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-05: EFEG 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Railroad-PT-010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-11: CONJ 0 1 0 0 5 0 0 1
Railroad-PT-010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 3/299 3/32 Railroad-PT-010-CTLFireability-06 594299 m, 118859 m/sec, 2404530 t fired, .

Time elapsed: 5 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-05: EFEG 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Railroad-PT-010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-11: CONJ 0 1 0 0 5 0 0 1
Railroad-PT-010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 8/299 5/32 Railroad-PT-010-CTLFireability-06 1172658 m, 115671 m/sec, 5832952 t fired, .

Time elapsed: 10 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-05: EFEG 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Railroad-PT-010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-11: CONJ 0 1 0 0 5 0 0 1
Railroad-PT-010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 13/299 7/32 Railroad-PT-010-CTLFireability-06 1659310 m, 97330 m/sec, 8947887 t fired, .

Time elapsed: 15 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-05: EFEG 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Railroad-PT-010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-11: CONJ 0 1 0 0 5 0 0 1
Railroad-PT-010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 18/299 9/32 Railroad-PT-010-CTLFireability-06 2037632 m, 75664 m/sec, 12744808 t fired, .

Time elapsed: 20 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-05: EFEG 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Railroad-PT-010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-11: CONJ 0 1 0 0 5 0 0 1
Railroad-PT-010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 23/299 9/32 Railroad-PT-010-CTLFireability-06 2038163 m, 106 m/sec, 16830573 t fired, .

Time elapsed: 25 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 19 (type EXCL) for Railroad-PT-010-CTLFireability-06
lola: result : false
lola: markings : 2038166
lola: fired transitions : 17678105
lola: time used : 24.000000
lola: memory pages used : 9
lola: LAUNCH task # 13 (type EXCL) for 12 Railroad-PT-010-CTLFireability-04
lola: time limit : 324 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-06: CTL false CTL model checker
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Railroad-PT-010-CTLFireability-05: EFEG 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-11: CONJ 0 1 0 0 5 0 0 1
Railroad-PT-010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 4/324 4/32 Railroad-PT-010-CTLFireability-04 729509 m, 145901 m/sec, 3519638 t fired, .

Time elapsed: 30 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-06: CTL false CTL model checker
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Railroad-PT-010-CTLFireability-05: EFEG 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-11: CONJ 0 1 0 0 5 0 0 1
Railroad-PT-010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 9/324 6/32 Railroad-PT-010-CTLFireability-04 1213078 m, 96713 m/sec, 7691860 t fired, .

Time elapsed: 35 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-06: CTL false CTL model checker
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Railroad-PT-010-CTLFireability-05: EFEG 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-11: CONJ 0 1 0 0 5 0 0 1
Railroad-PT-010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 14/324 7/32 Railroad-PT-010-CTLFireability-04 1530268 m, 63438 m/sec, 11709372 t fired, .

Time elapsed: 40 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-06: CTL false CTL model checker
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Railroad-PT-010-CTLFireability-05: EFEG 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-11: CONJ 0 1 0 0 5 0 0 1
Railroad-PT-010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 19/324 8/32 Railroad-PT-010-CTLFireability-04 1748331 m, 43612 m/sec, 15652905 t fired, .

Time elapsed: 45 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-06: CTL false CTL model checker
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Railroad-PT-010-CTLFireability-05: EFEG 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-11: CONJ 0 1 0 0 5 0 0 1
Railroad-PT-010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 24/324 8/32 Railroad-PT-010-CTLFireability-04 1892424 m, 28818 m/sec, 19589355 t fired, .

Time elapsed: 50 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-06: CTL false CTL model checker
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Railroad-PT-010-CTLFireability-05: EFEG 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-11: CONJ 0 1 0 0 5 0 0 1
Railroad-PT-010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 29/324 9/32 Railroad-PT-010-CTLFireability-04 1983603 m, 18235 m/sec, 23679249 t fired, .

Time elapsed: 55 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-06: CTL false CTL model checker
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Railroad-PT-010-CTLFireability-05: EFEG 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-11: CONJ 0 1 0 0 5 0 0 1
Railroad-PT-010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 34/324 9/32 Railroad-PT-010-CTLFireability-04 2031260 m, 9531 m/sec, 28115792 t fired, .

Time elapsed: 60 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-06: CTL false CTL model checker
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Railroad-PT-010-CTLFireability-05: EFEG 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-11: CONJ 0 1 0 0 5 0 0 1
Railroad-PT-010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 39/324 9/32 Railroad-PT-010-CTLFireability-04 2038163 m, 1380 m/sec, 32547323 t fired, .

Time elapsed: 65 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 13 (type EXCL) for Railroad-PT-010-CTLFireability-04
lola: result : false
lola: markings : 2038166
lola: fired transitions : 36426068
lola: time used : 43.000000
lola: memory pages used : 9
lola: LAUNCH task # 7 (type EXCL) for 6 Railroad-PT-010-CTLFireability-02
lola: time limit : 353 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-04: CTL false CTL model checker
Railroad-PT-010-CTLFireability-06: CTL false CTL model checker
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Railroad-PT-010-CTLFireability-05: EFEG 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-11: CONJ 0 1 0 0 5 0 0 1
Railroad-PT-010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 1/353 1/32 Railroad-PT-010-CTLFireability-02 111229 m, 22245 m/sec, 407912 t fired, .

Time elapsed: 70 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-04: CTL false CTL model checker
Railroad-PT-010-CTLFireability-06: CTL false CTL model checker
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Railroad-PT-010-CTLFireability-05: EFEG 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-11: CONJ 0 1 0 0 5 0 0 1
Railroad-PT-010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 6/353 5/32 Railroad-PT-010-CTLFireability-02 1106854 m, 199125 m/sec, 4924713 t fired, .

Time elapsed: 75 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-04: CTL false CTL model checker
Railroad-PT-010-CTLFireability-06: CTL false CTL model checker
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Railroad-PT-010-CTLFireability-05: EFEG 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-11: CONJ 0 1 0 0 5 0 0 1
Railroad-PT-010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 11/353 8/32 Railroad-PT-010-CTLFireability-02 1862272 m, 151083 m/sec, 8988405 t fired, .

Time elapsed: 80 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-04: CTL false CTL model checker
Railroad-PT-010-CTLFireability-06: CTL false CTL model checker
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Railroad-PT-010-CTLFireability-05: EFEG 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-11: CONJ 0 1 0 0 5 0 0 1
Railroad-PT-010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 16/353 9/32 Railroad-PT-010-CTLFireability-02 2038083 m, 35162 m/sec, 13181244 t fired, .

Time elapsed: 85 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 7 (type EXCL) for Railroad-PT-010-CTLFireability-02
lola: result : true
lola: markings : 2038166
lola: fired transitions : 16324600
lola: time used : 19.000000
lola: memory pages used : 9
lola: LAUNCH task # 16 (type EXCL) for 15 Railroad-PT-010-CTLFireability-05
lola: time limit : 390 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for Railroad-PT-010-CTLFireability-05
lola: result : false
lola: markings : 192754
lola: fired transitions : 959342
lola: time used : 2.000000
lola: memory pages used : 1
lola: LAUNCH task # 52 (type EXCL) for 33 Railroad-PT-010-CTLFireability-11
lola: time limit : 438 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for Railroad-PT-010-CTLFireability-11
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 Railroad-PT-010-CTLFireability-07
lola: time limit : 501 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-02: CTL true CTL model checker
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-04: CTL false CTL model checker
Railroad-PT-010-CTLFireability-05: EFEG false state space /EFEG
Railroad-PT-010-CTLFireability-06: CTL false CTL model checker
Railroad-PT-010-CTLFireability-11: CONJ true CONJ
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Railroad-PT-010-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Railroad-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Railroad-PT-010-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 0/501 1/32 Railroad-PT-010-CTLFireability-07 10784 m, 2156 m/sec, 68534 t fired, .

Time elapsed: 90 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 22 (type EXCL) for Railroad-PT-010-CTLFireability-07
lola: result : false
lola: markings : 207711
lola: fired transitions : 2110074
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 Railroad-PT-010-CTLFireability-00
lola: time limit : 584 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for Railroad-PT-010-CTLFireability-00
lola: result : false
lola: markings : 2979
lola: fired transitions : 20622
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 Railroad-PT-010-CTLFireability-08
lola: time limit : 701 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for Railroad-PT-010-CTLFireability-08
lola: result : true
lola: markings : 11110
lola: fired transitions : 34494
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 Railroad-PT-010-CTLFireability-10
lola: time limit : 877 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for Railroad-PT-010-CTLFireability-10
lola: result : true
lola: markings : 618
lola: fired transitions : 2146
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 Railroad-PT-010-CTLFireability-09
lola: time limit : 1169 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for Railroad-PT-010-CTLFireability-09
lola: result : false
lola: markings : 276543
lola: fired transitions : 2950440
lola: time used : 2.000000
lola: memory pages used : 2
lola: LAUNCH task # 4 (type EXCL) for 3 Railroad-PT-010-CTLFireability-01
lola: time limit : 1753 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for Railroad-PT-010-CTLFireability-01
lola: result : true
lola: markings : 1792
lola: fired transitions : 6694
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 47 (type EXCL) for 46 Railroad-PT-010-CTLFireability-14
lola: time limit : 3507 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for Railroad-PT-010-CTLFireability-14
lola: result : true
lola: markings : 12
lola: fired transitions : 72
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Railroad-PT-010-CTLFireability-00: CTL false CTL model checker
Railroad-PT-010-CTLFireability-01: CTL true CTL model checker
Railroad-PT-010-CTLFireability-02: CTL true CTL model checker
Railroad-PT-010-CTLFireability-03: CTL false CTL model checker
Railroad-PT-010-CTLFireability-04: CTL false CTL model checker
Railroad-PT-010-CTLFireability-05: EFEG false state space /EFEG
Railroad-PT-010-CTLFireability-06: CTL false CTL model checker
Railroad-PT-010-CTLFireability-07: CTL false CTL model checker
Railroad-PT-010-CTLFireability-08: CTL true CTL model checker
Railroad-PT-010-CTLFireability-09: CTL false CTL model checker
Railroad-PT-010-CTLFireability-10: CTL true CTL model checker
Railroad-PT-010-CTLFireability-11: CONJ true CONJ
Railroad-PT-010-CTLFireability-12: CTL false CTL model checker
Railroad-PT-010-CTLFireability-13: INITIAL false preprocessing
Railroad-PT-010-CTLFireability-14: CTL true CTL model checker
Railroad-PT-010-CTLFireability-15: INITIAL false preprocessing


Time elapsed: 93 secs. Pages in use: 9

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Railroad-PT-010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is Railroad-PT-010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r326-tall-167889198300370"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Railroad-PT-010.tgz
mv Railroad-PT-010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;