fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r326-tall-167889198100186
Last Updated
May 14, 2023

About the Execution of LoLA for RERS17pb115-PT-6

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
3204.739 3600000.00 3650585.00 9213.00 [undef] Time out reached

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r326-tall-167889198100186.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is RERS17pb115-PT-6, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r326-tall-167889198100186
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 70M
-rw-r--r-- 1 mcc users 7.4K Feb 25 13:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 83K Feb 25 13:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 25 13:52 CTLFireability.txt
-rw-r--r-- 1 mcc users 43K Feb 25 13:52 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:41 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:41 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:39 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 25 16:39 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.0K Feb 25 16:39 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:39 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 14:07 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 144K Feb 25 14:07 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.5K Feb 25 14:03 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 57K Feb 25 14:03 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:39 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:39 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:23 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:23 iscolored
-rw-r--r-- 1 mcc users 69M Mar 5 18:23 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb115-PT-6-CTLFireability-00
FORMULA_NAME RERS17pb115-PT-6-CTLFireability-01
FORMULA_NAME RERS17pb115-PT-6-CTLFireability-02
FORMULA_NAME RERS17pb115-PT-6-CTLFireability-03
FORMULA_NAME RERS17pb115-PT-6-CTLFireability-04
FORMULA_NAME RERS17pb115-PT-6-CTLFireability-05
FORMULA_NAME RERS17pb115-PT-6-CTLFireability-06
FORMULA_NAME RERS17pb115-PT-6-CTLFireability-07
FORMULA_NAME RERS17pb115-PT-6-CTLFireability-08
FORMULA_NAME RERS17pb115-PT-6-CTLFireability-09
FORMULA_NAME RERS17pb115-PT-6-CTLFireability-10
FORMULA_NAME RERS17pb115-PT-6-CTLFireability-11
FORMULA_NAME RERS17pb115-PT-6-CTLFireability-12
FORMULA_NAME RERS17pb115-PT-6-CTLFireability-13
FORMULA_NAME RERS17pb115-PT-6-CTLFireability-14
FORMULA_NAME RERS17pb115-PT-6-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678995264363

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=RERS17pb115-PT-6
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT RERS17pb115-PT-6
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393232 kB
MemFree: 12932516 kB
After kill :
MemTotal: 16393232 kB
MemFree: 16088788 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 48 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 53 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 58 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 63 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 68 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 73 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 78 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 83 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 88 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 93 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 98 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 103 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 108 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 113 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 118 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 123 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 128 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 133 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 138 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 143 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 148 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 153 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 158 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 163 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 168 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 173 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 178 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 183 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 188 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 193 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 198 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 203 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 208 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 213 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 218 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 223 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 228 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 233 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 238 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 243 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 248 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 253 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 258 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 263 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 268 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 273 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 278 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 283 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 288 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 293 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 298 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 303 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 308 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 313 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 318 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 323 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 328 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 333 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 338 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 343 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 348 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 353 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 358 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 363 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 368 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 373 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 378 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 383 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 388 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 393 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 398 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 403 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 408 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 413 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 418 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 423 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 428 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 433 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 438 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 443 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 448 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 453 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 458 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 463 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 468 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 473 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 478 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 483 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 488 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 493 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 498 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 503 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 508 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 513 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 519 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 524 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 529 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 534 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 539 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 544 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 549 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 554 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 559 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 564 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 569 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 574 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 579 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 584 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 589 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 594 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 599 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 604 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 609 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 614 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 619 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 579.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 624 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 629 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 634 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 639 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 644 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 649 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 654 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 659 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 664 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 669 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 674 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 679 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 684 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 689 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 694 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 699 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 704 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 709 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 714 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 719 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 724 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 729 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 734 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 739 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 744 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 749 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 754 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 759 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 764 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 769 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 774 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 779 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 784 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 789 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 794 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 799 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 804 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 809 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 814 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 819 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 824 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 829 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 834 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 839 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 844 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 849 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 854 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 859 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 864 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 869 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 874 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 879 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 884 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 889 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 894 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 899 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 904 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 909 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 914 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 919 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 924 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 929 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 934 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 939 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 944 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 949 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 954 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 959 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 964 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 969 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 974 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 979 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 984 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 989 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 994 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 999 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1004 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1009 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1014 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1019 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1024 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1029 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1034 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1039 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1044 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1049 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1054 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1059 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1064 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1069 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1074 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1079 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1084 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1089 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1094 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1099 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1104 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1109 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1114 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1119 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1124 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1129 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1134 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1139 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 522.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1144 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1149 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1154 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1159 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1164 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1169 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1174 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1179 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1184 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1189 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1194 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1199 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1204 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1209 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1214 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1219 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1224 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1229 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1234 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1239 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1244 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1249 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1254 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1259 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1264 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1269 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1274 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1279 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1284 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1289 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1294 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1299 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1304 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1309 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1314 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1319 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1324 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1329 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1334 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1339 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1344 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1349 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1354 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1359 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1364 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1369 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1374 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1379 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1384 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1389 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1394 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1399 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1404 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1409 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1414 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1419 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1424 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1429 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1434 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1439 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1444 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1449 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1454 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1459 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1464 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1469 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1474 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1479 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1484 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1489 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1494 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1499 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1504 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1509 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1514 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1519 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1524 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1529 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1534 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1539 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1544 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1549 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1554 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1559 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1564 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1569 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1574 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1579 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1584 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1589 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1594 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1599 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1604 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1609 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1614 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1619 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1624 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1629 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1634 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1639 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1644 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1649 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1654 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1659 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1664 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1669 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1674 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1679 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1684 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1689 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1694 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1699 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1704 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 564.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1709 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1714 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1719 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1724 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1729 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1734 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1739 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1744 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1749 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1754 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1759 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1764 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1769 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1774 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1779 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1784 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1789 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1794 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1799 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1804 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1809 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1814 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1819 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1824 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1829 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1834 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1839 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1844 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1849 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1854 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1859 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1864 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1869 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1874 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1879 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1884 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1889 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1894 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1899 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1904 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1910 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1915 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1920 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1925 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1930 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1935 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1940 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1945 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1950 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1955 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1960 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1965 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1970 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1975 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1980 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1985 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1990 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1995 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2000 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2005 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2010 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2015 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2020 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2025 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2030 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2035 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2040 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2045 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2050 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2055 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2060 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2065 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2070 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2075 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2080 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2085 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2090 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2095 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2100 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2105 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2110 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2115 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2120 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2125 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2130 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2135 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2140 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2145 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2150 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2155 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2160 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2165 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2170 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2175 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2180 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2185 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2190 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2195 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2200 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2205 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2210 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2215 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2220 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2225 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2230 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2235 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2240 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2245 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2250 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2255 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2260 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2265 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2270 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 562.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2275 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2280 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2285 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2290 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2295 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2300 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2305 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2310 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2315 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2320 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2325 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2330 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2335 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2340 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2345 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2350 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2355 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2360 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2365 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2370 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2375 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2380 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2385 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2390 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2395 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2400 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2405 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2410 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2415 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2420 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2425 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2430 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2435 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2440 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2445 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2450 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2455 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2460 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2465 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2470 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2475 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2480 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2485 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2490 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2495 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2500 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2505 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2510 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2515 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2520 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2525 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2530 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2535 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2540 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2545 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2550 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2555 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2560 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2565 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2570 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2575 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2580 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2585 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2590 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2595 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2600 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2605 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2610 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2615 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2620 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2625 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2630 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2635 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2640 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2645 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2650 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2655 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2660 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2665 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2670 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2675 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2680 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2685 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2690 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2695 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2700 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2705 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2710 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2715 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2720 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2725 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2730 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2735 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2740 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2745 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2750 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2755 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2760 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2765 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2770 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2775 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2780 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2785 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2790 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2795 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2800 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2805 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2810 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2815 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2820 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2825 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2830 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2835 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2840 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2845 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2850 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2855 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2860 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2865 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2870 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2875 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2880 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2885 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2890 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2895 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2900 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2905 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2910 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2915 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2920 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2925 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2930 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 638.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2935 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2940 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2945 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2950 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2955 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2960 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2965 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2970 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2975 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2980 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2985 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2990 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 2995 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3000 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3005 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3010 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3015 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3020 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3025 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3030 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3035 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3040 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-15: CONJ 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 3045 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb115-PT-6-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-01: EF 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-03: AG 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-06: EFAGEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-07: DISJ 0 0 0 0 1 0 0 0
RERS17pb115-PT-6-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-09: EXEF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-10: EF 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
RERS17pb115-PT-6-CTLFireability-12: DISJ 0 0 0 0 0 0 0 0

========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb115-PT-6"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is RERS17pb115-PT-6, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r326-tall-167889198100186"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb115-PT-6.tgz
mv RERS17pb115-PT-6 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;